* [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage
@ 2021-03-19 8:24 ` Richard Zhu
0 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..23efbad9e804 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
Additional required properties for imx8mq-pcie:
- clock-names: Must include the following additional entries:
- "pcie_aux"
+- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW
+ schematic design. The PCIE_VPH is suggested to be 1.8v refer to the
+ data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS
+ should be cleared to zero accordingly.
Example:
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage
@ 2021-03-19 8:24 ` Richard Zhu
0 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..23efbad9e804 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
Additional required properties for imx8mq-pcie:
- clock-names: Must include the following additional entries:
- "pcie_aux"
+- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW
+ schematic design. The PCIE_VPH is suggested to be 1.8v refer to the
+ data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS
+ should be cleared to zero accordingly.
Example:
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] arm64: dts: add one property to specify the imx8mq pcie phy voltage
2021-03-19 8:24 ` Richard Zhu
@ 2021-03-19 8:24 ` Richard Zhu
-1 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 85b045253a0e..30bcf5f583e0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ pcie-vph-3v3;
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] arm64: dts: add one property to specify the imx8mq pcie phy voltage
@ 2021-03-19 8:24 ` Richard Zhu
0 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 85b045253a0e..30bcf5f583e0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ pcie-vph-3v3;
status = "okay";
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3
2021-03-19 8:24 ` Richard Zhu
@ 2021-03-19 8:24 ` Richard Zhu
-1 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..c35d5511b55b 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -37,6 +37,7 @@
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
@@ -611,6 +612,10 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
+ struct dw_pcie *pci = imx6_pcie->pci;
+ struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
+
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ:
/*
@@ -621,6 +626,16 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
imx6_pcie_grp_offset(imx6_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ /*
+ * Regarding to the datasheet, the PCIE_VPH is suggested
+ * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+ * VREG_BYPASS should be cleared to zero.
+ */
+ if (of_property_read_bool(node, "pcie-vph-3v3"))
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ imx6_pcie_grp_offset(imx6_pcie),
+ IMX8MQ_GPR_PCIE_VREG_BYPASS,
+ 0);
break;
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3
@ 2021-03-19 8:24 ` Richard Zhu
0 siblings, 0 replies; 8+ messages in thread
From: Richard Zhu @ 2021-03-19 8:24 UTC (permalink / raw)
To: l.stach, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel,
Richard Zhu
Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..c35d5511b55b 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -37,6 +37,7 @@
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
@@ -611,6 +612,10 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
+ struct dw_pcie *pci = imx6_pcie->pci;
+ struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
+
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ:
/*
@@ -621,6 +626,16 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
imx6_pcie_grp_offset(imx6_pcie),
IMX8MQ_GPR_PCIE_REF_USE_PAD,
IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ /*
+ * Regarding to the datasheet, the PCIE_VPH is suggested
+ * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+ * VREG_BYPASS should be cleared to zero.
+ */
+ if (of_property_read_bool(node, "pcie-vph-3v3"))
+ regmap_update_bits(imx6_pcie->iomuxc_gpr,
+ imx6_pcie_grp_offset(imx6_pcie),
+ IMX8MQ_GPR_PCIE_VREG_BYPASS,
+ 0);
break;
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage
2021-03-19 8:24 ` Richard Zhu
@ 2021-03-19 9:49 ` Lucas Stach
-1 siblings, 0 replies; 8+ messages in thread
From: Lucas Stach @ 2021-03-19 9:49 UTC (permalink / raw)
To: Richard Zhu, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel
Am Freitag, dem 19.03.2021 um 16:24 +0800 schrieb Richard Zhu:
> Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
> In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
> sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
> the VREG_BYPASS bits of GPR registers should be cleared from default
> value 1b'1 to 1b'0.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index de4b2baf91e8..23efbad9e804 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
> Additional required properties for imx8mq-pcie:
> - clock-names: Must include the following additional entries:
> - "pcie_aux"
> +- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW
> + schematic design. The PCIE_VPH is suggested to be 1.8v refer to the
> + data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS
> + should be cleared to zero accordingly.
Uhm, no. Please don't add boolean DT properties for random parts of the
board design.
If we need to know the voltage of PCIE_VPH, we should really add the
VPH regulator as a supply to the PCIe controller node, then work out
the voltage the usual way by using the Linux regulator API.
Regards,
Lucas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage
@ 2021-03-19 9:49 ` Lucas Stach
0 siblings, 0 replies; 8+ messages in thread
From: Lucas Stach @ 2021-03-19 9:49 UTC (permalink / raw)
To: Richard Zhu, andrew.smirnov, shawnguo, kw, bhelgaas, stefan,
lorenzo.pieralisi
Cc: linux-pci, linux-imx, linux-arm-kernel, linux-kernel, kernel
Am Freitag, dem 19.03.2021 um 16:24 +0800 schrieb Richard Zhu:
> Both 1.8v and 3.3v power supplies can be feeded to i.MX8MQ PCIe PHY.
> In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
> sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
> the VREG_BYPASS bits of GPR registers should be cleared from default
> value 1b'1 to 1b'0.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index de4b2baf91e8..23efbad9e804 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -59,6 +59,10 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
> Additional required properties for imx8mq-pcie:
> - clock-names: Must include the following additional entries:
> - "pcie_aux"
> +- pcie-vph-3v3: If present then PCIE_VPH is feeded by 3.3v in the HW
> + schematic design. The PCIE_VPH is suggested to be 1.8v refer to the
> + data sheet. If the PCIE_VPH is supplied by 3.3V, the VREG_BYPASS
> + should be cleared to zero accordingly.
Uhm, no. Please don't add boolean DT properties for random parts of the
board design.
If we need to know the voltage of PCIE_VPH, we should really add the
VPH regulator as a supply to the PCIe controller node, then work out
the voltage the usual way by using the Linux regulator API.
Regards,
Lucas
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-03-19 9:51 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-19 8:24 [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage Richard Zhu
2021-03-19 8:24 ` Richard Zhu
2021-03-19 8:24 ` [PATCH 2/3] arm64: dts: add one property to " Richard Zhu
2021-03-19 8:24 ` Richard Zhu
2021-03-19 8:24 ` [PATCH 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3 Richard Zhu
2021-03-19 8:24 ` Richard Zhu
2021-03-19 9:49 ` [PATCH 1/3] dt-bindings: imx6q-pcie: specify the imx8mq pcie phy voltage Lucas Stach
2021-03-19 9:49 ` Lucas Stach
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