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From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org,
	openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
	Guo Ren <guoren@linux.alibaba.com>, Arnd Bergmann <arnd@arndb.de>,
	Chris Zankel <chris@zankel.net>,
	Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH v6 8/9] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 31 Mar 2021 14:30:39 +0000	[thread overview]
Message-ID: <1617201040-83905-9-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1617201040-83905-1-git-send-email-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.

Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.

This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 9ad6b7b82707..f19d780638f7 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
 	select ARCH_HAS_DMA_SET_UNCACHED if MMU
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_TABLE_SORT
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org,
	openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
	Guo Ren <guoren@linux.alibaba.com>, Arnd Bergmann <arnd@arndb.de>,
	Chris Zankel <chris@zankel.net>,
	Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH v6 8/9] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 31 Mar 2021 14:30:39 +0000	[thread overview]
Message-ID: <1617201040-83905-9-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1617201040-83905-1-git-send-email-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.

Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.

This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 9ad6b7b82707..f19d780638f7 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
 	select ARCH_HAS_DMA_SET_UNCACHED if MMU
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_TABLE_SORT
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org,
	Guo Ren <guoren@linux.alibaba.com>, Arnd Bergmann <arnd@arndb.de>,
	Chris Zankel <chris@zankel.net>,
	linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
	Max Filippov <jcmvbkbc@gmail.com>,
	openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
	linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v6 8/9] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 31 Mar 2021 14:30:39 +0000	[thread overview]
Message-ID: <1617201040-83905-9-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1617201040-83905-1-git-send-email-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.

Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.

This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 9ad6b7b82707..f19d780638f7 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
 	select ARCH_HAS_DMA_SET_UNCACHED if MMU
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_TABLE_SORT
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org <guoren@kernel.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v6 8/9] xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 31 Mar 2021 14:30:39 +0000	[thread overview]
Message-ID: <1617201040-83905-9-git-send-email-guoren@kernel.org> (raw)
In-Reply-To: <1617201040-83905-1-git-send-email-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.

Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.

This patch cancels the dependency of on qspinlock generic code on
architecture's xchg16.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 9ad6b7b82707..f19d780638f7 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
 	select ARCH_HAS_DMA_SET_UNCACHED if MMU
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_SPINLOCKS_XCHG32
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_TABLE_SORT
-- 
2.17.1


  parent reply	other threads:[~2021-03-31 14:33 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31 14:30 [PATCH v6 0/9] riscv: Add qspinlock/qrwlock guoren
2021-03-31 14:30 ` [OpenRISC] " guoren
2021-03-31 14:30 ` guoren
2021-03-31 14:30 ` guoren
2021-03-31 14:30 ` [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-04-06 16:51   ` Boqun Feng
2021-04-06 16:51     ` [OpenRISC] " Boqun Feng
2021-04-06 16:51     ` Boqun Feng
2021-04-06 16:51     ` Boqun Feng
2021-04-06 23:52     ` [OpenRISC] " Stafford Horne
2021-04-06 23:52       ` Stafford Horne
2021-04-06 23:52       ` Stafford Horne
2021-04-06 23:52       ` Stafford Horne
2021-04-07  9:47       ` Peter Zijlstra
2021-04-07  9:47         ` Peter Zijlstra
2021-04-07  9:47         ` Peter Zijlstra
2021-04-07  9:47         ` Peter Zijlstra
2021-04-07 20:12         ` Stafford Horne
2021-04-07 20:12           ` Stafford Horne
2021-04-07 20:12           ` Stafford Horne
2021-04-07 20:12           ` Stafford Horne
2021-04-08 19:00       ` Waiman Long
2021-04-08 19:00         ` Waiman Long
2021-04-08 19:00         ` Waiman Long
2021-04-08 19:00         ` Waiman Long
2021-03-31 14:30 ` [PATCH v6 2/9] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30 ` [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-04-05  5:54   ` Guo Ren
2021-04-05  5:54     ` [OpenRISC] " Guo Ren
2021-04-05  5:54     ` Guo Ren
2021-04-05  5:54     ` Guo Ren
2021-04-11 16:02   ` Guo Ren
2021-04-11 16:02     ` [OpenRISC] " Guo Ren
2021-04-11 16:02     ` Guo Ren
2021-04-11 16:02     ` Guo Ren
2021-04-11 16:51     ` Guo Ren
2021-04-11 16:51       ` [OpenRISC] " Guo Ren
2021-04-11 16:51       ` Guo Ren
2021-04-11 16:51       ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 4/9] csky: locks: Optimize coding convention guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-04-11 16:01   ` Guo Ren
2021-04-11 16:01     ` [OpenRISC] " Guo Ren
2021-04-11 16:01     ` Guo Ren
2021-04-11 16:01     ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 5/9] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30 ` [PATCH v6 6/9] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-04-06  8:56   ` Stafford Horne
2021-04-06  8:56     ` [OpenRISC] " Stafford Horne
2021-04-06  8:56     ` Stafford Horne
2021-04-06  8:56     ` Stafford Horne
2021-03-31 14:30 ` [PATCH v6 7/9] sparc: " guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30 ` guoren [this message]
2021-03-31 14:30   ` [OpenRISC] [PATCH v6 8/9] xtensa: " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30 ` [PATCH v6 9/9] powerpc/qspinlock: " guoren
2021-03-31 14:30   ` [OpenRISC] " guoren
2021-03-31 14:30   ` guoren
2021-03-31 14:30   ` guoren

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