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From: Krishna Manikandan <mkrishn@codeaurora.org>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	freedreno@lists.freedesktop.org
Cc: Krishna Manikandan <mkrishn@codeaurora.org>,
	linux-kernel@vger.kernel.org, robdclark@gmail.com,
	kalyan_t@codeaurora.org, dianders@chromium.org
Subject: [PATCH v1 2/3] drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5
Date: Tue,  6 Apr 2021 11:31:34 +0530	[thread overview]
Message-ID: <1617688895-26275-3-git-send-email-mkrishn@codeaurora.org> (raw)
In-Reply-To: <1617688895-26275-1-git-send-email-mkrishn@codeaurora.org>

INTF_5 is used by EDP panel in SC7280 target. Add vsync
and underrun irqs needed by INTF_5 to dpu irq map.

Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 72cdaf8..a37928b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -69,10 +69,12 @@
 #define DPU_INTR_INTF_1_UNDERRUN BIT(26)
 #define DPU_INTR_INTF_2_UNDERRUN BIT(28)
 #define DPU_INTR_INTF_3_UNDERRUN BIT(30)
+#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
 #define DPU_INTR_INTF_0_VSYNC BIT(25)
 #define DPU_INTR_INTF_1_VSYNC BIT(27)
 #define DPU_INTR_INTF_2_VSYNC BIT(29)
 #define DPU_INTR_INTF_3_VSYNC BIT(31)
+#define DPU_INTR_INTF_5_VSYNC BIT(23)
 
 /**
  * Pingpong Secondary interrupt status bit definitions
@@ -308,7 +310,10 @@ static const struct dpu_irq_type dpu_irq_map[] = {
 	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
 	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
 	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
-	/* irq_idx:32-63 */
+	/* irq_idx:32-33 */
+	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
+	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
+	/* irq_idx:34-63 */
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Krishna Manikandan <mkrishn@codeaurora.org>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	freedreno@lists.freedesktop.org
Cc: Krishna Manikandan <mkrishn@codeaurora.org>,
	dianders@chromium.org, linux-kernel@vger.kernel.org,
	kalyan_t@codeaurora.org
Subject: [PATCH v1 2/3] drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5
Date: Tue,  6 Apr 2021 11:31:34 +0530	[thread overview]
Message-ID: <1617688895-26275-3-git-send-email-mkrishn@codeaurora.org> (raw)
In-Reply-To: <1617688895-26275-1-git-send-email-mkrishn@codeaurora.org>

INTF_5 is used by EDP panel in SC7280 target. Add vsync
and underrun irqs needed by INTF_5 to dpu irq map.

Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 72cdaf8..a37928b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -69,10 +69,12 @@
 #define DPU_INTR_INTF_1_UNDERRUN BIT(26)
 #define DPU_INTR_INTF_2_UNDERRUN BIT(28)
 #define DPU_INTR_INTF_3_UNDERRUN BIT(30)
+#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
 #define DPU_INTR_INTF_0_VSYNC BIT(25)
 #define DPU_INTR_INTF_1_VSYNC BIT(27)
 #define DPU_INTR_INTF_2_VSYNC BIT(29)
 #define DPU_INTR_INTF_3_VSYNC BIT(31)
+#define DPU_INTR_INTF_5_VSYNC BIT(23)
 
 /**
  * Pingpong Secondary interrupt status bit definitions
@@ -308,7 +310,10 @@ static const struct dpu_irq_type dpu_irq_map[] = {
 	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
 	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
 	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
-	/* irq_idx:32-63 */
+	/* irq_idx:32-33 */
+	{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
+	{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
+	/* irq_idx:34-63 */
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
 	{ DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
-- 
2.7.4

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  parent reply	other threads:[~2021-04-06  6:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-06  6:01 [PATCH v1 0/3] Add irq support to accommodate SC7280 target Krishna Manikandan
2021-04-06  6:01 ` Krishna Manikandan
2021-04-06  6:01 ` [PATCH v1 1/3] drm/msm/disp/dpu1: increase the range of interrupts in dpu_irq_map Krishna Manikandan
2021-04-06  6:01   ` Krishna Manikandan
2021-04-06  6:01 ` Krishna Manikandan [this message]
2021-04-06  6:01   ` [PATCH v1 2/3] drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5 Krishna Manikandan
2021-04-06  6:01 ` [PATCH v1 3/3] drm/msm/disp/dpu1: add flags to indicate obsolete irqs Krishna Manikandan
2021-04-06  6:01   ` Krishna Manikandan
2021-05-26 19:03 ` [PATCH v1 0/3] Add irq support to accommodate SC7280 target patchwork-bot+linux-arm-msm

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