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From: Frank Chang <1923629@bugs.launchpad.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating
Date: Thu, 15 Apr 2021 07:31:04 -0000	[thread overview]
Message-ID: <161847186460.28384.4417965053936211792.malone@soybean.canonical.com> (raw)
In-Reply-To: 161832726983.9430.3755052950345832110.malonedeb@chaenomeles.canonical.com

This should be a quick fix, we will run couple tests again to ensure the
fix doesn't break anything. Thanks~

** Changed in: qemu
     Assignee: (unassigned) => Frank Chang (frankchang0125)

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https://bugs.launchpad.net/bugs/1923629

Title:
  RISC-V Vector Instruction vssub.vv not saturating

Status in QEMU:
  New

Bug description:
  I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
  incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).

  Here is the bit of the code:

  		vmv.v.i		v16, 0
  		…
  8f040457	vssub.vv	v8,v16,v8

  I believe the instruction encoding is correct (vssub.vv with vd = v8,
  vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.

  I’ve just tested with what I think is the latest branch (
  https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
  2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
  exists.

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  parent reply	other threads:[~2021-04-15  7:41 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13 15:21 [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating Tony Cole
2021-04-15  3:57 ` Alistair Francis
2021-04-15  4:00   ` Kito Cheng
2021-04-15  4:18   ` LIU Zhiwei
2021-04-15  4:42     ` Alistair Francis
2021-04-15  4:42 ` [Bug 1923629] " Alistair Francis
2021-04-15  7:31 ` Frank Chang [this message]
2021-05-12 23:58 ` Alistair Francis
2021-08-25  7:18 ` Thomas Huth

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