* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
@ 2021-04-15 13:53 ` ml-0
2021-04-15 14:21 ` Peter Maydell
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-15 13:53 UTC (permalink / raw)
To: qemu-devel
** Description changed:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-WSL2
#1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
- unsigned int fpscr =__get_FPSCR();
- fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
- __set_FPSCR(fpscr);
+ unsigned int fpscr =__get_FPSCR();
+ fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
+ __set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and __set_FPSCR(fpscr)
are taken from CMSIS_5 at ./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The same
- startup code works fine on the Arm Corstone-300 FVP.
+ startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
--
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
2021-04-15 13:53 ` [Bug 1923861] " ml-0
@ 2021-04-15 14:21 ` Peter Maydell
2021-04-15 15:36 ` ml-0
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-15 14:21 UTC (permalink / raw)
To: qemu-devel
Does your code enable the FPU (via the CPACR and, if running in
NonSecure) the NSACR? If not then a fault is exactly what you should
expect. (I believe the FVP has a non-standard behaviour where it will
enable the FPU by default even though real hardware does not behave that
way.)
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
2021-04-15 13:53 ` [Bug 1923861] " ml-0
2021-04-15 14:21 ` Peter Maydell
@ 2021-04-15 15:36 ` ml-0
2021-04-15 16:07 ` Peter Maydell
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-15 15:36 UTC (permalink / raw)
To: qemu-devel
Yes, I think I did:
SCB->NSACR |= (3U << 10U); /* enable Non-secure access to CP10 and CP11 coprocessors */
__DSB();
__ISB();
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
__DSB();
__ISB();
But I get a NOCP (no coprocessor) hard fault.
Does the qemu mps3-an547 model contain the FPU by default or do I have to select it via the command line?
Is there an example code / test case included in the qemu database where I can lookup the usage of mps3-an547 + FPU?
--
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (2 preceding siblings ...)
2021-04-15 15:36 ` ml-0
@ 2021-04-15 16:07 ` Peter Maydell
2021-04-15 16:44 ` ml-0
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-15 16:07 UTC (permalink / raw)
To: qemu-devel
Do you have a guest binary and QEMU commandline I can use to reproduce
the issue ?
--
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (3 preceding siblings ...)
2021-04-15 16:07 ` Peter Maydell
@ 2021-04-15 16:44 ` ml-0
2021-04-15 18:17 ` Peter Maydell
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-15 16:44 UTC (permalink / raw)
To: qemu-devel
Command line is
qemu-system-arm -machine mps3-an547 -nographic -kernel test.elf -semihosting -semihosting-config enable=on,target=native
Binary is attached. It does
int main(int argc, char* argv[])
{
SCB->NSACR |= (3U << 10U); /* enable Non-secure access to CP10 and CP11 coprocessors */
__DSB();
__ISB();
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
__DSB();
__ISB();
// enable DL branch cache
#define CCR (*((volatile unsigned int *)0xE000ED14))
#define CCR_DL (1 << 19)
CCR |= CCR_DL;
__ISB();
uint32_t result;
__asm volatile ("VMRS %0, fpscr" : "=r" (result) ); // <-- NOCP hardfault
printf("fpscr = 0x%08lx\r\n", result);
__asm volatile ("VMRS %0, mvfr0" : "=r" (result) );
printf("mvfr0 = 0x%08lx\r\n", result);
__asm volatile ("VMRS %0, mvfr1" : "=r" (result) );
printf("mvfr1 = 0x%08lx\r\n", result);
__asm volatile ("VMRS %0, mvfr2" : "=r" (result) );
printf("mvfr2 = 0x%08lx\r\n", result);
exit(0);
}
Thank you for your help!
** Attachment added: "test.elf"
https://bugs.launchpad.net/qemu/+bug/1923861/+attachment/5488449/+files/test.elf
--
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (4 preceding siblings ...)
2021-04-15 16:44 ` ml-0
@ 2021-04-15 18:17 ` Peter Maydell
2021-04-15 18:32 ` Peter Maydell
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-15 18:17 UTC (permalink / raw)
To: qemu-devel
Thanks. This is a bug in the AN547 model -- we were accidentally turning
off the FPU. I'll write a patch.
NB that with that bug fixed your code then hits an UNDEF trying to do:
0x00000996: eef7 1a10 vmrs r1, mvfr0
Only A-profile CPUs have MVFR0 accessible via the vmrs instruction. For
M-profile this register is memory-mapped, at 0xE000EF40.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (5 preceding siblings ...)
2021-04-15 18:17 ` Peter Maydell
@ 2021-04-15 18:32 ` Peter Maydell
2021-04-16 7:51 ` ml-0
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-15 18:32 UTC (permalink / raw)
To: qemu-devel
The bug fix for the QEMU part of this is
https://patchew.org/QEMU/20210415182353.8173-1-peter.maydell@linaro.org/
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (6 preceding siblings ...)
2021-04-15 18:32 ` Peter Maydell
@ 2021-04-16 7:51 ` ml-0
2021-04-16 9:20 ` Peter Maydell
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-16 7:51 UTC (permalink / raw)
To: qemu-devel
Thanks for the fix. I applied it and
1. yes, the hard fault when reading FPSCR is gone.
2. yes, I also see the UNDEF. Note that on the Corstone-300 MPS3-AN547 FVP I can access mvfr0 via vmrs.
I changed the vmrs to ldr. Now I can read the registers. The values differ from what the FVP tells me:
fpscr = 0x00000000 (qemu-system-arm) - 0x00040000 (Corstone FVP)
mvfr0 = 0x10110021 - 0x10110221
mvfr1 = 0x11000011 - 0x12100211
mvfr2 = 0x00000040 - 0x00000040
Using the FPU for some simple calculations
volatile int nom_i, den_i;
nom_i = 7;
den_i = 3;
volatile float nom_f, den_f, div_f;
nom_f = (float)nom_i;
den_f = (float)den_i;
div_f = nom_f / den_f;
printf("%e / %f = %f\r\n", nom_f, den_f, div_f);
I run into another UNDEF when executing
vcvt.f64.f32 d6, s12
Again, the FVP can execute the same elf. I attached it. Maybe you can
have another look.
** Attachment added: "test2.elf"
https://bugs.launchpad.net/qemu/+bug/1923861/+attachment/5488742/+files/test2.elf
--
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (7 preceding siblings ...)
2021-04-16 7:51 ` ml-0
@ 2021-04-16 9:20 ` Peter Maydell
2021-04-16 9:53 ` ml-0
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-16 9:20 UTC (permalink / raw)
To: qemu-devel
Some of those ID register differences are expected; some I'm surprised by. The differences are:
* no MVE (expected, we don't implement it yet)
* no double-precision
* no FP16
So the missing double-precision is why your vcvt UNDEFs. Those last two
ought to be present, but something is squashing them; I will
investigate.
The FPSCR difference is that we aren't reporting FPSCR.LTPSIZE for some
reason -- that's a bug too.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (8 preceding siblings ...)
2021-04-16 9:20 ` Peter Maydell
@ 2021-04-16 9:53 ` ml-0
2021-04-16 9:53 ` Peter Maydell
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-16 9:53 UTC (permalink / raw)
To: qemu-devel
I changed the compile options to single precision, only. Then, my small
FP example works. Ok for my purposes, I don't need double.
But I would need MVE. Are there any plans to implement MVE?
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (9 preceding siblings ...)
2021-04-16 9:53 ` ml-0
@ 2021-04-16 9:53 ` Peter Maydell
2021-04-16 10:10 ` Peter Maydell
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-16 9:53 UTC (permalink / raw)
To: qemu-devel
Oops -- we were giving the AN547 a Cortex-M33 rather than the -M55 it
ought to have :-(
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (10 preceding siblings ...)
2021-04-16 9:53 ` Peter Maydell
@ 2021-04-16 10:10 ` Peter Maydell
2021-04-16 10:43 ` Peter Maydell
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-16 10:10 UTC (permalink / raw)
To: qemu-devel
Yes, MVE is next on my todo list; it will probably be in 6.2, or maybe
7.0 depending how long it takes to implement it all.
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (11 preceding siblings ...)
2021-04-16 10:10 ` Peter Maydell
@ 2021-04-16 10:43 ` Peter Maydell
2021-04-16 11:07 ` ml-0
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-16 10:43 UTC (permalink / raw)
To: qemu-devel
https://patchew.org/QEMU/20210416104010.13228-1-peter.maydell@linaro.org/
should fix the "not actually an M55" bug which will then give you the
double-precision and FP16 (and the right FPSCR value).
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (12 preceding siblings ...)
2021-04-16 10:43 ` Peter Maydell
@ 2021-04-16 11:07 ` ml-0
2021-04-19 12:59 ` Peter Maydell
2021-04-30 7:25 ` Thomas Huth
15 siblings, 0 replies; 17+ messages in thread
From: ml-0 @ 2021-04-16 11:07 UTC (permalink / raw)
To: qemu-devel
I tried your fix. Yes, the fpscr and mvfr0/1/2 values do match the FVP,
now (except for the MVE bit which is explained above).
Thx for the updates.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
New
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (13 preceding siblings ...)
2021-04-16 11:07 ` ml-0
@ 2021-04-19 12:59 ` Peter Maydell
2021-04-30 7:25 ` Thomas Huth
15 siblings, 0 replies; 17+ messages in thread
From: Peter Maydell @ 2021-04-19 12:59 UTC (permalink / raw)
To: qemu-devel
These fixes are now in master and will be in rc4 and the eventual 6.0
release.
** Changed in: qemu
Status: New => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
Fix Committed
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread* [Bug 1923861] Re: Hardfault when accessing FPSCR register
2021-04-14 15:43 [Bug 1923861] [NEW] Hardfault when accessing FPSCR register ml-0
` (14 preceding siblings ...)
2021-04-19 12:59 ` Peter Maydell
@ 2021-04-30 7:25 ` Thomas Huth
15 siblings, 0 replies; 17+ messages in thread
From: Thomas Huth @ 2021-04-30 7:25 UTC (permalink / raw)
To: qemu-devel
https://gitlab.com/qemu-project/qemu/-/commit/330ef14e6e749919c5c
https://gitlab.com/qemu-project/qemu/-/commit/1df0878cff267128393
** Changed in: qemu
Status: Fix Committed => Fix Released
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1923861
Title:
Hardfault when accessing FPSCR register
Status in QEMU:
Fix Released
Bug description:
QEMU release version: v6.0.0-rc2
command line:
qemu-system-arm -machine mps3-an547 -nographic -kernel <my_project>.elf -semihosting -semihosting-config enable=on,target=native
host operating system: Linux ISCNR90TMR1S 5.4.72-microsoft-standard-
WSL2 #1 SMP Wed Oct 28 23:40:43 UTC 2020 x86_64 x86_64 x86_64
GNU/Linux
guest operating system: none (bare metal)
Observation:
I am simulating embedded firmware for a Cortex-M55 device, using MPS3-AN547 machine. In the startup code I am accessing the FPSCR core register:
unsigned int fpscr =__get_FPSCR();
fpscr = fpscr & (~FPU_FPDSCR_AHP_Msk);
__set_FPSCR(fpscr);
where the register access functions __get_FPSCR() and
__set_FPSCR(fpscr) are taken from CMSIS_5 at
./CMSIS/Core/include/cmsis_gcc.h
I observe hardfaults upon __get_FPSCR() and __set_FPSCR(fpscr). The
same startup code works fine on the Arm Corstone-300 FVP (MPS3-AN547).
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1923861/+subscriptions
^ permalink raw reply [flat|nested] 17+ messages in thread