* [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles
@ 2021-04-21 17:28 Umesh Nerlige Ramappa
2021-04-21 17:28 ` [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy Umesh Nerlige Ramappa
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2021-04-21 17:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
This is just a refresh of the earlier patch along with cover letter for the IGT
testing. The query provides the engine cs cycles counter.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Test-with: 20210421172046.65062-1-umesh.nerlige.ramappa@intel.com
Umesh Nerlige Ramappa (1):
i915/query: Correlate engine and cpu timestamps with better accuracy
drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++
include/uapi/drm/i915_drm.h | 48 ++++++++++
2 files changed, 193 insertions(+)
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy 2021-04-21 17:28 [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles Umesh Nerlige Ramappa @ 2021-04-21 17:28 ` Umesh Nerlige Ramappa 2021-04-23 7:05 ` Lionel Landwerlin 2021-04-21 18:26 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles Patchwork ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-04-21 17:28 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these timestamps separately and the calculated delta between these timestamps lack enough accuracy. To improve the accuracy of these time measurements to within a few us, add a query that returns the engine and cpu timestamps captured as close to each other as possible. v2: (Tvrtko) - document clock reference used - return cpu timestamp always - capture cpu time just before lower dword of cs timestamp v3: (Chris) - use uncore-rpm - use __query_cs_timestamp helper v4: (Lionel) - Kernel perf subsytem allows users to specify the clock id to be used in perf_event_open. This clock id is used by the perf subsystem to return the appropriate cpu timestamp in perf events. Similarly, let the user pass the clockid to this query so that cpu timestamp corresponds to the clock id requested. v5: (Tvrtko) - Use normal ktime accessors instead of fast versions - Add more uApi documentation v6: (Lionel) - Move switch out of spinlock v7: (Chris) - cs_timestamp is a misnomer, use cs_cycles instead - return the cs cycle frequency as well in the query v8: - Add platform and engine specific checks v9: (Lionel) - Return 2 cpu timestamps in the query - captured before and after the register read v10: (Chris) - Use local_clock() to measure time taken to read lower dword of register and return it to user. Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 48 ++++++++++ 2 files changed, 193 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index fed337ad7b68..25b96927ab92 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -6,6 +6,8 @@ #include <linux/nospec.h> +#include "gt/intel_engine_pm.h" +#include "gt/intel_engine_user.h" #include "i915_drv.h" #include "i915_perf.h" #include "i915_query.h" @@ -90,6 +92,148 @@ static int query_topology_info(struct drm_i915_private *dev_priv, return total_length; } +typedef u64 (*__ktime_func_t)(void); +static __ktime_func_t __clock_id_to_func(clockid_t clk_id) +{ + /* + * Use logic same as the perf subsystem to allow user to select the + * reference clock id to be used for timestamps. + */ + switch (clk_id) { + case CLOCK_MONOTONIC: + return &ktime_get_ns; + case CLOCK_MONOTONIC_RAW: + return &ktime_get_raw_ns; + case CLOCK_REALTIME: + return &ktime_get_real_ns; + case CLOCK_BOOTTIME: + return &ktime_get_boottime_ns; + case CLOCK_TAI: + return &ktime_get_clocktai_ns; + default: + return NULL; + } +} + +static inline int +__read_timestamps(struct intel_uncore *uncore, + i915_reg_t lower_reg, + i915_reg_t upper_reg, + u64 *cs_ts, + u64 *cpu_ts, + __ktime_func_t cpu_clock) +{ + u32 upper, lower, old_upper, loop = 0; + + upper = intel_uncore_read_fw(uncore, upper_reg); + do { + cpu_ts[1] = local_clock(); + cpu_ts[0] = cpu_clock(); + lower = intel_uncore_read_fw(uncore, lower_reg); + cpu_ts[1] = local_clock() - cpu_ts[1]; + old_upper = upper; + upper = intel_uncore_read_fw(uncore, upper_reg); + } while (upper != old_upper && loop++ < 2); + + *cs_ts = (u64)upper << 32 | lower; + + return 0; +} + +static int +__query_cs_cycles(struct intel_engine_cs *engine, + u64 *cs_ts, u64 *cpu_ts, + __ktime_func_t cpu_clock) +{ + struct intel_uncore *uncore = engine->uncore; + enum forcewake_domains fw_domains; + u32 base = engine->mmio_base; + intel_wakeref_t wakeref; + int ret; + + fw_domains = intel_uncore_forcewake_for_reg(uncore, + RING_TIMESTAMP(base), + FW_REG_READ); + + with_intel_runtime_pm(uncore->rpm, wakeref) { + spin_lock_irq(&uncore->lock); + intel_uncore_forcewake_get__locked(uncore, fw_domains); + + ret = __read_timestamps(uncore, + RING_TIMESTAMP(base), + RING_TIMESTAMP_UDW(base), + cs_ts, + cpu_ts, + cpu_clock); + + intel_uncore_forcewake_put__locked(uncore, fw_domains); + spin_unlock_irq(&uncore->lock); + } + + return ret; +} + +static int +query_cs_cycles(struct drm_i915_private *i915, + struct drm_i915_query_item *query_item) +{ + struct drm_i915_query_cs_cycles __user *query_ptr; + struct drm_i915_query_cs_cycles query; + struct intel_engine_cs *engine; + __ktime_func_t cpu_clock; + int ret; + + if (INTEL_GEN(i915) < 6) + return -ENODEV; + + query_ptr = u64_to_user_ptr(query_item->data_ptr); + ret = copy_query_item(&query, sizeof(query), sizeof(query), query_item); + if (ret != 0) + return ret; + + if (query.flags) + return -EINVAL; + + if (query.rsvd) + return -EINVAL; + + cpu_clock = __clock_id_to_func(query.clockid); + if (!cpu_clock) + return -EINVAL; + + engine = intel_engine_lookup_user(i915, + query.engine.engine_class, + query.engine.engine_instance); + if (!engine) + return -EINVAL; + + if (IS_GEN(i915, 6) && + query.engine.engine_class != I915_ENGINE_CLASS_RENDER) + return -ENODEV; + + query.cs_frequency = engine->gt->clock_frequency; + ret = __query_cs_cycles(engine, + &query.cs_cycles, + query.cpu_timestamp, + cpu_clock); + if (ret) + return ret; + + if (put_user(query.cs_frequency, &query_ptr->cs_frequency)) + return -EFAULT; + + if (put_user(query.cpu_timestamp[0], &query_ptr->cpu_timestamp[0])) + return -EFAULT; + + if (put_user(query.cpu_timestamp[1], &query_ptr->cpu_timestamp[1])) + return -EFAULT; + + if (put_user(query.cs_cycles, &query_ptr->cs_cycles)) + return -EFAULT; + + return sizeof(query); +} + static int query_engine_info(struct drm_i915_private *i915, struct drm_i915_query_item *query_item) @@ -424,6 +568,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, query_topology_info, query_engine_info, query_perf_config, + query_cs_cycles, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 6a34243a7646..08b00f1709b5 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2230,6 +2230,10 @@ struct drm_i915_query_item { #define DRM_I915_QUERY_TOPOLOGY_INFO 1 #define DRM_I915_QUERY_ENGINE_INFO 2 #define DRM_I915_QUERY_PERF_CONFIG 3 + /** + * Query Command Streamer timestamp register. + */ +#define DRM_I915_QUERY_CS_CYCLES 4 /* Must be kept compact -- no holes and well documented */ /** @@ -2397,6 +2401,50 @@ struct drm_i915_engine_info { __u64 rsvd1[4]; }; +/** + * struct drm_i915_query_cs_cycles + * + * The query returns the command streamer cycles and the frequency that can be + * used to calculate the command streamer timestamp. In addition the query + * returns a set of cpu timestamps that indicate when the command streamer cycle + * count was captured. + */ +struct drm_i915_query_cs_cycles { + /** Engine for which command streamer cycles is queried. */ + struct i915_engine_class_instance engine; + + /** Must be zero. */ + __u32 flags; + + /** + * Command streamer cycles as read from the command streamer + * register at 0x358 offset. + */ + __u64 cs_cycles; + + /** Frequency of the cs cycles in Hz. */ + __u64 cs_frequency; + + /** + * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the + * cs_cycles register using the reference clockid set by the user. + * cpu_timestamp[1] is the time taken in ns to read the lower dword of + * the cs_cycles register. + */ + __u64 cpu_timestamp[2]; + + /** + * Reference clock id for CPU timestamp. For definition, see + * clock_gettime(2) and perf_event_open(2). Supported clock ids are + * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, + * CLOCK_TAI. + */ + __s32 clockid; + + /** Must be zero. */ + __u32 rsvd; +}; + /** * struct drm_i915_query_engine_info * -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy 2021-04-21 17:28 ` [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy Umesh Nerlige Ramappa @ 2021-04-23 7:05 ` Lionel Landwerlin 2021-04-23 15:11 ` Umesh Nerlige Ramappa 2021-04-26 11:53 ` Jani Nikula 0 siblings, 2 replies; 13+ messages in thread From: Lionel Landwerlin @ 2021-04-23 7:05 UTC (permalink / raw) To: Umesh Nerlige Ramappa, intel-gfx; +Cc: Chris Wilson On 21/04/2021 20:28, Umesh Nerlige Ramappa wrote: > Perf measurements rely on CPU and engine timestamps to correlate > events of interest across these time domains. Current mechanisms get > these timestamps separately and the calculated delta between these > timestamps lack enough accuracy. > > To improve the accuracy of these time measurements to within a few us, > add a query that returns the engine and cpu timestamps captured as > close to each other as possible. > > v2: (Tvrtko) > - document clock reference used > - return cpu timestamp always > - capture cpu time just before lower dword of cs timestamp > > v3: (Chris) > - use uncore-rpm > - use __query_cs_timestamp helper > > v4: (Lionel) > - Kernel perf subsytem allows users to specify the clock id to be used > in perf_event_open. This clock id is used by the perf subsystem to > return the appropriate cpu timestamp in perf events. Similarly, let > the user pass the clockid to this query so that cpu timestamp > corresponds to the clock id requested. > > v5: (Tvrtko) > - Use normal ktime accessors instead of fast versions > - Add more uApi documentation > > v6: (Lionel) > - Move switch out of spinlock > > v7: (Chris) > - cs_timestamp is a misnomer, use cs_cycles instead > - return the cs cycle frequency as well in the query > > v8: > - Add platform and engine specific checks > > v9: (Lionel) > - Return 2 cpu timestamps in the query - captured before and after the > register read > > v10: (Chris) > - Use local_clock() to measure time taken to read lower dword of > register and return it to user. > > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > --- > drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ > include/uapi/drm/i915_drm.h | 48 ++++++++++ > 2 files changed, 193 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > index fed337ad7b68..25b96927ab92 100644 > --- a/drivers/gpu/drm/i915/i915_query.c > +++ b/drivers/gpu/drm/i915/i915_query.c > @@ -6,6 +6,8 @@ > > #include <linux/nospec.h> > > +#include "gt/intel_engine_pm.h" > +#include "gt/intel_engine_user.h" > #include "i915_drv.h" > #include "i915_perf.h" > #include "i915_query.h" > @@ -90,6 +92,148 @@ static int query_topology_info(struct drm_i915_private *dev_priv, > return total_length; > } > > +typedef u64 (*__ktime_func_t)(void); > +static __ktime_func_t __clock_id_to_func(clockid_t clk_id) > +{ > + /* > + * Use logic same as the perf subsystem to allow user to select the > + * reference clock id to be used for timestamps. > + */ > + switch (clk_id) { > + case CLOCK_MONOTONIC: > + return &ktime_get_ns; > + case CLOCK_MONOTONIC_RAW: > + return &ktime_get_raw_ns; > + case CLOCK_REALTIME: > + return &ktime_get_real_ns; > + case CLOCK_BOOTTIME: > + return &ktime_get_boottime_ns; > + case CLOCK_TAI: > + return &ktime_get_clocktai_ns; > + default: > + return NULL; > + } > +} > + > +static inline int > +__read_timestamps(struct intel_uncore *uncore, > + i915_reg_t lower_reg, > + i915_reg_t upper_reg, > + u64 *cs_ts, > + u64 *cpu_ts, > + __ktime_func_t cpu_clock) > +{ > + u32 upper, lower, old_upper, loop = 0; > + > + upper = intel_uncore_read_fw(uncore, upper_reg); > + do { > + cpu_ts[1] = local_clock(); > + cpu_ts[0] = cpu_clock(); > + lower = intel_uncore_read_fw(uncore, lower_reg); > + cpu_ts[1] = local_clock() - cpu_ts[1]; > + old_upper = upper; > + upper = intel_uncore_read_fw(uncore, upper_reg); > + } while (upper != old_upper && loop++ < 2); > + > + *cs_ts = (u64)upper << 32 | lower; > + > + return 0; > +} > + > +static int > +__query_cs_cycles(struct intel_engine_cs *engine, > + u64 *cs_ts, u64 *cpu_ts, > + __ktime_func_t cpu_clock) > +{ > + struct intel_uncore *uncore = engine->uncore; > + enum forcewake_domains fw_domains; > + u32 base = engine->mmio_base; > + intel_wakeref_t wakeref; > + int ret; > + > + fw_domains = intel_uncore_forcewake_for_reg(uncore, > + RING_TIMESTAMP(base), > + FW_REG_READ); > + > + with_intel_runtime_pm(uncore->rpm, wakeref) { > + spin_lock_irq(&uncore->lock); > + intel_uncore_forcewake_get__locked(uncore, fw_domains); > + > + ret = __read_timestamps(uncore, > + RING_TIMESTAMP(base), > + RING_TIMESTAMP_UDW(base), > + cs_ts, > + cpu_ts, > + cpu_clock); > + > + intel_uncore_forcewake_put__locked(uncore, fw_domains); > + spin_unlock_irq(&uncore->lock); > + } > + > + return ret; > +} > + > +static int > +query_cs_cycles(struct drm_i915_private *i915, > + struct drm_i915_query_item *query_item) > +{ > + struct drm_i915_query_cs_cycles __user *query_ptr; > + struct drm_i915_query_cs_cycles query; > + struct intel_engine_cs *engine; > + __ktime_func_t cpu_clock; > + int ret; > + > + if (INTEL_GEN(i915) < 6) > + return -ENODEV; > + > + query_ptr = u64_to_user_ptr(query_item->data_ptr); > + ret = copy_query_item(&query, sizeof(query), sizeof(query), query_item); > + if (ret != 0) > + return ret; > + > + if (query.flags) > + return -EINVAL; > + > + if (query.rsvd) > + return -EINVAL; > + > + cpu_clock = __clock_id_to_func(query.clockid); > + if (!cpu_clock) > + return -EINVAL; > + > + engine = intel_engine_lookup_user(i915, > + query.engine.engine_class, > + query.engine.engine_instance); > + if (!engine) > + return -EINVAL; > + > + if (IS_GEN(i915, 6) && > + query.engine.engine_class != I915_ENGINE_CLASS_RENDER) > + return -ENODEV; Thanks a bunch for rebasing this. My only comment on this patch would be : don't we want IS_GEN_RANGE(i915, 1, 6) instead of IS_GEN(i915, 6) ? (assuming gen1 is a thing...) -Lionel > + > + query.cs_frequency = engine->gt->clock_frequency; > + ret = __query_cs_cycles(engine, > + &query.cs_cycles, > + query.cpu_timestamp, > + cpu_clock); > + if (ret) > + return ret; > + > + if (put_user(query.cs_frequency, &query_ptr->cs_frequency)) > + return -EFAULT; > + > + if (put_user(query.cpu_timestamp[0], &query_ptr->cpu_timestamp[0])) > + return -EFAULT; > + > + if (put_user(query.cpu_timestamp[1], &query_ptr->cpu_timestamp[1])) > + return -EFAULT; > + > + if (put_user(query.cs_cycles, &query_ptr->cs_cycles)) > + return -EFAULT; > + > + return sizeof(query); > +} > + > static int > query_engine_info(struct drm_i915_private *i915, > struct drm_i915_query_item *query_item) > @@ -424,6 +568,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, > query_topology_info, > query_engine_info, > query_perf_config, > + query_cs_cycles, > }; > > int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index 6a34243a7646..08b00f1709b5 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -2230,6 +2230,10 @@ struct drm_i915_query_item { > #define DRM_I915_QUERY_TOPOLOGY_INFO 1 > #define DRM_I915_QUERY_ENGINE_INFO 2 > #define DRM_I915_QUERY_PERF_CONFIG 3 > + /** > + * Query Command Streamer timestamp register. > + */ > +#define DRM_I915_QUERY_CS_CYCLES 4 > /* Must be kept compact -- no holes and well documented */ > > /** > @@ -2397,6 +2401,50 @@ struct drm_i915_engine_info { > __u64 rsvd1[4]; > }; > > +/** > + * struct drm_i915_query_cs_cycles > + * > + * The query returns the command streamer cycles and the frequency that can be > + * used to calculate the command streamer timestamp. In addition the query > + * returns a set of cpu timestamps that indicate when the command streamer cycle > + * count was captured. > + */ > +struct drm_i915_query_cs_cycles { > + /** Engine for which command streamer cycles is queried. */ > + struct i915_engine_class_instance engine; > + > + /** Must be zero. */ > + __u32 flags; > + > + /** > + * Command streamer cycles as read from the command streamer > + * register at 0x358 offset. > + */ > + __u64 cs_cycles; > + > + /** Frequency of the cs cycles in Hz. */ > + __u64 cs_frequency; > + > + /** > + * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the > + * cs_cycles register using the reference clockid set by the user. > + * cpu_timestamp[1] is the time taken in ns to read the lower dword of > + * the cs_cycles register. > + */ > + __u64 cpu_timestamp[2]; > + > + /** > + * Reference clock id for CPU timestamp. For definition, see > + * clock_gettime(2) and perf_event_open(2). Supported clock ids are > + * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, > + * CLOCK_TAI. > + */ > + __s32 clockid; > + > + /** Must be zero. */ > + __u32 rsvd; > +}; > + > /** > * struct drm_i915_query_engine_info > * _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy 2021-04-23 7:05 ` Lionel Landwerlin @ 2021-04-23 15:11 ` Umesh Nerlige Ramappa 2021-04-23 15:21 ` Lionel Landwerlin 2021-04-26 11:53 ` Jani Nikula 1 sibling, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-04-23 15:11 UTC (permalink / raw) To: Lionel Landwerlin; +Cc: intel-gfx, Chris Wilson On Fri, Apr 23, 2021 at 10:05:34AM +0300, Lionel Landwerlin wrote: >On 21/04/2021 20:28, Umesh Nerlige Ramappa wrote: >>Perf measurements rely on CPU and engine timestamps to correlate >>events of interest across these time domains. Current mechanisms get >>these timestamps separately and the calculated delta between these >>timestamps lack enough accuracy. >> >>To improve the accuracy of these time measurements to within a few us, >>add a query that returns the engine and cpu timestamps captured as >>close to each other as possible. >> >>v2: (Tvrtko) >>- document clock reference used >>- return cpu timestamp always >>- capture cpu time just before lower dword of cs timestamp >> >>v3: (Chris) >>- use uncore-rpm >>- use __query_cs_timestamp helper >> >>v4: (Lionel) >>- Kernel perf subsytem allows users to specify the clock id to be used >> in perf_event_open. This clock id is used by the perf subsystem to >> return the appropriate cpu timestamp in perf events. Similarly, let >> the user pass the clockid to this query so that cpu timestamp >> corresponds to the clock id requested. >> >>v5: (Tvrtko) >>- Use normal ktime accessors instead of fast versions >>- Add more uApi documentation >> >>v6: (Lionel) >>- Move switch out of spinlock >> >>v7: (Chris) >>- cs_timestamp is a misnomer, use cs_cycles instead >>- return the cs cycle frequency as well in the query >> >>v8: >>- Add platform and engine specific checks >> >>v9: (Lionel) >>- Return 2 cpu timestamps in the query - captured before and after the >> register read >> >>v10: (Chris) >>- Use local_clock() to measure time taken to read lower dword of >> register and return it to user. >> >>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> >>--- >> drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ >> include/uapi/drm/i915_drm.h | 48 ++++++++++ >> 2 files changed, 193 insertions(+) >> >>diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c >>index fed337ad7b68..25b96927ab92 100644 >>--- a/drivers/gpu/drm/i915/i915_query.c >>+++ b/drivers/gpu/drm/i915/i915_query.c >>@@ -6,6 +6,8 @@ >> #include <linux/nospec.h> >>+#include "gt/intel_engine_pm.h" >>+#include "gt/intel_engine_user.h" >> #include "i915_drv.h" >> #include "i915_perf.h" >> #include "i915_query.h" >>@@ -90,6 +92,148 @@ static int query_topology_info(struct drm_i915_private *dev_priv, >> return total_length; >> } >>+typedef u64 (*__ktime_func_t)(void); >>+static __ktime_func_t __clock_id_to_func(clockid_t clk_id) >>+{ >>+ /* >>+ * Use logic same as the perf subsystem to allow user to select the >>+ * reference clock id to be used for timestamps. >>+ */ >>+ switch (clk_id) { >>+ case CLOCK_MONOTONIC: >>+ return &ktime_get_ns; >>+ case CLOCK_MONOTONIC_RAW: >>+ return &ktime_get_raw_ns; >>+ case CLOCK_REALTIME: >>+ return &ktime_get_real_ns; >>+ case CLOCK_BOOTTIME: >>+ return &ktime_get_boottime_ns; >>+ case CLOCK_TAI: >>+ return &ktime_get_clocktai_ns; >>+ default: >>+ return NULL; >>+ } >>+} >>+ >>+static inline int >>+__read_timestamps(struct intel_uncore *uncore, >>+ i915_reg_t lower_reg, >>+ i915_reg_t upper_reg, >>+ u64 *cs_ts, >>+ u64 *cpu_ts, >>+ __ktime_func_t cpu_clock) >>+{ >>+ u32 upper, lower, old_upper, loop = 0; >>+ >>+ upper = intel_uncore_read_fw(uncore, upper_reg); >>+ do { >>+ cpu_ts[1] = local_clock(); >>+ cpu_ts[0] = cpu_clock(); >>+ lower = intel_uncore_read_fw(uncore, lower_reg); >>+ cpu_ts[1] = local_clock() - cpu_ts[1]; >>+ old_upper = upper; >>+ upper = intel_uncore_read_fw(uncore, upper_reg); >>+ } while (upper != old_upper && loop++ < 2); >>+ >>+ *cs_ts = (u64)upper << 32 | lower; >>+ >>+ return 0; >>+} >>+ >>+static int >>+__query_cs_cycles(struct intel_engine_cs *engine, >>+ u64 *cs_ts, u64 *cpu_ts, >>+ __ktime_func_t cpu_clock) >>+{ >>+ struct intel_uncore *uncore = engine->uncore; >>+ enum forcewake_domains fw_domains; >>+ u32 base = engine->mmio_base; >>+ intel_wakeref_t wakeref; >>+ int ret; >>+ >>+ fw_domains = intel_uncore_forcewake_for_reg(uncore, >>+ RING_TIMESTAMP(base), >>+ FW_REG_READ); >>+ >>+ with_intel_runtime_pm(uncore->rpm, wakeref) { >>+ spin_lock_irq(&uncore->lock); >>+ intel_uncore_forcewake_get__locked(uncore, fw_domains); >>+ >>+ ret = __read_timestamps(uncore, >>+ RING_TIMESTAMP(base), >>+ RING_TIMESTAMP_UDW(base), >>+ cs_ts, >>+ cpu_ts, >>+ cpu_clock); >>+ >>+ intel_uncore_forcewake_put__locked(uncore, fw_domains); >>+ spin_unlock_irq(&uncore->lock); >>+ } >>+ >>+ return ret; >>+} >>+ >>+static int >>+query_cs_cycles(struct drm_i915_private *i915, >>+ struct drm_i915_query_item *query_item) >>+{ >>+ struct drm_i915_query_cs_cycles __user *query_ptr; >>+ struct drm_i915_query_cs_cycles query; >>+ struct intel_engine_cs *engine; >>+ __ktime_func_t cpu_clock; >>+ int ret; >>+ >>+ if (INTEL_GEN(i915) < 6) >>+ return -ENODEV; Less than gen6 is handled here early on. >>+ >>+ query_ptr = u64_to_user_ptr(query_item->data_ptr); >>+ ret = copy_query_item(&query, sizeof(query), sizeof(query), query_item); >>+ if (ret != 0) >>+ return ret; >>+ >>+ if (query.flags) >>+ return -EINVAL; >>+ >>+ if (query.rsvd) >>+ return -EINVAL; >>+ >>+ cpu_clock = __clock_id_to_func(query.clockid); >>+ if (!cpu_clock) >>+ return -EINVAL; >>+ >>+ engine = intel_engine_lookup_user(i915, >>+ query.engine.engine_class, >>+ query.engine.engine_instance); >>+ if (!engine) >>+ return -EINVAL; >>+ >>+ if (IS_GEN(i915, 6) && >>+ query.engine.engine_class != I915_ENGINE_CLASS_RENDER) >>+ return -ENODEV; > > >Thanks a bunch for rebasing this. > >My only comment on this patch would be : don't we want >IS_GEN_RANGE(i915, 1, 6) instead of IS_GEN(i915, 6) ? > >(assuming gen1 is a thing...) Less than gen6 check is above at function entry. On gen6, only render works, so I wait until I can get the engine to check that. Thanks, Umesh > > >-Lionel > > >>+ >>+ query.cs_frequency = engine->gt->clock_frequency; >>+ ret = __query_cs_cycles(engine, >>+ &query.cs_cycles, >>+ query.cpu_timestamp, >>+ cpu_clock); >>+ if (ret) >>+ return ret; >>+ >>+ if (put_user(query.cs_frequency, &query_ptr->cs_frequency)) >>+ return -EFAULT; >>+ >>+ if (put_user(query.cpu_timestamp[0], &query_ptr->cpu_timestamp[0])) >>+ return -EFAULT; >>+ >>+ if (put_user(query.cpu_timestamp[1], &query_ptr->cpu_timestamp[1])) >>+ return -EFAULT; >>+ >>+ if (put_user(query.cs_cycles, &query_ptr->cs_cycles)) >>+ return -EFAULT; >>+ >>+ return sizeof(query); >>+} >>+ >> static int >> query_engine_info(struct drm_i915_private *i915, >> struct drm_i915_query_item *query_item) >>@@ -424,6 +568,7 @@ static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, >> query_topology_info, >> query_engine_info, >> query_perf_config, >>+ query_cs_cycles, >> }; >> int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) >>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>index 6a34243a7646..08b00f1709b5 100644 >>--- a/include/uapi/drm/i915_drm.h >>+++ b/include/uapi/drm/i915_drm.h >>@@ -2230,6 +2230,10 @@ struct drm_i915_query_item { >> #define DRM_I915_QUERY_TOPOLOGY_INFO 1 >> #define DRM_I915_QUERY_ENGINE_INFO 2 >> #define DRM_I915_QUERY_PERF_CONFIG 3 >>+ /** >>+ * Query Command Streamer timestamp register. >>+ */ >>+#define DRM_I915_QUERY_CS_CYCLES 4 >> /* Must be kept compact -- no holes and well documented */ >> /** >>@@ -2397,6 +2401,50 @@ struct drm_i915_engine_info { >> __u64 rsvd1[4]; >> }; >>+/** >>+ * struct drm_i915_query_cs_cycles >>+ * >>+ * The query returns the command streamer cycles and the frequency that can be >>+ * used to calculate the command streamer timestamp. In addition the query >>+ * returns a set of cpu timestamps that indicate when the command streamer cycle >>+ * count was captured. >>+ */ >>+struct drm_i915_query_cs_cycles { >>+ /** Engine for which command streamer cycles is queried. */ >>+ struct i915_engine_class_instance engine; >>+ >>+ /** Must be zero. */ >>+ __u32 flags; >>+ >>+ /** >>+ * Command streamer cycles as read from the command streamer >>+ * register at 0x358 offset. >>+ */ >>+ __u64 cs_cycles; >>+ >>+ /** Frequency of the cs cycles in Hz. */ >>+ __u64 cs_frequency; >>+ >>+ /** >>+ * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the >>+ * cs_cycles register using the reference clockid set by the user. >>+ * cpu_timestamp[1] is the time taken in ns to read the lower dword of >>+ * the cs_cycles register. >>+ */ >>+ __u64 cpu_timestamp[2]; >>+ >>+ /** >>+ * Reference clock id for CPU timestamp. For definition, see >>+ * clock_gettime(2) and perf_event_open(2). Supported clock ids are >>+ * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, >>+ * CLOCK_TAI. >>+ */ >>+ __s32 clockid; >>+ >>+ /** Must be zero. */ >>+ __u32 rsvd; >>+}; >>+ >> /** >> * struct drm_i915_query_engine_info >> * > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy 2021-04-23 15:11 ` Umesh Nerlige Ramappa @ 2021-04-23 15:21 ` Lionel Landwerlin 0 siblings, 0 replies; 13+ messages in thread From: Lionel Landwerlin @ 2021-04-23 15:21 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx, Chris Wilson On 23/04/2021 18:11, Umesh Nerlige Ramappa wrote: > On Fri, Apr 23, 2021 at 10:05:34AM +0300, Lionel Landwerlin wrote: >> On 21/04/2021 20:28, Umesh Nerlige Ramappa wrote: >>> Perf measurements rely on CPU and engine timestamps to correlate >>> events of interest across these time domains. Current mechanisms get >>> these timestamps separately and the calculated delta between these >>> timestamps lack enough accuracy. >>> >>> To improve the accuracy of these time measurements to within a few us, >>> add a query that returns the engine and cpu timestamps captured as >>> close to each other as possible. >>> >>> v2: (Tvrtko) >>> - document clock reference used >>> - return cpu timestamp always >>> - capture cpu time just before lower dword of cs timestamp >>> >>> v3: (Chris) >>> - use uncore-rpm >>> - use __query_cs_timestamp helper >>> >>> v4: (Lionel) >>> - Kernel perf subsytem allows users to specify the clock id to be used >>> in perf_event_open. This clock id is used by the perf subsystem to >>> return the appropriate cpu timestamp in perf events. Similarly, let >>> the user pass the clockid to this query so that cpu timestamp >>> corresponds to the clock id requested. >>> >>> v5: (Tvrtko) >>> - Use normal ktime accessors instead of fast versions >>> - Add more uApi documentation >>> >>> v6: (Lionel) >>> - Move switch out of spinlock >>> >>> v7: (Chris) >>> - cs_timestamp is a misnomer, use cs_cycles instead >>> - return the cs cycle frequency as well in the query >>> >>> v8: >>> - Add platform and engine specific checks >>> >>> v9: (Lionel) >>> - Return 2 cpu timestamps in the query - captured before and after the >>> register read >>> >>> v10: (Chris) >>> - Use local_clock() to measure time taken to read lower dword of >>> register and return it to user. >>> >>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> >>> --- >>> drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ >>> include/uapi/drm/i915_drm.h | 48 ++++++++++ >>> 2 files changed, 193 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_query.c >>> b/drivers/gpu/drm/i915/i915_query.c >>> index fed337ad7b68..25b96927ab92 100644 >>> --- a/drivers/gpu/drm/i915/i915_query.c >>> +++ b/drivers/gpu/drm/i915/i915_query.c >>> @@ -6,6 +6,8 @@ >>> #include <linux/nospec.h> >>> +#include "gt/intel_engine_pm.h" >>> +#include "gt/intel_engine_user.h" >>> #include "i915_drv.h" >>> #include "i915_perf.h" >>> #include "i915_query.h" >>> @@ -90,6 +92,148 @@ static int query_topology_info(struct >>> drm_i915_private *dev_priv, >>> return total_length; >>> } >>> +typedef u64 (*__ktime_func_t)(void); >>> +static __ktime_func_t __clock_id_to_func(clockid_t clk_id) >>> +{ >>> + /* >>> + * Use logic same as the perf subsystem to allow user to select >>> the >>> + * reference clock id to be used for timestamps. >>> + */ >>> + switch (clk_id) { >>> + case CLOCK_MONOTONIC: >>> + return &ktime_get_ns; >>> + case CLOCK_MONOTONIC_RAW: >>> + return &ktime_get_raw_ns; >>> + case CLOCK_REALTIME: >>> + return &ktime_get_real_ns; >>> + case CLOCK_BOOTTIME: >>> + return &ktime_get_boottime_ns; >>> + case CLOCK_TAI: >>> + return &ktime_get_clocktai_ns; >>> + default: >>> + return NULL; >>> + } >>> +} >>> + >>> +static inline int >>> +__read_timestamps(struct intel_uncore *uncore, >>> + i915_reg_t lower_reg, >>> + i915_reg_t upper_reg, >>> + u64 *cs_ts, >>> + u64 *cpu_ts, >>> + __ktime_func_t cpu_clock) >>> +{ >>> + u32 upper, lower, old_upper, loop = 0; >>> + >>> + upper = intel_uncore_read_fw(uncore, upper_reg); >>> + do { >>> + cpu_ts[1] = local_clock(); >>> + cpu_ts[0] = cpu_clock(); >>> + lower = intel_uncore_read_fw(uncore, lower_reg); >>> + cpu_ts[1] = local_clock() - cpu_ts[1]; >>> + old_upper = upper; >>> + upper = intel_uncore_read_fw(uncore, upper_reg); >>> + } while (upper != old_upper && loop++ < 2); >>> + >>> + *cs_ts = (u64)upper << 32 | lower; >>> + >>> + return 0; >>> +} >>> + >>> +static int >>> +__query_cs_cycles(struct intel_engine_cs *engine, >>> + u64 *cs_ts, u64 *cpu_ts, >>> + __ktime_func_t cpu_clock) >>> +{ >>> + struct intel_uncore *uncore = engine->uncore; >>> + enum forcewake_domains fw_domains; >>> + u32 base = engine->mmio_base; >>> + intel_wakeref_t wakeref; >>> + int ret; >>> + >>> + fw_domains = intel_uncore_forcewake_for_reg(uncore, >>> + RING_TIMESTAMP(base), >>> + FW_REG_READ); >>> + >>> + with_intel_runtime_pm(uncore->rpm, wakeref) { >>> + spin_lock_irq(&uncore->lock); >>> + intel_uncore_forcewake_get__locked(uncore, fw_domains); >>> + >>> + ret = __read_timestamps(uncore, >>> + RING_TIMESTAMP(base), >>> + RING_TIMESTAMP_UDW(base), >>> + cs_ts, >>> + cpu_ts, >>> + cpu_clock); >>> + >>> + intel_uncore_forcewake_put__locked(uncore, fw_domains); >>> + spin_unlock_irq(&uncore->lock); >>> + } >>> + >>> + return ret; >>> +} >>> + >>> +static int >>> +query_cs_cycles(struct drm_i915_private *i915, >>> + struct drm_i915_query_item *query_item) >>> +{ >>> + struct drm_i915_query_cs_cycles __user *query_ptr; >>> + struct drm_i915_query_cs_cycles query; >>> + struct intel_engine_cs *engine; >>> + __ktime_func_t cpu_clock; >>> + int ret; >>> + >>> + if (INTEL_GEN(i915) < 6) >>> + return -ENODEV; > > Less than gen6 is handled here early on. > >>> + >>> + query_ptr = u64_to_user_ptr(query_item->data_ptr); >>> + ret = copy_query_item(&query, sizeof(query), sizeof(query), >>> query_item); >>> + if (ret != 0) >>> + return ret; >>> + >>> + if (query.flags) >>> + return -EINVAL; >>> + >>> + if (query.rsvd) >>> + return -EINVAL; >>> + >>> + cpu_clock = __clock_id_to_func(query.clockid); >>> + if (!cpu_clock) >>> + return -EINVAL; >>> + >>> + engine = intel_engine_lookup_user(i915, >>> + query.engine.engine_class, >>> + query.engine.engine_instance); >>> + if (!engine) >>> + return -EINVAL; >>> + >>> + if (IS_GEN(i915, 6) && >>> + query.engine.engine_class != I915_ENGINE_CLASS_RENDER) >>> + return -ENODEV; >> >> >> Thanks a bunch for rebasing this. >> >> My only comment on this patch would be : don't we want >> IS_GEN_RANGE(i915, 1, 6) instead of IS_GEN(i915, 6) ? >> >> (assuming gen1 is a thing...) > > Less than gen6 check is above at function entry. On gen6, only render > works, so I wait until I can get the engine to check that. Ah okay, I thought we could go for parity with REG_READ which seems to go back to Gen4. But it's not important at least for mesa because we probably only case about gen7+. Hopefuly nobody else has objections : Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Thanks, -Lionel > > Thanks, > Umesh > >> >> >> -Lionel >> >> >>> + >>> + query.cs_frequency = engine->gt->clock_frequency; >>> + ret = __query_cs_cycles(engine, >>> + &query.cs_cycles, >>> + query.cpu_timestamp, >>> + cpu_clock); >>> + if (ret) >>> + return ret; >>> + >>> + if (put_user(query.cs_frequency, &query_ptr->cs_frequency)) >>> + return -EFAULT; >>> + >>> + if (put_user(query.cpu_timestamp[0], >>> &query_ptr->cpu_timestamp[0])) >>> + return -EFAULT; >>> + >>> + if (put_user(query.cpu_timestamp[1], >>> &query_ptr->cpu_timestamp[1])) >>> + return -EFAULT; >>> + >>> + if (put_user(query.cs_cycles, &query_ptr->cs_cycles)) >>> + return -EFAULT; >>> + >>> + return sizeof(query); >>> +} >>> + >>> static int >>> query_engine_info(struct drm_i915_private *i915, >>> struct drm_i915_query_item *query_item) >>> @@ -424,6 +568,7 @@ static int (* const i915_query_funcs[])(struct >>> drm_i915_private *dev_priv, >>> query_topology_info, >>> query_engine_info, >>> query_perf_config, >>> + query_cs_cycles, >>> }; >>> int i915_query_ioctl(struct drm_device *dev, void *data, struct >>> drm_file *file) >>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>> index 6a34243a7646..08b00f1709b5 100644 >>> --- a/include/uapi/drm/i915_drm.h >>> +++ b/include/uapi/drm/i915_drm.h >>> @@ -2230,6 +2230,10 @@ struct drm_i915_query_item { >>> #define DRM_I915_QUERY_TOPOLOGY_INFO 1 >>> #define DRM_I915_QUERY_ENGINE_INFO 2 >>> #define DRM_I915_QUERY_PERF_CONFIG 3 >>> + /** >>> + * Query Command Streamer timestamp register. >>> + */ >>> +#define DRM_I915_QUERY_CS_CYCLES 4 >>> /* Must be kept compact -- no holes and well documented */ >>> /** >>> @@ -2397,6 +2401,50 @@ struct drm_i915_engine_info { >>> __u64 rsvd1[4]; >>> }; >>> +/** >>> + * struct drm_i915_query_cs_cycles >>> + * >>> + * The query returns the command streamer cycles and the frequency >>> that can be >>> + * used to calculate the command streamer timestamp. In addition >>> the query >>> + * returns a set of cpu timestamps that indicate when the command >>> streamer cycle >>> + * count was captured. >>> + */ >>> +struct drm_i915_query_cs_cycles { >>> + /** Engine for which command streamer cycles is queried. */ >>> + struct i915_engine_class_instance engine; >>> + >>> + /** Must be zero. */ >>> + __u32 flags; >>> + >>> + /** >>> + * Command streamer cycles as read from the command streamer >>> + * register at 0x358 offset. >>> + */ >>> + __u64 cs_cycles; >>> + >>> + /** Frequency of the cs cycles in Hz. */ >>> + __u64 cs_frequency; >>> + >>> + /** >>> + * CPU timestamps in ns. cpu_timestamp[0] is captured before >>> reading the >>> + * cs_cycles register using the reference clockid set by the user. >>> + * cpu_timestamp[1] is the time taken in ns to read the lower >>> dword of >>> + * the cs_cycles register. >>> + */ >>> + __u64 cpu_timestamp[2]; >>> + >>> + /** >>> + * Reference clock id for CPU timestamp. For definition, see >>> + * clock_gettime(2) and perf_event_open(2). Supported clock ids >>> are >>> + * CLOCK_MONOTONIC, CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, >>> CLOCK_BOOTTIME, >>> + * CLOCK_TAI. >>> + */ >>> + __s32 clockid; >>> + >>> + /** Must be zero. */ >>> + __u32 rsvd; >>> +}; >>> + >>> /** >>> * struct drm_i915_query_engine_info >>> * >> >> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy 2021-04-23 7:05 ` Lionel Landwerlin 2021-04-23 15:11 ` Umesh Nerlige Ramappa @ 2021-04-26 11:53 ` Jani Nikula 1 sibling, 0 replies; 13+ messages in thread From: Jani Nikula @ 2021-04-26 11:53 UTC (permalink / raw) To: Lionel Landwerlin, Umesh Nerlige Ramappa, intel-gfx; +Cc: Chris Wilson On Fri, 23 Apr 2021, Lionel Landwerlin <lionel.g.landwerlin@intel.com> wrote: > On 21/04/2021 20:28, Umesh Nerlige Ramappa wrote: >> +static int >> +query_cs_cycles(struct drm_i915_private *i915, >> + struct drm_i915_query_item *query_item) >> +{ >> + struct drm_i915_query_cs_cycles __user *query_ptr; >> + struct drm_i915_query_cs_cycles query; >> + struct intel_engine_cs *engine; >> + __ktime_func_t cpu_clock; >> + int ret; >> + >> + if (INTEL_GEN(i915) < 6) >> + return -ENODEV; >> + [...] >> + >> + if (IS_GEN(i915, 6) && >> + query.engine.engine_class != I915_ENGINE_CLASS_RENDER) >> + return -ENODEV; > > > Thanks a bunch for rebasing this. > > My only comment on this patch would be : don't we want > IS_GEN_RANGE(i915, 1, 6) instead of IS_GEN(i915, 6) ? Please see the new deprecation comments in i915_drv.h. We're moving from GEN to VER. In short, please use the new VER macros for individual components instead of the generic GEN. Thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles 2021-04-21 17:28 [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles Umesh Nerlige Ramappa 2021-04-21 17:28 ` [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy Umesh Nerlige Ramappa @ 2021-04-21 18:26 ` Patchwork 2021-04-21 18:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-04-22 2:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-21 18:26 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89314/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:2234: warning: Incorrect use of kernel-doc format: * Query Command Streamer timestamp register. ./include/uapi/drm/i915_drm.h:2420: warning: Incorrect use of kernel-doc format: * Command streamer cycles as read from the command streamer ./include/uapi/drm/i915_drm.h:2429: warning: Incorrect use of kernel-doc format: * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the ./include/uapi/drm/i915_drm.h:2437: warning: Incorrect use of kernel-doc format: * Reference clock id for CPU timestamp. For definition, see ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'engine' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'flags' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_cycles' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_frequency' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cpu_timestamp' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'clockid' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'rsvd' not described in 'drm_i915_query_cs_cycles' ./drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:102: warning: Function parameter or member 'ww' not described in 'i915_gem_shrink' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'jump_whitelist' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'shadow_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Function parameter or member 'batch_map' not described in 'intel_engine_cmd_parser' ./drivers/gpu/drm/i915/i915_cmd_parser.c:1420: warning: Excess function parameter 'trampoline' description in 'intel_engine_cmd_parser' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add support for querying engine cycles 2021-04-21 17:28 [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles Umesh Nerlige Ramappa 2021-04-21 17:28 ` [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy Umesh Nerlige Ramappa 2021-04-21 18:26 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles Patchwork @ 2021-04-21 18:50 ` Patchwork 2021-04-22 2:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 3 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-21 18:50 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 2465 bytes --] == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89314/ State : success == Summary == CI Bug Log - changes from CI_DRM_9993 -> Patchwork_19966 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/index.html Known issues ------------ Here are the changes found in Patchwork_19966 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html #### Possible fixes #### * igt@kms_frontbuffer_tracking@basic: - {fi-rkl-11500t}: [SKIP][3] ([i915#1849] / [i915#3180]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180 Participating hosts (42 -> 39) ------------------------------ Missing (3): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus Build changes ------------- * IGT: IGT_6072 -> IGTPW_5757 * Linux: CI_DRM_9993 -> Patchwork_19966 CI-20190529: 20190529 CI_DRM_9993: 629d3809e6d926c77ba5e9c5405e64eeba564560 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_5757: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5757/index.html IGT_6072: 0a51f49df9f5ca535fc0206a27a6780de6b52320 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_19966: ca44314a5a5d70c39de70db3f333a2228809e1d4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ca44314a5a5d i915/query: Correlate engine and cpu timestamps with better accuracy == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/index.html [-- Attachment #1.2: Type: text/html, Size: 3104 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Add support for querying engine cycles 2021-04-21 17:28 [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles Umesh Nerlige Ramappa ` (2 preceding siblings ...) 2021-04-21 18:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-04-22 2:17 ` Patchwork 3 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-22 2:17 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30261 bytes --] == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89314/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9993_full -> Patchwork_19966_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_19966_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_19966_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_19966_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html New tests --------- New tests have been introduced between CI_DRM_9993_full and Patchwork_19966_full: ### New IGT tests (2) ### * igt@i915_query@cs-cycles: - Statuses : 6 pass(s) - Exec time: [0.00, 0.05] s * igt@i915_query@cs-cycles-invalid: - Statuses : 6 pass(s) - Exec time: [0.00, 0.04] s Known issues ------------ Here are the changes found in Patchwork_19966_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-clear: - shard-iclb: [PASS][2] -> [FAIL][3] ([i915#3160]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb7/igt@gem_create@create-clear.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb3/igt@gem_create@create-clear.html * igt@gem_ctx_bad_destroy@invalid-pad: - shard-skl: NOTRUN -> [DMESG-WARN][4] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@gem_ctx_bad_destroy@invalid-pad.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb2/igt@gem_ctx_persistence@process.html * igt@gem_ctx_sseu@mmap-args: - shard-tglb: NOTRUN -> [SKIP][6] ([i915#280]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb6/igt@gem_ctx_sseu@mmap-args.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl4/igt@gem_exec_fair@basic-deadline.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl6/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271]) +126 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl4/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html - shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk8/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_reloc@basic-wide-active@bcs0: - shard-apl: NOTRUN -> [FAIL][16] ([i915#2389]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl3/igt@gem_exec_reloc@basic-wide-active@bcs0.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-apl1/igt@gem_exec_suspend@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl6/igt@gem_exec_suspend@basic-s3.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl4/igt@gem_huc_copy@huc-copy.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb6/igt@gem_pwrite@basic-exhaustion.html * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled: - shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +41 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk5/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html - shard-iclb: NOTRUN -> [SKIP][22] ([i915#768]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#3297]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html - shard-iclb: NOTRUN -> [SKIP][24] ([i915#3297]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb7/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][25] ([i915#3002]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb6/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@set-cache-level: - shard-snb: NOTRUN -> [FAIL][26] ([i915#3324]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb5/igt@gem_userptr_blits@set-cache-level.html - shard-skl: NOTRUN -> [FAIL][27] ([i915#3324]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl10/igt@gem_userptr_blits@set-cache-level.html * igt@gen9_exec_parse@bb-chained: - shard-iclb: NOTRUN -> [SKIP][28] ([fdo#112306]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb5/igt@gen9_exec_parse@bb-chained.html - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#112306]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb2/igt@gen9_exec_parse@bb-chained.html * igt@gen9_exec_parse@bb-large: - shard-skl: NOTRUN -> [FAIL][30] ([i915#3296]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl1/igt@gen9_exec_parse@bb-large.html - shard-apl: NOTRUN -> [FAIL][31] ([i915#3296]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl2/igt@gen9_exec_parse@bb-large.html * igt@i915_hangman@engine-error@vecs0: - shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271]) +123 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl4/igt@i915_hangman@engine-error@vecs0.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][33] ([i915#454]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl9/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rpm@system-suspend: - shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#151]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@i915_pm_rpm@system-suspend.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl9/igt@i915_pm_rpm@system-suspend.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][36] ([i915#2782]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb7/igt@i915_selftest@live@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: NOTRUN -> [FAIL][37] ([i915#2521]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_big_fb@y-tiled-8bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#110725] / [fdo#111614]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb3/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][41] ([fdo#110723]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_ccs@pipe-a-ccs-on-another-bo: - shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271]) +298 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb2/igt@kms_ccs@pipe-a-ccs-on-another-bo.html * igt@kms_ccs@pipe-a-random-ccs-data: - shard-iclb: [PASS][43] -> [DMESG-WARN][44] ([i915#3219]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb4/igt@kms_ccs@pipe-a-random-ccs-data.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@kms_ccs@pipe-a-random-ccs-data.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic: - shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111304]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic.html * igt@kms_chamelium@dp-mode-timings: - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +16 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl8/igt@kms_chamelium@dp-mode-timings.html * igt@kms_chamelium@hdmi-hpd-storm-disable: - shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +9 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl8/igt@kms_chamelium@hdmi-hpd-storm-disable.html * igt@kms_color@pipe-d-ctm-green-to-red: - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#1149]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb7/igt@kms_color@pipe-d-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +12 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html - shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +8 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html - shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html - shard-glk: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +4 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb2/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_color_chamelium@pipe-d-ctm-0-5: - shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-0-5.html * igt@kms_content_protection@uevent: - shard-kbl: NOTRUN -> [FAIL][55] ([i915#2105]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl2/igt@kms_content_protection@uevent.html - shard-apl: NOTRUN -> [FAIL][56] ([i915#2105]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding: - shard-tglb: NOTRUN -> [SKIP][57] ([i915#3319]) +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen: - shard-skl: [PASS][58] -> [FAIL][59] ([i915#54]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html * igt@kms_cursor_crc@pipe-d-cursor-dpms: - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109278]) +8 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-dpms.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][61] -> [FAIL][62] ([i915#2346]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109274]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb2/igt@kms_flip@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: NOTRUN -> [DMESG-WARN][64] ([i915#180]) +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: NOTRUN -> [FAIL][65] ([i915#2122]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs: - shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2672]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2672]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html * igt@kms_frontbuffer_tracking@basic: - shard-skl: [PASS][68] -> [FAIL][69] ([i915#49]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@kms_frontbuffer_tracking@basic.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl9/igt@kms_frontbuffer_tracking@basic.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render: - shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109280]) +18 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu: - shard-tglb: NOTRUN -> [SKIP][71] ([fdo#111825]) +20 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc: - shard-skl: [PASS][72] -> [SKIP][73] ([fdo#109271]) +10 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl9/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][74] -> [DMESG-WARN][75] ([i915#180]) +4 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#533]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d: - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#533]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#533]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265]) +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][80] ([fdo#108145] / [i915#265]) +4 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][81] ([i915#265]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html - shard-kbl: NOTRUN -> [FAIL][82] ([i915#265]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-glk: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk5/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html - shard-kbl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][85] -> [FAIL][86] ([fdo#108145] / [i915#265]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-d-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][87] ([fdo#112054]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb5/igt@kms_plane_lowres@pipe-d-tiling-yf.html * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping: - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2733]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658]) +2 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658]) +2 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-iclb: NOTRUN -> [SKIP][91] ([i915#658]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb3/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html - shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +3 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][94] -> [SKIP][95] ([fdo#109441]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109441]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_setmode@invalid-clone-single-crtc: - shard-skl: NOTRUN -> [WARN][97] ([i915#2100]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl9/igt@kms_setmode@invalid-clone-single-crtc.html * igt@kms_vblank@pipe-d-wait-forked-hang: - shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271]) +228 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl6/igt@kms_vblank@pipe-d-wait-forked-hang.html * igt@kms_vrr@flip-dpms: - shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109502]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb8/igt@kms_vrr@flip-dpms.html - shard-tglb: NOTRUN -> [SKIP][100] ([fdo#109502]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb3/igt@kms_vrr@flip-dpms.html * igt@kms_writeback@writeback-check-output: - shard-apl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2437]) +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl8/igt@kms_writeback@writeback-check-output.html * igt@perf@gen12-unprivileged-single-ctx-counters: - shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109289]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@perf@gen12-unprivileged-single-ctx-counters.html * igt@perf@polling-small-buf: - shard-skl: [PASS][103] -> [FAIL][104] ([i915#1722]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl8/igt@perf@polling-small-buf.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@perf@polling-small-buf.html * igt@prime_nv_test@i915_import_gtt_mmap: - shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109291]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb8/igt@prime_nv_test@i915_import_gtt_mmap.html - shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109291]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb2/igt@prime_nv_test@i915_import_gtt_mmap.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2994]) +3 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-apl8/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@fair-7: - shard-skl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl4/igt@sysfs_clients@fair-7.html * igt@sysfs_clients@sema-50: - shard-kbl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994]) +4 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl7/igt@sysfs_clients@sema-50.html * igt@sysfs_clients@split-25: - shard-tglb: NOTRUN -> [SKIP][110] ([i915#2994]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb6/igt@sysfs_clients@split-25.html - shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk6/igt@sysfs_clients@split-25.html - shard-iclb: NOTRUN -> [SKIP][112] ([i915#2994]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb8/igt@sysfs_clients@split-25.html #### Possible fixes #### * igt@gem_create@create-clear: - shard-skl: [FAIL][113] ([i915#1888] / [i915#3160]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl8/igt@gem_create@create-clear.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl1/igt@gem_create@create-clear.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][115] ([i915#2846]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk9/igt@gem_exec_fair@basic-deadline.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk4/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [FAIL][117] ([i915#2842]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][119] ([i915#2842]) -> [PASS][120] +1 similar issue [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][121] ([i915#2842]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-iclb: [FAIL][123] ([i915#2849]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [FAIL][125] ([i915#2428]) -> [PASS][126] +1 similar issue [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_workarounds@suspend-resume: - shard-kbl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128] +1 similar issue [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl6/igt@gem_workarounds@suspend-resume.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl3/igt@gem_workarounds@suspend-resume.html * igt@i915_selftest@mock@requests: - shard-skl: [INCOMPLETE][129] ([i915#198]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl6/igt@i915_selftest@mock@requests.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl6/igt@i915_selftest@mock@requests.html * igt@kms_cursor_crc@pipe-c-cursor-256x256-onscreen: - shard-kbl: [FAIL][131] ([i915#54]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-onscreen.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-256x256-onscreen.html - shard-glk: [FAIL][133] ([i915#54]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-glk1/igt@kms_cursor_crc@pipe-c-cursor-256x256-onscreen.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-glk6/igt@kms_cursor_crc@pipe-c-cursor-256x256-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-64x21-random: - shard-skl: [SKIP][135] ([fdo#109271]) -> [PASS][136] +14 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9993/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [FAIL][137] ([i915#2346]) -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm- == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19966/index.html [-- Attachment #1.2: Type: text/html, Size: 33832 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles @ 2021-04-27 21:49 Umesh Nerlige Ramappa 2021-04-27 22:16 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 0 siblings, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-04-27 21:49 UTC (permalink / raw) To: intel-gfx; +Cc: Chris Wilson This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Test-with: 20210421172046.65062-1-umesh.nerlige.ramappa@intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 48 ++++++++++ 2 files changed, 193 insertions(+) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles 2021-04-27 21:49 [Intel-gfx] [PATCH 0/1] " Umesh Nerlige Ramappa @ 2021-04-27 22:16 ` Patchwork 0 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-27 22:16 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89560/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:2234: warning: Incorrect use of kernel-doc format: * Query Command Streamer timestamp register. ./include/uapi/drm/i915_drm.h:2420: warning: Incorrect use of kernel-doc format: * Command streamer cycles as read from the command streamer ./include/uapi/drm/i915_drm.h:2429: warning: Incorrect use of kernel-doc format: * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the ./include/uapi/drm/i915_drm.h:2437: warning: Incorrect use of kernel-doc format: * Reference clock id for CPU timestamp. For definition, see ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'engine' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'flags' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_cycles' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_frequency' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cpu_timestamp' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'clockid' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'rsvd' not described in 'drm_i915_query_cs_cycles' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles @ 2021-04-27 21:53 Umesh Nerlige Ramappa 2021-04-27 23:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 0 siblings, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-04-27 21:53 UTC (permalink / raw) To: intel-gfx This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Test-with: 20210421172046.65062-1-umesh.nerlige.ramappa@intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 145 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 48 ++++++++++ 2 files changed, 193 insertions(+) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles 2021-04-27 21:53 [Intel-gfx] [PATCH 0/1] " Umesh Nerlige Ramappa @ 2021-04-27 23:55 ` Patchwork 0 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-27 23:55 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89561/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:2234: warning: Incorrect use of kernel-doc format: * Query Command Streamer timestamp register. ./include/uapi/drm/i915_drm.h:2420: warning: Incorrect use of kernel-doc format: * Command streamer cycles as read from the command streamer ./include/uapi/drm/i915_drm.h:2429: warning: Incorrect use of kernel-doc format: * CPU timestamps in ns. cpu_timestamp[0] is captured before reading the ./include/uapi/drm/i915_drm.h:2437: warning: Incorrect use of kernel-doc format: * Reference clock id for CPU timestamp. For definition, see ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'engine' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'flags' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_cycles' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cs_frequency' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'cpu_timestamp' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'clockid' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2446: warning: Function parameter or member 'rsvd' not described in 'drm_i915_query_cs_cycles' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/1] Add support for querying engine cycles @ 2021-04-29 0:34 Umesh Nerlige Ramappa 2021-04-29 1:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 0 siblings, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-04-29 0:34 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, jason This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch v4: Split cpu timestamp array into timestamp and delta for cleaner API Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Test-with: 20210429002959.69473-1-umesh.nerlige.ramappa@intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 148 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 52 +++++++++++ 2 files changed, 200 insertions(+) -- 2.20.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles 2021-04-29 0:34 [PATCH 0/1] " Umesh Nerlige Ramappa @ 2021-04-29 1:34 ` Patchwork 0 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-04-29 1:34 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89615/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:2234: warning: Incorrect use of kernel-doc format: * Query Command Streamer timestamp register. ./include/uapi/drm/i915_drm.h:2420: warning: Incorrect use of kernel-doc format: * Command streamer cycles as read from the command streamer ./include/uapi/drm/i915_drm.h:2429: warning: Incorrect use of kernel-doc format: * CPU timestamp in ns. The timestamp is captured before reading the ./include/uapi/drm/i915_drm.h:2435: warning: Incorrect use of kernel-doc format: * Time delta in ns captured around reading the lower dword of the ./include/uapi/drm/i915_drm.h:2441: warning: Incorrect use of kernel-doc format: * Reference clock id for CPU timestamp. For definition, see ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'engine' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'flags' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'cs_cycles' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'cs_frequency' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'cpu_timestamp' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'cpu_delta' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'clockid' not described in 'drm_i915_query_cs_cycles' ./include/uapi/drm/i915_drm.h:2450: warning: Function parameter or member 'rsvd' not described in 'drm_i915_query_cs_cycles' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/1] Add support for querying engine cycles @ 2021-05-04 0:12 Umesh Nerlige Ramappa 2021-05-04 1:12 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 0 siblings, 1 reply; 13+ messages in thread From: Umesh Nerlige Ramappa @ 2021-05-04 0:12 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, jason This is just a refresh of the earlier patch along with cover letter for the IGT testing. The query provides the engine cs cycles counter. v2: Use GRAPHICS_VER() instead of IG_GEN() v3: Add R-b to the patch v4: Split cpu timestamp array into timestamp and delta for cleaner API v5: Add width of the cs cycles to the uapi Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Test-with: 20210504001003.69445-1-umesh.nerlige.ramappa@intel.com Umesh Nerlige Ramappa (1): i915/query: Correlate engine and cpu timestamps with better accuracy drivers/gpu/drm/i915/i915_query.c | 157 ++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 56 +++++++++++ 2 files changed, 213 insertions(+) -- 2.20.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles 2021-05-04 0:12 [PATCH 0/1] " Umesh Nerlige Ramappa @ 2021-05-04 1:12 ` Patchwork 0 siblings, 0 replies; 13+ messages in thread From: Patchwork @ 2021-05-04 1:12 UTC (permalink / raw) To: Umesh Nerlige Ramappa; +Cc: intel-gfx == Series Details == Series: Add support for querying engine cycles URL : https://patchwork.freedesktop.org/series/89766/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./include/uapi/drm/i915_drm.h:2234: warning: Incorrect use of kernel-doc format: * Query Command Streamer timestamp register. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-05-04 1:12 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-04-21 17:28 [Intel-gfx] [PATCH 0/1] Add support for querying engine cycles Umesh Nerlige Ramappa 2021-04-21 17:28 ` [Intel-gfx] [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy Umesh Nerlige Ramappa 2021-04-23 7:05 ` Lionel Landwerlin 2021-04-23 15:11 ` Umesh Nerlige Ramappa 2021-04-23 15:21 ` Lionel Landwerlin 2021-04-26 11:53 ` Jani Nikula 2021-04-21 18:26 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Add support for querying engine cycles Patchwork 2021-04-21 18:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-04-22 2:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-04-27 21:49 [Intel-gfx] [PATCH 0/1] " Umesh Nerlige Ramappa 2021-04-27 22:16 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 2021-04-27 21:53 [Intel-gfx] [PATCH 0/1] " Umesh Nerlige Ramappa 2021-04-27 23:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 2021-04-29 0:34 [PATCH 0/1] " Umesh Nerlige Ramappa 2021-04-29 1:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork 2021-05-04 0:12 [PATCH 0/1] " Umesh Nerlige Ramappa 2021-05-04 1:12 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for " Patchwork
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