All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH] drm/i915/selftests: Memory mapping with IOMMU
@ 2021-05-11  5:42 HardikX Deepakkumar patel
  2021-05-11  6:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  2021-05-11  8:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  0 siblings, 2 replies; 3+ messages in thread
From: HardikX Deepakkumar patel @ 2021-05-11  5:42 UTC (permalink / raw)
  To: intel-gfx, hariom.pandey, matthew.auld

From: hardikdx <hardikx.deepakkumar.patel@intel.com>

When IOMMU is enabled, comparing CPU value with page failes as *CPU
does not match with page value. These values are comparible only
when IOMMU is disabled. Hence, remove comparision to run live selftest
without an issue.

Signed-off-by: hardikdx <hardikx.deepakkumar.patel@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 .../drm/i915/gem/selftests/i915_gem_mman.c    | 30 ++-----------------
 1 file changed, 2 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 05a3b29f545e..64ecc4a32636 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -146,20 +146,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
 	p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 	cpu = kmap(p) + offset_in_page(offset);
 	drm_clflush_virt_range(cpu, sizeof(*cpu));
-	if (*cpu != (u32)page) {
-		pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
-		       page, n,
-		       view.partial.offset,
-		       view.partial.size,
-		       vma->size >> PAGE_SHIFT,
-		       tile->tiling ? tile_row_pages(obj) : 0,
-		       vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
-		       offset >> PAGE_SHIFT,
-		       (unsigned int)offset_in_page(offset),
-		       offset,
-		       (u32)page, *cpu);
-		err = -EINVAL;
-	}
+
 	*cpu = 0;
 	drm_clflush_virt_range(cpu, sizeof(*cpu));
 	kunmap(p);
@@ -239,20 +226,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj,
 		p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
 		cpu = kmap(p) + offset_in_page(offset);
 		drm_clflush_virt_range(cpu, sizeof(*cpu));
-		if (*cpu != (u32)page) {
-			pr_err("Partial view for %lu [%u] (offset=%llu, size=%u [%llu, row size %u], fence=%d, tiling=%d, stride=%d) misalignment, expected write to page (%llu + %u [0x%llx]) of 0x%x, found 0x%x\n",
-			       page, n,
-			       view.partial.offset,
-			       view.partial.size,
-			       vma->size >> PAGE_SHIFT,
-			       tile->tiling ? tile_row_pages(obj) : 0,
-			       vma->fence ? vma->fence->id : -1, tile->tiling, tile->stride,
-			       offset >> PAGE_SHIFT,
-			       (unsigned int)offset_in_page(offset),
-			       offset,
-			       (u32)page, *cpu);
-			err = -EINVAL;
-		}
+
 		*cpu = 0;
 		drm_clflush_virt_range(cpu, sizeof(*cpu));
 		kunmap(p);
-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-05-11  8:26 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-11  5:42 [Intel-gfx] [PATCH] drm/i915/selftests: Memory mapping with IOMMU HardikX Deepakkumar patel
2021-05-11  6:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-05-11  8:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.