From: no-reply@patchew.org To: david.edmondson@oracle.com Cc: qemu-devel@nongnu.org, ehabkost@redhat.com, kvm@vger.kernel.org, mtosatti@redhat.com, richard.henderson@linaro.org, david.edmondson@oracle.com, babu.moger@amd.com, pbonzini@redhat.com Subject: Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM Date: Thu, 20 May 2021 08:15:50 -0700 (PDT) [thread overview] Message-ID: <162152374779.4995.3945715207326940335@0addf061776e> (raw) In-Reply-To: <20210520145647.3483809-1-david.edmondson@oracle.com> Patchew URL: https://patchew.org/QEMU/20210520145647.3483809-1-david.edmondson@oracle.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210520145647.3483809-1-david.edmondson@oracle.com Subject: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20210520145647.3483809-1-david.edmondson@oracle.com -> patchew/20210520145647.3483809-1-david.edmondson@oracle.com Switched to a new branch 'test' 9761ad4 target/i386: Manipulate only AMD XSAVE state on AMD fcba7d5 target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd 0493da2 target/i386: Introduce AMD X86XSaveArea sub-union e8d400c target/i386: Prepare for per-vendor X86XSaveArea layout 5a78b06 target/i386: Clarify the padding requirements of X86XSaveArea ba3c3af target/i386: Use constants for XSAVE offsets 844afa9 target/i386: Declare constants for XSAVE offsets === OUTPUT BEGIN === 1/7 Checking commit 844afa9929e3 (target/i386: Declare constants for XSAVE offsets) WARNING: line over 80 characters #60: FILE: target/i386/cpu.h:1352: +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); WARNING: line over 80 characters #63: FILE: target/i386/cpu.h:1354: +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); total: 0 errors, 2 warnings, 48 lines checked Patch 1/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 2/7 Checking commit ba3c3afe9795 (target/i386: Use constants for XSAVE offsets) 3/7 Checking commit 5a78b069f6d4 (target/i386: Clarify the padding requirements of X86XSaveArea) 4/7 Checking commit e8d400c3e40e (target/i386: Prepare for per-vendor X86XSaveArea layout) 5/7 Checking commit 0493da29bcd9 (target/i386: Introduce AMD X86XSaveArea sub-union) 6/7 Checking commit fcba7d58090d (target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd) 7/7 Checking commit 9761ad41cd68 (target/i386: Manipulate only AMD XSAVE state on AMD) ERROR: spaces required around that '+' (ctx:VxV) #90: FILE: target/i386/xsave_helper.c:53: + stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5)); ^ ERROR: spaces required around that '+' (ctx:VxV) #91: FILE: target/i386/xsave_helper.c:54: + stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6)); ^ ERROR: spaces required around that '+' (ctx:VxV) #92: FILE: target/i386/xsave_helper.c:55: + stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7)); ^ ERROR: spaces required around that '+' (ctx:VxV) #150: FILE: target/i386/xsave_helper.c:114: + env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8); ^ ERROR: spaces required around that '+' (ctx:VxV) #151: FILE: target/i386/xsave_helper.c:115: + env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16); ^ ERROR: spaces required around that '+' (ctx:VxV) #152: FILE: target/i386/xsave_helper.c:116: + env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24); ^ total: 6 errors, 0 warnings, 140 lines checked Patch 7/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210520145647.3483809-1-david.edmondson@oracle.com/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
WARNING: multiple messages have this Message-ID (diff)
From: no-reply@patchew.org To: david.edmondson@oracle.com Cc: ehabkost@redhat.com, kvm@vger.kernel.org, mtosatti@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, david.edmondson@oracle.com, babu.moger@amd.com, pbonzini@redhat.com Subject: Re: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM Date: Thu, 20 May 2021 08:15:50 -0700 (PDT) [thread overview] Message-ID: <162152374779.4995.3945715207326940335@0addf061776e> (raw) In-Reply-To: <20210520145647.3483809-1-david.edmondson@oracle.com> Patchew URL: https://patchew.org/QEMU/20210520145647.3483809-1-david.edmondson@oracle.com/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210520145647.3483809-1-david.edmondson@oracle.com Subject: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20210520145647.3483809-1-david.edmondson@oracle.com -> patchew/20210520145647.3483809-1-david.edmondson@oracle.com Switched to a new branch 'test' 9761ad4 target/i386: Manipulate only AMD XSAVE state on AMD fcba7d5 target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd 0493da2 target/i386: Introduce AMD X86XSaveArea sub-union e8d400c target/i386: Prepare for per-vendor X86XSaveArea layout 5a78b06 target/i386: Clarify the padding requirements of X86XSaveArea ba3c3af target/i386: Use constants for XSAVE offsets 844afa9 target/i386: Declare constants for XSAVE offsets === OUTPUT BEGIN === 1/7 Checking commit 844afa9929e3 (target/i386: Declare constants for XSAVE offsets) WARNING: line over 80 characters #60: FILE: target/i386/cpu.h:1352: +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); WARNING: line over 80 characters #63: FILE: target/i386/cpu.h:1354: +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); total: 0 errors, 2 warnings, 48 lines checked Patch 1/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 2/7 Checking commit ba3c3afe9795 (target/i386: Use constants for XSAVE offsets) 3/7 Checking commit 5a78b069f6d4 (target/i386: Clarify the padding requirements of X86XSaveArea) 4/7 Checking commit e8d400c3e40e (target/i386: Prepare for per-vendor X86XSaveArea layout) 5/7 Checking commit 0493da29bcd9 (target/i386: Introduce AMD X86XSaveArea sub-union) 6/7 Checking commit fcba7d58090d (target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd) 7/7 Checking commit 9761ad41cd68 (target/i386: Manipulate only AMD XSAVE state on AMD) ERROR: spaces required around that '+' (ctx:VxV) #90: FILE: target/i386/xsave_helper.c:53: + stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5)); ^ ERROR: spaces required around that '+' (ctx:VxV) #91: FILE: target/i386/xsave_helper.c:54: + stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6)); ^ ERROR: spaces required around that '+' (ctx:VxV) #92: FILE: target/i386/xsave_helper.c:55: + stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7)); ^ ERROR: spaces required around that '+' (ctx:VxV) #150: FILE: target/i386/xsave_helper.c:114: + env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8); ^ ERROR: spaces required around that '+' (ctx:VxV) #151: FILE: target/i386/xsave_helper.c:115: + env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16); ^ ERROR: spaces required around that '+' (ctx:VxV) #152: FILE: target/i386/xsave_helper.c:116: + env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24); ^ total: 6 errors, 0 warnings, 140 lines checked Patch 7/7 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20210520145647.3483809-1-david.edmondson@oracle.com/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com
next prev parent reply other threads:[~2021-05-20 15:16 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-20 14:56 [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 1/7] target/i386: Declare constants for XSAVE offsets David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 2/7] target/i386: Use " David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 3/7] target/i386: Clarify the padding requirements of X86XSaveArea David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 4/7] target/i386: Prepare for per-vendor X86XSaveArea layout David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 6/7] target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 14:56 ` [RFC PATCH 7/7] target/i386: Manipulate only AMD XSAVE state on AMD David Edmondson 2021-05-20 14:56 ` David Edmondson 2021-05-20 15:15 ` no-reply [this message] 2021-05-20 15:15 ` [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM no-reply 2021-06-08 8:24 ` David Edmondson 2021-06-08 8:24 ` David Edmondson 2021-07-01 21:24 ` Babu Moger 2021-07-01 21:32 ` David Edmondson 2021-07-01 21:32 ` David Edmondson 2021-06-11 16:01 ` Paolo Bonzini 2021-06-11 16:01 ` Paolo Bonzini 2021-06-14 16:21 ` David Edmondson 2021-06-14 16:21 ` David Edmondson
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