* [Intel-gfx] [PATCH 0/7] Pipe DMC Support
@ 2021-05-24 19:30 Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err Anusha Srivatsa
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
Adding the actual Pipe DMC bits.
This series is rebased on top of the new
"More DMC cleanup" series:
https://patchwork.freedesktop.org/series/90379/
Anusha Srivatsa (7):
drm/i915/dmc: s/DRM_ERROR/drm_err
drm/i915/dmc: Add intel_dmc_has_payload() helper
drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
drm/i915/dmc: Introduce DMC_FW_MAIN
drm/i915/xelpd: Pipe A DMC plugging
drm/i915/adl_p: Pipe B DMC Support
drm/i915/adl_p: Load DMC
.../drm/i915/display/intel_display_debugfs.c | 10 +-
.../drm/i915/display/intel_display_power.c | 21 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 212 ++++++++++--------
drivers/gpu/drm/i915/display/intel_dmc.h | 35 +++
drivers/gpu/drm/i915/i915_drv.h | 18 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
7 files changed, 178 insertions(+), 122 deletions(-)
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 2/7] drm/i915/dmc: Add intel_dmc_has_payload() helper Anusha Srivatsa
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
v2: use container_of() (Jani)
v3: Indentation fixes. (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 48 +++++++++++++-----------
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 560574dd929a..5887453ff302 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -395,6 +395,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
@@ -439,28 +440,28 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
header_len_bytes = dmc_header->header_len;
dmc_header_size = sizeof(*v1);
} else {
- DRM_ERROR("Unknown DMC fw header version: %u\n",
- dmc_header->header_ver);
+ drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
+ dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- DRM_ERROR("DMC firmware has wrong dmc header length "
- "(%u bytes)\n", header_len_bytes);
+ drm_err(&i915->drm, "DMC firmware has wrong dmc header length "
+ "(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
return 0;
}
for (i = 0; i < mmio_count; i++) {
if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
mmioaddr[i] > DMC_MMIO_END_RANGE) {
- DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
+ drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
+ mmioaddr[i]);
return 0;
}
dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
@@ -476,14 +477,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
goto error_truncated;
if (payload_size > dmc->max_fw_size) {
- DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
dmc->dmc_fw_size = dmc_header->fw_size;
dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
if (!dmc->dmc_payload) {
- DRM_ERROR("Memory allocation failed for dmc payload\n");
+ drm_err(&i915->drm, "Memory allocation failed for dmc payload\n");
return 0;
}
@@ -493,7 +494,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
return header_len_bytes + payload_size;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -503,6 +504,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries, dmc_offset;
const struct intel_fw_info *fw_info;
@@ -515,8 +517,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- DRM_ERROR("DMC firmware has unknown header version %u\n",
- package_header->header_ver);
+ drm_err(&i915->drm, "DMC firmware has unknown header version %u\n",
+ package_header->header_ver);
return 0;
}
@@ -529,8 +531,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
goto error_truncated;
if (package_header->header_len * 4 != package_size) {
- DRM_ERROR("DMC firmware has wrong package header length "
- "(%u bytes)\n", package_size);
+ drm_err(&i915->drm, "DMC firmware has wrong package header length "
+ "(%u bytes)\n", package_size);
return 0;
}
@@ -543,8 +545,8 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
package_header->header_ver);
if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
- DRM_ERROR("DMC firmware not supported for %c stepping\n",
- si->stepping);
+ drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
+ si->stepping);
return 0;
}
@@ -552,7 +554,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
return package_size + dmc_offset * 4;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
@@ -561,22 +563,24 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+
if (rem_size < sizeof(struct intel_css_header)) {
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
if (sizeof(struct intel_css_header) !=
(css_header->header_len * 4)) {
- DRM_ERROR("DMC firmware has wrong CSS header length "
- "(%u bytes)\n",
- (css_header->header_len * 4));
+ drm_err(&i915->drm, "DMC firmware has wrong CSS header length "
+ "(%u bytes)\n",
+ (css_header->header_len * 4));
return 0;
}
if (dmc->required_version &&
css_header->version != dmc->required_version) {
- DRM_INFO("Refusing to load DMC firmware v%u.%u,"
+ drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u,"
" please use v%u.%u\n",
DMC_VERSION_MAJOR(css_header->version),
DMC_VERSION_MINOR(css_header->version),
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/dmc: Add intel_dmc_has_payload() helper
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h Anusha Srivatsa
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
v2: rebased.
v3: Move intel_dmc to intel_dmc.h in another patch (Lucas)
v4: Remove headers not needed from intel_dmc.h
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
.../gpu/drm/i915/display/intel_display_power.c | 16 ++++++++--------
drivers/gpu/drm/i915/display/intel_dmc.c | 13 +++++++++----
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
5 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 94e5cbd86e77..88bb05d5c483 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -542,10 +542,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(dmc->dmc_payload));
+ seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
- if (!dmc->dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
goto out;
seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 991ceea06a07..b546672c9b00 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1220,7 +1220,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->dmc.dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
return;
switch (dev_priv->dmc.target_dc_state) {
@@ -5579,7 +5579,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5646,7 +5646,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5712,7 +5712,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
}
@@ -5869,7 +5869,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->dmc.dmc_payload)
+ if (resume && intel_dmc_has_payload(dev_priv))
intel_dmc_load_program(dev_priv);
/* Wa_14011508470 */
@@ -6230,7 +6230,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->dmc.dmc_payload) {
+ intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -6420,7 +6420,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->dmc.dmc_payload) {
+ if (intel_dmc_has_payload(i915)) {
if (i915->dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
@@ -6431,7 +6431,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->dmc.dmc_payload &&
+ if (intel_dmc_has_payload(i915) &&
(i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5887453ff302..f9a0f194f9cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -237,6 +237,11 @@ struct stepping_info {
char substepping;
};
+bool intel_dmc_has_payload(struct drm_i915_private *i915)
+{
+ return i915->dmc.dmc_payload;
+}
+
static const struct stepping_info skl_stepping_info[] = {
{'A', '0'}, {'B', '0'}, {'C', '0'},
{'D', '0'}, {'E', '0'}, {'F', '0'},
@@ -320,7 +325,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->dmc.dmc_payload) {
+ if (!intel_dmc_has_payload(dev_priv)) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
@@ -656,7 +661,7 @@ static void dmc_load_work_fn(struct work_struct *work)
request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
parse_dmc_fw(dev_priv, fw);
- if (dev_priv->dmc.dmc_payload) {
+ if (intel_dmc_has_payload(dev_priv)) {
intel_dmc_load_program(dev_priv);
intel_dmc_runtime_pm_put(dev_priv);
@@ -785,7 +790,7 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
flush_work(&dev_priv->dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
- if (!dev_priv->dmc.dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
intel_dmc_runtime_pm_put(dev_priv);
}
@@ -805,7 +810,7 @@ void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv)
* Reacquire the reference to keep RPM disabled in case DMC isn't
* loaded.
*/
- if (!dev_priv->dmc.dmc_payload)
+ if (!intel_dmc_has_payload(dev_priv))
intel_dmc_runtime_pm_get(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 57dd99da0ced..64816f4a71b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -17,5 +17,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
+bool intel_dmc_has_payload(struct drm_i915_private *i915);
#endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8b964e355cb5..833d3e8b7631 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -792,7 +792,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
struct intel_dmc *dmc = &m->i915->dmc;
err_printf(m, "DMC loaded: %s\n",
- yesno(dmc->dmc_payload));
+ yesno(intel_dmc_has_payload(m->i915) != 0));
err_printf(m, "DMC fw version: %d.%d\n",
DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 2/7] drm/i915/dmc: Add intel_dmc_has_payload() helper Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 21:49 ` Souza, Jose
2021-05-24 19:30 ` [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
` (6 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
Move struct intel_dmc from i915_drv.h to intel_dmc.h.
v2: Add includes along with moving the struct.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.h | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 18 +-----------------
2 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 64816f4a71b6..4c22f567b61b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -6,12 +6,33 @@
#ifndef __INTEL_DMC_H__
#define __INTEL_DMC_H__
+#include "i915_reg.h"
+#include "intel_wakeref.h"
+#include <linux/workqueue.h>
+
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
+struct intel_dmc {
+ struct work_struct work;
+ const char *fw_path;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dc_state;
+ u32 target_dc_state;
+ u32 allowed_dc_mask;
+ intel_wakeref_t wakeref;
+};
+
void intel_dmc_ucode_init(struct drm_i915_private *i915);
void intel_dmc_load_program(struct drm_i915_private *i915);
void intel_dmc_ucode_fini(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9cb02618ba15..b5962768a1f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -67,6 +67,7 @@
#include "display/intel_bios.h"
#include "display/intel_display.h"
#include "display/intel_display_power.h"
+#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_dmc {
- struct work_struct work;
- const char *fw_path;
- u32 required_version;
- u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
- u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
- u32 dc_state;
- u32 target_dc_state;
- u32 allowed_dc_mask;
- intel_wakeref_t wakeref;
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (2 preceding siblings ...)
2021-05-24 19:30 ` [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 21:58 ` Souza, Jose
2021-05-24 19:30 ` [Intel-gfx] [PATCH 5/7] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
` (5 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++++++++++-------------
drivers/gpu/drm/i915/display/intel_dmc.h | 20 ++++++++---
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index f9a0f194f9cf..16bfbca6c1ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
bool intel_dmc_has_payload(struct drm_i915_private *i915)
{
- return i915->dmc.dmc_payload;
+ return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->dmc.dmc_payload;
+ struct intel_dmc *dmc = &dev_priv->dmc;
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!intel_dmc_has_payload(dev_priv)) {
+ if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->dmc.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
- dev_priv->dmc.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
size_t rem_size)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
- ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+ BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+ ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
/*
* Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
- mmioaddr[i] > DMC_MMIO_END_RANGE) {
- drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
- dmc->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- dmc->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -485,16 +481,16 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
- dmc->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!dmc->dmc_payload) {
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload) {
drm_err(&i915->drm, "Memory allocation failed for dmc payload\n");
return 0;
}
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(dmc->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -829,5 +825,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
intel_dmc_ucode_suspend(dev_priv);
drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- kfree(dev_priv->dmc.dmc_payload);
+ kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 4c22f567b61b..b747cc9bf6a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -16,17 +16,27 @@ struct drm_i915_private;
#define DMC_VERSION_MAJOR(version) ((version) >> 16)
#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
+enum {
+ DMC_FW_MAIN = 0,
+ DMC_FW_MAX
+};
+
struct intel_dmc {
struct work_struct work;
const char *fw_path;
u32 required_version;
u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
+ struct dmc_fw_info {
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dmc_offset;
+ u32 start_mmioaddr;
+ u32 dmc_fw_size; /*dwords */
+ u32 *payload;
+ } dmc_info[DMC_FW_MAX];
+
u32 dc_state;
u32 target_dc_state;
u32 allowed_dc_mask;
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915/xelpd: Pipe A DMC plugging
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (3 preceding siblings ...)
2021-05-24 19:30 ` [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 6/7] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.
Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c | 5 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 121 ++++++++++--------
drivers/gpu/drm/i915/display/intel_dmc.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 79 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
+ seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
out:
seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(0)));
+ intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
seq_printf(m, "ssp base: 0x%08x\n",
intel_de_read(dev_priv, DMC_SSP_BASE));
seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b546672c9b00..dce7f1d1540f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
{
drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv, DMC_PROGRAM(0)),
- "DMC program storage start is NULL\n");
+ !intel_de_read(dev_priv,
+ DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ "DMC program storage start is NULL\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 16bfbca6c1ed..3b3bb15e6a24 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
struct intel_dmc *dmc = &dev_priv->dmc;
- struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
- u32 i, fw_size;
+ u32 id, i;
if (!HAS_DMC(dev_priv)) {
drm_err(&dev_priv->drm,
@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
return;
}
- fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
- for (i = 0; i < fw_size; i++)
- intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
- dmc_info->payload[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+ intel_uncore_write_fw(&dev_priv->uncore,
+ DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+ dmc->dmc_info[id].payload[i]);
+ }
+ }
preempt_enable();
- for (i = 0; i < dmc_info->mmio_count; i++) {
- intel_de_write(dev_priv, dmc_info->mmioaddr[i],
- dmc_info->mmiodata[i]);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
+ intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
+ dmc->dmc_info[id].mmiodata[i]);
+ }
}
dev_priv->dmc.dc_state = 0;
@@ -353,59 +357,65 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
gen9_set_dc_state_debugmask(dev_priv);
}
+static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
+ const struct stepping_info *si)
+{
+ if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
+ (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping))
+ return true;
+
+ return false;
+}
+
/*
* Search fw_info table for dmc_offset to find firmware binary: num_entries is
* already sanitized.
*/
-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
+static void dmc_set_fw_offset(struct intel_dmc *dmc,
+ const struct intel_fw_info *fw_info,
unsigned int num_entries,
const struct stepping_info *si,
u8 package_ver)
{
- u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
- unsigned int i;
+ unsigned int i, id;
- for (i = 0; i < num_entries; i++) {
- if (package_ver > 1 && fw_info[i].dmc_id != 0)
- continue;
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
- if (fw_info[i].substepping == '*' &&
- si->stepping == fw_info[i].stepping) {
- dmc_offset = fw_info[i].offset;
- break;
+ for (i = 0; i < num_entries; i++) {
+ if (package_ver > 1) {
+ if (fw_info[i].dmc_id >= DMC_FW_MAX || fw_info[i].dmc_id < DMC_FW_MAIN) {
+ drm_notice(&i915->drm, "Invalid firmware id: %d\n", fw_info[i].dmc_id);
+ continue;
+ } else {
+ id = fw_info[i].dmc_id;
+ }
+ } else {
+ id = DMC_FW_MAIN;
}
- if (si->stepping == fw_info[i].stepping &&
- si->substepping == fw_info[i].substepping) {
- dmc_offset = fw_info[i].offset;
- break;
- }
+ /* More specific versions come first, so we don't even have to
+ * check for the stepping since we already found a previous FW
+ * for this id.
+ */
+ if (dmc->dmc_info[id].present)
+ continue;
- if (fw_info[i].stepping == '*' &&
- fw_info[i].substepping == '*') {
- /*
- * In theory we should stop the search as generic
- * entries should always come after the more specific
- * ones, but let's continue to make sure to work even
- * with "broken" firmwares. If we don't find a more
- * specific one, then we use this entry
- */
- dmc_offset = fw_info[i].offset;
+ if (fw_info_matches_stepping(&fw_info[i], si)) {
+ dmc->dmc_info[id].present = true;
+ dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
}
}
-
- return dmc_offset;
}
static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
- size_t rem_size)
+ size_t rem_size, u8 dmc_id)
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
- u32 mmio_count, mmio_count_max;
+ u32 mmio_count, mmio_count_max, start_mmioaddr;
u8 *payload;
BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
@@ -432,6 +442,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
/* header_len is in dwords */
header_len_bytes = dmc_header->header_len * 4;
+ start_mmioaddr = v3->start_mmioaddr;
dmc_header_size = sizeof(*v3);
} else if (dmc_header->header_ver == 1) {
const struct intel_dmc_header_v1 *v1 =
@@ -445,6 +456,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
mmio_count = v1->mmio_count;
mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
header_len_bytes = dmc_header->header_len;
+ start_mmioaddr = 0x80000;
dmc_header_size = sizeof(*v1);
} else {
drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
@@ -469,6 +481,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
dmc_info->mmiodata[i] = mmiodata[i];
}
dmc_info->mmio_count = mmio_count;
+ dmc_info->start_mmioaddr = start_mmioaddr;
rem_size -= header_len_bytes;
@@ -507,7 +520,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
{
struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
u32 package_size = sizeof(struct intel_package_header);
- u32 num_entries, max_entries, dmc_offset;
+ u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
if (rem_size < package_size)
@@ -543,16 +556,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
fw_info = (const struct intel_fw_info *)
((u8 *)package_header + sizeof(*package_header));
- dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
- package_header->header_ver);
- if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
- drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
- si->stepping);
- return 0;
- }
+ dmc_set_fw_offset(dmc, fw_info, num_entries, si,
+ package_header->header_ver);
/* dmc_offset is in dwords */
- return package_size + dmc_offset * 4;
+ return package_size;
error_truncated:
drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -604,7 +612,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_dmc *dmc = &dev_priv->dmc;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
u32 readcount = 0;
- u32 r;
+ u32 r, offset;
+ int id;
if (!fw)
return;
@@ -625,9 +634,19 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
readcount += r;
- /* Extract dmc_header information */
- dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
- parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
+ for (id = 0; id < DMC_FW_MAX; id++) {
+ if (!dev_priv->dmc.dmc_info[id].present)
+ continue;
+
+ offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
+ if (fw->size - offset < 0) {
+ drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
+ continue;
+ }
+
+ dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
+ parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
+ }
}
static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b747cc9bf6a7..007a284b0ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -18,6 +18,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
+ DMC_FW_PIPEA,
DMC_FW_MAX
};
@@ -35,6 +36,7 @@ struct intel_dmc {
u32 start_mmioaddr;
u32 dmc_fw_size; /*dwords */
u32 *payload;
+ bool present;
} dmc_info[DMC_FW_MAX];
u32 dc_state;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4dbe79009c0e..9713108ea78e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7728,7 +7728,7 @@ enum {
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
/* DMC */
-#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
+#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
#define DMC_HTP_ADDR_SKL 0x00500034
#define DMC_SSP_BASE _MMIO(0x8F074)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/adl_p: Pipe B DMC Support
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (4 preceding siblings ...)
2021-05-24 19:30 ` [Intel-gfx] [PATCH 5/7] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 7/7] drm/i915/adl_p: Load DMC Anusha Srivatsa
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "path: %s\n", dmc->fw_path);
seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv)));
+ seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
if (!intel_dmc_has_payload(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
+ DMC_FW_PIPEB,
DMC_FW_MAX
};
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/adl_p: Load DMC
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (5 preceding siblings ...)
2021-05-24 19:30 ` [Intel-gfx] [PATCH 6/7] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
@ 2021-05-24 19:30 ` Anusha Srivatsa
2021-05-24 20:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev2) Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anusha Srivatsa @ 2021-05-24 19:30 UTC (permalink / raw)
To: intel-gfx
Load DMC v2.06 on ADLP. The release notes mention that
this version enables few power savings features.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 3b3bb15e6a24..e1a7426cb7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
#define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
+#define ADLP_DMC_PATH "i915/adlp_dmc_ver2_10.bin"
+#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
#define ADLS_DMC_PATH DMC_PATH(adls, 2, 01)
#define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1)
MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -722,7 +726,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
*/
intel_dmc_runtime_pm_get(dev_priv);
- if (IS_ALDERLAKE_S(dev_priv)) {
+ if (IS_ALDERLAKE_P(dev_priv)) {
+ dmc->fw_path = ADLP_DMC_PATH;
+ dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+ dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+ } else if (IS_ALDERLAKE_S(dev_priv)) {
dmc->fw_path = ADLS_DMC_PATH;
dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev2)
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (6 preceding siblings ...)
2021-05-24 19:30 ` [Intel-gfx] [PATCH 7/7] drm/i915/adl_p: Load DMC Anusha Srivatsa
@ 2021-05-24 20:10 ` Patchwork
2021-05-24 20:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-24 20:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-05-24 20:10 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Pipe DMC Support (rev2)
URL : https://patchwork.freedesktop.org/series/90445/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e45725e49bdd drm/i915/dmc: s/DRM_ERROR/drm_err
-:80: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#80: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:487:
if (!dmc->dmc_payload) {
+ drm_err(&i915->drm, "Memory allocation failed for dmc payload\n");
total: 0 errors, 1 warnings, 0 checks, 140 lines checked
7cd57a2ac1a8 drm/i915/dmc: Add intel_dmc_has_payload() helper
b8888f455925 drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
75f070edde6f drm/i915/dmc: Introduce DMC_FW_MAIN
11185b96af31 drm/i915/xelpd: Pipe A DMC plugging
-:39: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:587:
+ intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
-:54: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:965:
+ DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
-:147: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:387:
+ drm_notice(&i915->drm, "Invalid firmware id: %d\n", fw_info[i].dmc_id);
total: 0 errors, 3 warnings, 0 checks, 263 lines checked
f7ecd81b636d drm/i915/adl_p: Pipe B DMC Support
09bd925cfaf4 drm/i915/adl_p: Load DMC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Pipe DMC Support (rev2)
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (7 preceding siblings ...)
2021-05-24 20:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev2) Patchwork
@ 2021-05-24 20:11 ` Patchwork
2021-05-24 20:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-05-24 20:11 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Pipe DMC Support (rev2)
URL : https://patchwork.freedesktop.org/series/90445/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Pipe DMC Support (rev2)
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
` (8 preceding siblings ...)
2021-05-24 20:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-24 20:33 ` Patchwork
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-05-24 20:33 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 9912 bytes --]
== Series Details ==
Series: Pipe DMC Support (rev2)
URL : https://patchwork.freedesktop.org/series/90445/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10127 -> Patchwork_20182
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20182 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20182, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20182:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [PASS][1] -> [DMESG-WARN][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6600u: [PASS][3] -> [DMESG-WARN][4] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6600u/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-tgl-dsi}: [FAIL][5] ([i915#1436] / [i915#2932] / [i915#2966]) -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-tgl-dsi/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-tgl-dsi/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20182 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#109315]) +17 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-hsw-4770: NOTRUN -> [WARN][9] ([i915#2283])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-hsw-4770: NOTRUN -> [SKIP][10] ([fdo#109271]) +4 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3012])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6600u: [PASS][12] -> [SKIP][13] ([fdo#109271]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6600u/igt@i915_pm_rpm@module-reload.html
- fi-skl-6700k2: [PASS][14] -> [SKIP][15] ([fdo#109271]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-4770: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1072]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-hsw-4770: [INCOMPLETE][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-hsw-4770/igt@gem_exec_suspend@basic-s0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-hsw-4770/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][21] ([i915#2782]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [DMESG-FAIL][23] ([i915#3462]) -> [INCOMPLETE][24] ([i915#2782] / [i915#2940] / [i915#3462])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-kbl-x1275: [FAIL][25] ([i915#1436] / [i915#3363]) -> [FAIL][26] ([i915#1436] / [i915#2426] / [i915#3363])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-kbl-x1275/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-kbl-x1275/igt@runner@aborted.html
- fi-cfl-8700k: [FAIL][27] ([i915#3363]) -> [FAIL][28] ([i915#2426] / [i915#3363])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-8700k/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-cfl-8700k/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][29] ([i915#3363] / [k.org#202321]) -> [FAIL][30] ([i915#2426] / [i915#3363] / [k.org#202321])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-glk-dsi/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-glk-dsi/igt@runner@aborted.html
- fi-cml-u2: [FAIL][31] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) -> [FAIL][32] ([i915#3363] / [i915#3462])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cml-u2/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-cml-u2/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][33] ([i915#2426] / [i915#3363]) -> [FAIL][34] ([i915#3363])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10127/fi-cfl-guc/igt@runner@aborted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/fi-cfl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (41 -> 34)
------------------------------
Missing (7): fi-kbl-soraka fi-rkl-11500t fi-bsw-cyan fi-apl-guc fi-ivb-3770 fi-cml-drallion fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10127 -> Patchwork_20182
CI-20190529: 20190529
CI_DRM_10127: d6d3a2a996af7a82e567e96a19410ac9d7246794 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6092: d87087c321da07035d4f96d98c34e451b3ccb809 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20182: 09bd925cfaf4f6b57972054cce6c1f4e3743d32a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
09bd925cfaf4 drm/i915/adl_p: Load DMC
f7ecd81b636d drm/i915/adl_p: Pipe B DMC Support
11185b96af31 drm/i915/xelpd: Pipe A DMC plugging
75f070edde6f drm/i915/dmc: Introduce DMC_FW_MAIN
b8888f455925 drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
7cd57a2ac1a8 drm/i915/dmc: Add intel_dmc_has_payload() helper
e45725e49bdd drm/i915/dmc: s/DRM_ERROR/drm_err
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20182/index.html
[-- Attachment #1.2: Type: text/html, Size: 12878 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h
2021-05-24 19:30 ` [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h Anusha Srivatsa
@ 2021-05-24 21:49 ` Souza, Jose
0 siblings, 0 replies; 14+ messages in thread
From: Souza, Jose @ 2021-05-24 21:49 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx
On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> Move struct intel_dmc from i915_drv.h to intel_dmc.h.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> v2: Add includes along with moving the struct.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.h | 21 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 18 +-----------------
> 2 files changed, 22 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 64816f4a71b6..4c22f567b61b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -6,12 +6,33 @@
> #ifndef __INTEL_DMC_H__
> #define __INTEL_DMC_H__
>
> +#include "i915_reg.h"
> +#include "intel_wakeref.h"
> +#include <linux/workqueue.h>
> +
> struct drm_i915_private;
>
> #define DMC_VERSION(major, minor) ((major) << 16 | (minor))
> #define DMC_VERSION_MAJOR(version) ((version) >> 16)
> #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
>
> +struct intel_dmc {
> + struct work_struct work;
> + const char *fw_path;
> + u32 required_version;
> + u32 max_fw_size; /* bytes */
> + u32 *dmc_payload;
> + u32 dmc_fw_size; /* dwords */
> + u32 version;
> + u32 mmio_count;
> + i915_reg_t mmioaddr[20];
> + u32 mmiodata[20];
> + u32 dc_state;
> + u32 target_dc_state;
> + u32 allowed_dc_mask;
> + intel_wakeref_t wakeref;
> +};
> +
> void intel_dmc_ucode_init(struct drm_i915_private *i915);
> void intel_dmc_load_program(struct drm_i915_private *i915);
> void intel_dmc_ucode_fini(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9cb02618ba15..b5962768a1f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -67,6 +67,7 @@
> #include "display/intel_bios.h"
> #include "display/intel_display.h"
> #include "display/intel_display_power.h"
> +#include "display/intel_dmc.h"
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> #include "display/intel_frontbuffer.h"
> @@ -328,23 +329,6 @@ struct drm_i915_display_funcs {
> void (*read_luts)(struct intel_crtc_state *crtc_state);
> };
>
> -struct intel_dmc {
> - struct work_struct work;
> - const char *fw_path;
> - u32 required_version;
> - u32 max_fw_size; /* bytes */
> - u32 *dmc_payload;
> - u32 dmc_fw_size; /* dwords */
> - u32 version;
> - u32 mmio_count;
> - i915_reg_t mmioaddr[20];
> - u32 mmiodata[20];
> - u32 dc_state;
> - u32 target_dc_state;
> - u32 allowed_dc_mask;
> - intel_wakeref_t wakeref;
> -};
> -
> enum i915_cache_level {
> I915_CACHE_NONE = 0,
> I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
2021-05-24 19:30 ` [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
@ 2021-05-24 21:58 ` Souza, Jose
2021-05-26 16:17 ` Srivatsa, Anusha
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2021-05-24 21:58 UTC (permalink / raw)
To: Srivatsa, Anusha, intel-gfx
On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> This is a prep patch for Pipe DMC plugging.
>
> Add dmc_info struct in intel_dmc to have all common fields
> shared between all DMC's in the package.
> Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++++++++++-------------
> drivers/gpu/drm/i915/display/intel_dmc.h | 20 ++++++++---
> 2 files changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f9a0f194f9cf..16bfbca6c1ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -239,7 +239,7 @@ struct stepping_info {
>
> bool intel_dmc_has_payload(struct drm_i915_private *i915)
> {
> - return i915->dmc.dmc_payload;
> + return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> }
>
> static const struct stepping_info skl_stepping_info[] = {
> @@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> */
> void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
> - u32 *payload = dev_priv->dmc.dmc_payload;
> + struct intel_dmc *dmc = &dev_priv->dmc;
> + struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
> u32 i, fw_size;
>
> if (!HAS_DMC(dev_priv)) {
> @@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> return;
> }
>
> - if (!intel_dmc_has_payload(dev_priv)) {
> + if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
> drm_err(&dev_priv->drm,
> "Tried to program CSR with empty payload\n");
> return;
> }
>
> - fw_size = dev_priv->dmc.dmc_fw_size;
> + fw_size = dmc_info->dmc_fw_size;
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> preempt_disable();
>
> for (i = 0; i < fw_size; i++)
> intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
> - payload[i]);
> + dmc_info->payload[i]);
>
> preempt_enable();
>
> - for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
> - intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
> - dev_priv->dmc.mmiodata[i]);
> + for (i = 0; i < dmc_info->mmio_count; i++) {
> + intel_de_write(dev_priv, dmc_info->mmioaddr[i],
> + dmc_info->mmiodata[i]);
> }
>
> dev_priv->dmc.dc_state = 0;
> @@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> size_t rem_size)
> {
> struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
> + struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
> unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> const u32 *mmioaddr, *mmiodata;
> u32 mmio_count, mmio_count_max;
> u8 *payload;
>
> - BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
> - ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
> + BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
> + ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>
> /*
> * Check if we can access common fields, we will checkc again below
> @@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> }
>
> for (i = 0; i < mmio_count; i++) {
> - if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
> - mmioaddr[i] > DMC_MMIO_END_RANGE) {
> - drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
> - mmioaddr[i]);
> - return 0;
> - }
Why the checks above were dropped?
> - dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
> - dmc->mmiodata[i] = mmiodata[i];
> + dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
> + dmc_info->mmiodata[i] = mmiodata[i];
> }
> - dmc->mmio_count = mmio_count;
> + dmc_info->mmio_count = mmio_count;
>
> rem_size -= header_len_bytes;
>
> @@ -485,16 +481,16 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
> return 0;
> }
> - dmc->dmc_fw_size = dmc_header->fw_size;
> + dmc_info->dmc_fw_size = dmc_header->fw_size;
Did not read the next patches but the if possible would be better to rename dmc_info to dmc_main_info or dmc_pipe_info when possible.
>
> - dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
> - if (!dmc->dmc_payload) {
> + dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
> + if (!dmc_info->payload) {
> drm_err(&i915->drm, "Memory allocation failed for dmc payload\n");
> return 0;
> }
>
> payload = (u8 *)(dmc_header) + header_len_bytes;
> - memcpy(dmc->dmc_payload, payload, payload_size);
> + memcpy(dmc_info->payload, payload, payload_size);
>
> return header_len_bytes + payload_size;
>
> @@ -829,5 +825,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
> intel_dmc_ucode_suspend(dev_priv);
> drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
>
> - kfree(dev_priv->dmc.dmc_payload);
> + kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 4c22f567b61b..b747cc9bf6a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -16,17 +16,27 @@ struct drm_i915_private;
> #define DMC_VERSION_MAJOR(version) ((version) >> 16)
> #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
>
> +enum {
> + DMC_FW_MAIN = 0,
> + DMC_FW_MAX
> +};
> +
> struct intel_dmc {
> struct work_struct work;
> const char *fw_path;
> u32 required_version;
> u32 max_fw_size; /* bytes */
> - u32 *dmc_payload;
> - u32 dmc_fw_size; /* dwords */
> u32 version;
> - u32 mmio_count;
> - i915_reg_t mmioaddr[20];
> - u32 mmiodata[20];
> + struct dmc_fw_info {
> + u32 mmio_count;
> + i915_reg_t mmioaddr[20];
> + u32 mmiodata[20];
> + u32 dmc_offset;
> + u32 start_mmioaddr;
dmc_offset and start_mmioaddr are added but not used here. I guess it will in the next patches so please add it only when used.
> + u32 dmc_fw_size; /*dwords */
> + u32 *payload;
> + } dmc_info[DMC_FW_MAX];
> +
> u32 dc_state;
> u32 target_dc_state;
> u32 allowed_dc_mask;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN
2021-05-24 21:58 ` Souza, Jose
@ 2021-05-26 16:17 ` Srivatsa, Anusha
0 siblings, 0 replies; 14+ messages in thread
From: Srivatsa, Anusha @ 2021-05-26 16:17 UTC (permalink / raw)
To: Souza, Jose, intel-gfx
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Monday, May 24, 2021 2:59 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce
> DMC_FW_MAIN
>
> On Mon, 2021-05-24 at 12:30 -0700, Anusha Srivatsa wrote:
> > This is a prep patch for Pipe DMC plugging.
> >
> > Add dmc_info struct in intel_dmc to have all common fields shared
> > between all DMC's in the package.
> > Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
> >
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc.c | 44
> > +++++++++++------------- drivers/gpu/drm/i915/display/intel_dmc.h |
> > 20 ++++++++---
> > 2 files changed, 35 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index f9a0f194f9cf..16bfbca6c1ed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -239,7 +239,7 @@ struct stepping_info {
> >
> > bool intel_dmc_has_payload(struct drm_i915_private *i915) {
> > - return i915->dmc.dmc_payload;
> > + return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> > }
> >
> > static const struct stepping_info skl_stepping_info[] = { @@ -316,7
> > +316,8 @@ static void gen9_set_dc_state_debugmask(struct
> drm_i915_private *dev_priv)
> > */
> > void intel_dmc_load_program(struct drm_i915_private *dev_priv) {
> > - u32 *payload = dev_priv->dmc.dmc_payload;
> > + struct intel_dmc *dmc = &dev_priv->dmc;
> > + struct dmc_fw_info *dmc_info = &dmc-
> >dmc_info[DMC_FW_MAIN];
> > u32 i, fw_size;
> >
> > if (!HAS_DMC(dev_priv)) {
> > @@ -325,26 +326,26 @@ void intel_dmc_load_program(struct
> drm_i915_private *dev_priv)
> > return;
> > }
> >
> > - if (!intel_dmc_has_payload(dev_priv)) {
> > + if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
> > drm_err(&dev_priv->drm,
> > "Tried to program CSR with empty payload\n");
> > return;
> > }
> >
> > - fw_size = dev_priv->dmc.dmc_fw_size;
> > + fw_size = dmc_info->dmc_fw_size;
> > assert_rpm_wakelock_held(&dev_priv->runtime_pm);
> >
> > preempt_disable();
> >
> > for (i = 0; i < fw_size; i++)
> > intel_uncore_write_fw(&dev_priv->uncore,
> DMC_PROGRAM(i),
> > - payload[i]);
> > + dmc_info->payload[i]);
> >
> > preempt_enable();
> >
> > - for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
> > - intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
> > - dev_priv->dmc.mmiodata[i]);
> > + for (i = 0; i < dmc_info->mmio_count; i++) {
> > + intel_de_write(dev_priv, dmc_info->mmioaddr[i],
> > + dmc_info->mmiodata[i]);
> > }
> >
> > dev_priv->dmc.dc_state = 0;
> > @@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct
> intel_dmc *dmc,
> > size_t rem_size)
> > {
> > struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
> > dmc);
> > + struct dmc_fw_info *dmc_info = &dmc-
> >dmc_info[DMC_FW_MAIN];
> > unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> > const u32 *mmioaddr, *mmiodata;
> > u32 mmio_count, mmio_count_max;
> > u8 *payload;
> >
> > - BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) <
> DMC_V3_MAX_MMIO_COUNT ||
> > - ARRAY_SIZE(dmc->mmioaddr) <
> DMC_V1_MAX_MMIO_COUNT);
> > + BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) <
> DMC_V3_MAX_MMIO_COUNT ||
> > + ARRAY_SIZE(dmc_info->mmioaddr) <
> DMC_V1_MAX_MMIO_COUNT);
> >
> > /*
> > * Check if we can access common fields, we will checkc again below
> > @@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct
> intel_dmc *dmc,
> > }
> >
> > for (i = 0; i < mmio_count; i++) {
> > - if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
> > - mmioaddr[i] > DMC_MMIO_END_RANGE) {
> > - drm_err(&i915->drm, "DMC firmware has wrong
> mmio address 0x%x\n",
> > - mmioaddr[i]);
> > - return 0;
> > - }
>
> Why the checks above were dropped?
The DMC_MMIO_START_RANGE And DMC_MMIO_END_RANGE were hardcoded values. But starting from gen12, they can be different for different platforms. The best way to grab them is from the blob itself. The above check does not make sense in that scenario.
> > - dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
> > - dmc->mmiodata[i] = mmiodata[i];
> > + dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
> > + dmc_info->mmiodata[i] = mmiodata[i];
> > }
> > - dmc->mmio_count = mmio_count;
> > + dmc_info->mmio_count = mmio_count;
> >
> > rem_size -= header_len_bytes;
> >
> > @@ -485,16 +481,16 @@ static u32 parse_dmc_fw_header(struct
> intel_dmc *dmc,
> > drm_err(&i915->drm, "DMC FW too big (%u bytes)\n",
> payload_size);
> > return 0;
> > }
> > - dmc->dmc_fw_size = dmc_header->fw_size;
> > + dmc_info->dmc_fw_size = dmc_header->fw_size;
>
> Did not read the next patches but the if possible would be better to rename
> dmc_info to dmc_main_info or dmc_pipe_info when possible.
dmc_info here will be referring to both main_dmc and pipe_dmc and hence named generic. The patches after this patch make more sense in that aspect.
> >
> > - dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
> > - if (!dmc->dmc_payload) {
> > + dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
> > + if (!dmc_info->payload) {
> > drm_err(&i915->drm, "Memory allocation failed for dmc
> payload\n");
> > return 0;
> > }
> >
> > payload = (u8 *)(dmc_header) + header_len_bytes;
> > - memcpy(dmc->dmc_payload, payload, payload_size);
> > + memcpy(dmc_info->payload, payload, payload_size);
> >
> > return header_len_bytes + payload_size;
> >
> > @@ -829,5 +825,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private
> *dev_priv)
> > intel_dmc_ucode_suspend(dev_priv);
> > drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
> >
> > - kfree(dev_priv->dmc.dmc_payload);
> > + kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> > b/drivers/gpu/drm/i915/display/intel_dmc.h
> > index 4c22f567b61b..b747cc9bf6a7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > @@ -16,17 +16,27 @@ struct drm_i915_private;
> > #define DMC_VERSION_MAJOR(version) ((version) >> 16)
> > #define DMC_VERSION_MINOR(version) ((version) & 0xffff)
> >
> > +enum {
> > + DMC_FW_MAIN = 0,
> > + DMC_FW_MAX
> > +};
> > +
> > struct intel_dmc {
> > struct work_struct work;
> > const char *fw_path;
> > u32 required_version;
> > u32 max_fw_size; /* bytes */
> > - u32 *dmc_payload;
> > - u32 dmc_fw_size; /* dwords */
> > u32 version;
> > - u32 mmio_count;
> > - i915_reg_t mmioaddr[20];
> > - u32 mmiodata[20];
> > + struct dmc_fw_info {
> > + u32 mmio_count;
> > + i915_reg_t mmioaddr[20];
> > + u32 mmiodata[20];
> > + u32 dmc_offset;
> > + u32 start_mmioaddr;
>
> dmc_offset and start_mmioaddr are added but not used here. I guess it will
> in the next patches so please add it only when used.
Sure. Checking this again and make the change.
Thanks for the feedback.
Anusha
> > + u32 dmc_fw_size; /*dwords */
> > + u32 *payload;
> > + } dmc_info[DMC_FW_MAX];
> > +
> > u32 dc_state;
> > u32 target_dc_state;
> > u32 allowed_dc_mask;
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-05-26 16:17 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-24 19:30 [Intel-gfx] [PATCH 0/7] Pipe DMC Support Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 1/7] drm/i915/dmc: s/DRM_ERROR/drm_err Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 2/7] drm/i915/dmc: Add intel_dmc_has_payload() helper Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 3/7] drm/i915/dmc: Move struct intel_dmc to intel_dmc.h Anusha Srivatsa
2021-05-24 21:49 ` Souza, Jose
2021-05-24 19:30 ` [Intel-gfx] [PATCH 4/7] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
2021-05-24 21:58 ` Souza, Jose
2021-05-26 16:17 ` Srivatsa, Anusha
2021-05-24 19:30 ` [Intel-gfx] [PATCH 5/7] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 6/7] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
2021-05-24 19:30 ` [Intel-gfx] [PATCH 7/7] drm/i915/adl_p: Load DMC Anusha Srivatsa
2021-05-24 20:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev2) Patchwork
2021-05-24 20:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-24 20:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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