[igt-dev] [PATCH v3 i-g-t 0/2] Keep tests working without relocations

[igt-dev] [PATCH v3 i-g-t 0/2] Keep tests working without relocations

[Andrzej Turko]

With relocations disabled for newer generations
the addresses of buffer objects in memory need
to be known in advance and, hence, assigned in
userspace.
If relocations are not supported, the tests now
use the intel allocator to find offsets and
update the contents of batches correspondingly.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Andrzej Turko (2):
  tests/i915/gem_exec_gttfill: Support gens without relocations
  tests/i915/gem_exec_store: Support gens without relocations

 tests/i915/gem_exec_gttfill.c |  75 +++++++++++--
 tests/i915/gem_exec_store.c   | 194 +++++++++++++++++++++++++---------
 2 files changed, 209 insertions(+), 60 deletions(-)

-- 
2.25.1

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[igt-dev] [PATCH i-g-t 1/2] tests/i915/gem_exec_gttfill: Support gens without relocations

[Andrzej Turko]

With relocations disabled for newer generations
addresses of objects need to be assigned by the test.
As all the objects won't fit in the gtt, using the allocator
does not guarantee that submitted batches won't overlap.
It only reduces the number of overlapping objects while ensuring
that evictions happen at different offsets.

Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_exec_gttfill.c | 75 ++++++++++++++++++++++++++++++-----
 1 file changed, 64 insertions(+), 11 deletions(-)

diff --git a/tests/i915/gem_exec_gttfill.c b/tests/i915/gem_exec_gttfill.c
index c0e27c9bb..091c74ebb 100644
--- a/tests/i915/gem_exec_gttfill.c
+++ b/tests/i915/gem_exec_gttfill.c
@@ -28,6 +28,8 @@
 IGT_TEST_DESCRIPTION("Fill the GTT with batches.");
 
 #define BATCH_SIZE (4096<<10)
+/* We don't have alignment detection yet, so assume the worst-case scenario. */
+#define BATCH_ALIGNMENT (1 << 21)
 
 struct batch {
 	uint32_t handle;
@@ -47,15 +49,21 @@ static void xchg_batch(void *array, unsigned int i, unsigned int j)
 static void submit(int fd, int gen,
 		   struct drm_i915_gem_execbuffer2 *eb,
 		   struct drm_i915_gem_relocation_entry *reloc,
-		   struct batch *batches, unsigned int count)
+		   struct batch *batches, unsigned int count,
+		   uint64_t ahnd, bool do_relocs)
 {
 	struct drm_i915_gem_exec_object2 obj;
 	uint32_t batch[16];
-	unsigned n;
+	uint64_t address, value;
+	unsigned n, j;
 
 	memset(&obj, 0, sizeof(obj));
-	obj.relocs_ptr = to_user_pointer(reloc);
-	obj.relocation_count = 2;
+	if (do_relocs) {
+		obj.relocs_ptr = to_user_pointer(reloc);
+		obj.relocation_count = 2;
+	} else {
+		obj.flags |= EXEC_OBJECT_PINNED;
+	}
 
 	memset(reloc, 0, 2*sizeof(*reloc));
 	reloc[0].offset = eb->batch_start_offset;
@@ -85,16 +93,40 @@ static void submit(int fd, int gen,
 	batch[++n] = 0; /* lower_32_bits(value) */
 	batch[++n] = 0; /* upper_32_bits(value) / nop */
 	batch[++n] = MI_BATCH_BUFFER_END;
-
 	eb->buffers_ptr = to_user_pointer(&obj);
+	j = 0;
 	for (unsigned i = 0; i < count; i++) {
 		obj.handle = batches[i].handle;
 		reloc[0].target_handle = obj.handle;
 		reloc[1].target_handle = obj.handle;
 
-		obj.offset = 0;
-		reloc[0].presumed_offset = obj.offset;
-		reloc[1].presumed_offset = obj.offset;
+		if (do_relocs) {
+			obj.offset = 0;
+		} else {
+			obj.offset = __intel_allocator_alloc(ahnd, obj.handle,
+							     BATCH_SIZE,
+							     BATCH_ALIGNMENT,
+							     ALLOC_STRATEGY_HIGH_TO_LOW);
+			for (; obj.offset == -1; j = ((++j) == count ? 0 : j)) {
+				if (i != j)
+					intel_allocator_free(ahnd, batches[j].handle);
+				obj.offset = __intel_allocator_alloc(ahnd, obj.handle,
+								     BATCH_SIZE,
+								     BATCH_ALIGNMENT,
+								     ALLOC_STRATEGY_HIGH_TO_LOW);
+			}
+
+			/* If there is no relocation support, we assume gen >= 8. */
+			reloc[0].presumed_offset = obj.offset;
+			address = obj.offset + reloc[0].delta;
+			batch[1] = address;
+			batch[2] = address >> 32;
+
+			reloc[1].presumed_offset = obj.offset;
+			value = obj.offset + reloc[1].delta;
+			batch[3] = value;
+			batch[4] = value >> 32;
+		}
 
 		memcpy(batches[i].ptr + eb->batch_start_offset,
 		       batch, sizeof(batch));
@@ -116,7 +148,8 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	struct batch *batches;
 	unsigned nengine;
 	unsigned count;
-	uint64_t size;
+	uint64_t size, ahnd;
+	bool do_relocs = gem_has_relocations(fd);
 
 	shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 	igt_assert(shared != MAP_FAILED);
@@ -138,6 +171,8 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	igt_assert(nengine * 64 <= BATCH_SIZE);
 
 	size = gem_aperture_size(fd);
+	if (!gem_uses_full_ppgtt(fd))
+		size /= 2;
 	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
 		size = 1ull << 32;
 	igt_require(size < (1ull<<32) * BATCH_SIZE);
@@ -145,6 +180,12 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	count = size / BATCH_SIZE + 1;
 	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
 		  count, (long long)size, nengine);
+
+	intel_allocator_multiprocess_start();
+	/* Avoid allocating on the last page */
+	ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096,
+					 INTEL_ALLOCATOR_SIMPLE,
+					 ALLOC_STRATEGY_HIGH_TO_LOW);
 	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
 	intel_detect_and_clear_missed_interrupts(fd);
 
@@ -165,7 +206,7 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 	}
 
 	/* Flush all memory before we start the timer */
-	submit(fd, gen, &execbuf, reloc, batches, count);
+	submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs);
 
 	igt_info("Setup %u batches in %.2fms\n",
 		 count, 1e-6 * igt_nsec_elapsed(&tv));
@@ -176,8 +217,14 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 		igt_permute_array(batches, count, xchg_batch);
 		execbuf.batch_start_offset = child*64;
 		execbuf.flags |= engines[child];
+
+		/* We need to open the allocator again in the new process */
+		ahnd = intel_allocator_open_full(fd, 0, 0, size - 4096,
+						 INTEL_ALLOCATOR_SIMPLE,
+						 ALLOC_STRATEGY_HIGH_TO_LOW);
+
 		igt_until_timeout(timeout) {
-			submit(fd, gen, &execbuf, reloc, batches, count);
+			submit(fd, gen, &execbuf, reloc, batches, count, ahnd, do_relocs);
 			for (unsigned i = 0; i < count; i++) {
 				uint64_t offset, delta;
 
@@ -189,13 +236,18 @@ static void fillgtt(int fd, unsigned ring, int timeout)
 		}
 		shared[child] = cycles;
 		igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles);
+		intel_allocator_close(ahnd);
 	}
 	igt_waitchildren();
 
+	intel_allocator_close(ahnd);
+	intel_allocator_multiprocess_stop();
+
 	for (unsigned i = 0; i < count; i++) {
 		munmap(batches[i].ptr, BATCH_SIZE);
 		gem_close(fd, batches[i].handle);
 	}
+	free(batches);
 
 	shared[nengine] = 0;
 	for (unsigned i = 0; i < nengine; i++)
@@ -216,6 +268,7 @@ igt_main
 		igt_fork_hang_detector(i915);
 	}
 
+
 	igt_subtest("basic") /* just enough to run a single pass */
 		fillgtt(i915, ALL_ENGINES, 1);
 
-- 
2.25.1

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[igt-dev] [PATCH i-g-t 2/2] tests/i915/gem_exec_store: Support gens without relocations

[Andrzej Turko]

With relocations disabled on newer generations
tests must assign addresses to objects by
themselves instead of relying on the driver.

Signed-off-by: Andrzej Turko <andrzej.turko@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_exec_store.c | 194 +++++++++++++++++++++++++++---------
 1 file changed, 145 insertions(+), 49 deletions(-)

diff --git a/tests/i915/gem_exec_store.c b/tests/i915/gem_exec_store.c
index 771ee1690..677cf8b9f 100644
--- a/tests/i915/gem_exec_store.c
+++ b/tests/i915/gem_exec_store.c
@@ -36,6 +36,9 @@
 
 #define ENGINE_MASK  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
 
+/* Without alignment detection we assume the worst-case scenario. */
+#define ALIGNMENT (1 << 21)
+
 static void store_dword(int fd, const struct intel_execution_engine2 *e)
 {
 	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
@@ -43,7 +46,9 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e)
 	struct drm_i915_gem_relocation_entry reloc;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	uint32_t batch[16];
+	uint64_t ahnd;
 	int i;
+	bool do_relocs = gem_has_relocations(fd);
 
 	intel_detect_and_clear_missed_interrupts(fd);
 	memset(&execbuf, 0, sizeof(execbuf));
@@ -53,43 +58,64 @@ static void store_dword(int fd, const struct intel_execution_engine2 *e)
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, 4096);
 	obj[1].handle = gem_create(fd, 4096);
 
-	memset(&reloc, 0, sizeof(reloc));
-	reloc.target_handle = obj[0].handle;
-	reloc.presumed_offset = 0;
-	reloc.offset = sizeof(uint32_t);
-	reloc.delta = 0;
-	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	obj[1].relocs_ptr = to_user_pointer(&reloc);
-	obj[1].relocation_count = 1;
+	if (do_relocs) {
+		memset(&reloc, 0, sizeof(reloc));
+		reloc.target_handle = obj[0].handle;
+		reloc.presumed_offset = obj[0].offset;
+		reloc.offset = sizeof(uint32_t);
+		reloc.delta = 0;
+		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+		obj[1].relocs_ptr = to_user_pointer(&reloc);
+		obj[1].relocation_count = 1;
+	} else {
+		obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
+						      4096, ALIGNMENT);
+		obj[0].offset = CANONICAL(obj[0].offset);
+		obj[0].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+				EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+
+		obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
+						      4096, ALIGNMENT);
+		obj[1].offset = CANONICAL(obj[1].offset);
+		obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+				EXEC_OBJECT_PINNED;
+	}
 
 	i = 0;
 	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 	if (gen >= 8) {
-		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
+		batch[++i] = obj[0].offset >> 32;
 	} else if (gen >= 4) {
 		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
 		reloc.offset += sizeof(uint32_t);
 	} else {
 		batch[i]--;
-		batch[++i] = 0;
+		batch[++i] = obj[0].offset;
 	}
 	batch[++i] = 0xc0ffee;
 	batch[++i] = MI_BATCH_BUFFER_END;
 	gem_write(fd, obj[1].handle, 0, batch, sizeof(batch));
+
 	gem_execbuf(fd, &execbuf);
+
 	gem_close(fd, obj[1].handle);
+	intel_allocator_free(ahnd, obj[1].handle);
 
 	gem_read(fd, obj[0].handle, 0, batch, sizeof(batch));
 	gem_close(fd, obj[0].handle);
+	intel_allocator_free(ahnd, obj[0].handle);
 	igt_assert_eq(*batch, 0xc0ffee);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+	intel_allocator_close(ahnd);
 }
 
 #define PAGES 1
@@ -102,7 +128,9 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
 	struct drm_i915_gem_execbuffer2 execbuf;
 #define NCACHELINES (4096/64)
 	uint32_t *batch;
+	uint64_t ahnd, reloc_value;
 	int i;
+	bool do_relocs = gem_has_relocations(fd);
 
 	reloc = calloc(NCACHELINES, sizeof(*reloc));
 	igt_assert(reloc);
@@ -114,36 +142,58 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
 	if (gen > 3 && gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
 	obj = calloc(execbuf.buffer_count, sizeof(*obj));
 	igt_assert(obj);
-	for (i = 0; i < execbuf.buffer_count; i++)
+	for (i = 0; i < execbuf.buffer_count; i++) {
 		obj[i].handle = gem_create(fd, 4096);
-	obj[i-1].relocs_ptr = to_user_pointer(reloc);
-	obj[i-1].relocation_count = NCACHELINES;
+
+		if (!do_relocs) {
+			obj[i].offset = intel_allocator_alloc(ahnd, obj[i].handle,
+							      4096, ALIGNMENT);
+			obj[i].offset = CANONICAL(obj[i].offset);
+			obj[i].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+				       EXEC_OBJECT_PINNED;
+			if (i + 1 < execbuf.buffer_count)
+				obj[i].flags |= EXEC_OBJECT_WRITE;
+		}
+	}
+	if (do_relocs) {
+		obj[i-1].relocs_ptr = to_user_pointer(reloc);
+		obj[i-1].relocation_count = NCACHELINES;
+	}
 	execbuf.buffers_ptr = to_user_pointer(obj);
 
 	batch = gem_mmap__cpu(fd, obj[i-1].handle, 0, 4096, PROT_WRITE);
 
 	i = 0;
 	for (unsigned n = 0; n < NCACHELINES; n++) {
+
 		reloc[n].target_handle = obj[n % (execbuf.buffer_count-1)].handle;
-		reloc[n].presumed_offset = -1;
-		reloc[n].offset = (i + 1)*sizeof(uint32_t);
 		reloc[n].delta = 4 * (n * 16 + n % 16);
-		reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+
+		if (do_relocs) {
+			reloc[n].presumed_offset = -1;
+			reloc[n].offset = (i + 1)*sizeof(uint32_t);
+			reloc[n].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+			reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+			reloc_value = 0;
+		} else {
+			reloc_value = obj[n % (execbuf.buffer_count-1)].offset +
+				      reloc[n].delta;
+		}
 
 		batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 		if (gen >= 8) {
-			batch[++i] = 0;
-			batch[++i] = 0;
+			batch[++i] = reloc_value;
+			batch[++i] = reloc_value >> 32;
 		} else if (gen >= 4) {
 			batch[++i] = 0;
-			batch[++i] = 0;
+			batch[++i] = reloc_value;
 			reloc[n].offset += sizeof(uint32_t);
 		} else {
 			batch[i]--;
-			batch[++i] = 0;
+			batch[++i] = reloc_value;
 		}
 		batch[++i] = n | ~n << 16;
 		i++;
@@ -163,11 +213,14 @@ static void store_cachelines(int fd, const struct intel_execution_engine2 *e,
 	}
 	free(reloc);
 
-	for (unsigned n = 0; n < execbuf.buffer_count; n++)
+	for (unsigned n = 0; n < execbuf.buffer_count; n++) {
 		gem_close(fd, obj[n].handle);
+		intel_allocator_free(ahnd, obj[n].handle);
+	}
 	free(obj);
 
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+	intel_allocator_close(ahnd);
 }
 
 static void store_all(int fd)
@@ -179,10 +232,11 @@ static void store_all(int fd)
 	struct drm_i915_gem_execbuffer2 execbuf;
 	unsigned *engines, *permuted;
 	uint32_t batch[16];
-	uint64_t offset;
+	uint64_t offset, ahnd, reloc_value;
 	unsigned nengine;
-	int value;
+	int value, address;
 	int i, j;
+	bool do_relocs = gem_has_relocations(fd);
 
 	nengine = 0;
 	__for_each_physical_engine(fd, engine) {
@@ -207,24 +261,43 @@ static void store_all(int fd)
 	if (gen < 6)
 		execbuf.flags |= I915_EXEC_SECURE;
 
+	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
+
 	memset(obj, 0, sizeof(obj));
 	obj[0].handle = gem_create(fd, nengine*sizeof(uint32_t));
 	obj[1].handle = gem_create(fd, 2*nengine*sizeof(batch));
-	obj[1].relocation_count = 1;
+
+	if (do_relocs) {
+		obj[1].relocation_count = 1;
+	} else {
+		obj[0].offset = intel_allocator_alloc(ahnd, obj[0].handle,
+						      nengine*sizeof(uint32_t),
+						      ALIGNMENT);
+		obj[0].offset = CANONICAL(obj[0].offset);
+		obj[0].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+				EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+
+		obj[1].offset = intel_allocator_alloc(ahnd, obj[1].handle,
+						      2*nengine*sizeof(batch),
+						      ALIGNMENT);
+		obj[1].offset = CANONICAL(obj[1].offset);
+		obj[1].flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS |
+				EXEC_OBJECT_PINNED;
+	}
 
 	offset = sizeof(uint32_t);
 	i = 0;
 	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
 	if (gen >= 8) {
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 		batch[++i] = 0;
 	} else if (gen >= 4) {
 		batch[++i] = 0;
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 		offset += sizeof(uint32_t);
 	} else {
 		batch[i]--;
-		batch[++i] = 0;
+		batch[address = ++i] = 0;
 	}
 	batch[value = ++i] = 0xc0ffee;
 	batch[++i] = MI_BATCH_BUFFER_END;
@@ -239,30 +312,45 @@ static void store_all(int fd)
 		execbuf.flags |= engine->flags;
 
 		j = 2*nengine;
-		reloc[j].target_handle = obj[0].handle;
-		reloc[j].presumed_offset = ~0;
-		reloc[j].offset = j*sizeof(batch) + offset;
-		reloc[j].delta = nengine*sizeof(uint32_t);
-		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
-
+		if (do_relocs) {
+			reloc[j].target_handle = obj[0].handle;
+			reloc[j].presumed_offset = ~0;
+			reloc[j].offset = j*sizeof(batch) + offset;
+			reloc[j].delta = nengine*sizeof(uint32_t);
+			reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+			reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
+		} else {
+			reloc_value = obj[0].offset + nengine*sizeof(uint32_t);
+			/* If there is no relocation support, we assume gen >= 8. */
+			batch[address] = reloc_value;
+			batch[address + 1] = reloc_value >> 32;
+		}
 		batch[value] = 0xdeadbeef;
+
 		gem_write(fd, obj[1].handle, j*sizeof(batch),
 			  batch, sizeof(batch));
 		execbuf.batch_start_offset = j*sizeof(batch);
 		gem_execbuf(fd, &execbuf);
 
 		j = 2*nengine + 1;
-		reloc[j].target_handle = obj[0].handle;
-		reloc[j].presumed_offset = ~0;
-		reloc[j].offset = j*sizeof(batch) + offset;
-		reloc[j].delta = nengine*sizeof(uint32_t);
-		reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-		obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
-
+		if (do_relocs) {
+			reloc[j].target_handle = obj[0].handle;
+			reloc[j].presumed_offset = ~0;
+			reloc[j].offset = j*sizeof(batch) + offset;
+			reloc[j].delta = nengine*sizeof(uint32_t);
+			reloc[j].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+			reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+			obj[1].relocs_ptr = to_user_pointer(&reloc[j]);
+		} else {
+			reloc_value = obj[0].offset + nengine*sizeof(uint32_t);
+			batch[address] = reloc_value;
+			/* If there is no relocation support, we assume gen >= 8. */
+			batch[address] = reloc_value;
+			batch[address + 1] = reloc_value >> 32;
+		}
 		batch[value] = nengine;
+
 		gem_write(fd, obj[1].handle, j*sizeof(batch),
 			  batch, sizeof(batch));
 		execbuf.batch_start_offset = j*sizeof(batch);
@@ -273,30 +361,38 @@ static void store_all(int fd)
 	gem_sync(fd, obj[1].handle);
 
 	for (i = 0; i < nengine; i++) {
-		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
 		execbuf.batch_start_offset = 2*i*sizeof(batch);
 		memcpy(permuted, engines, nengine*sizeof(engines[0]));
 		igt_permute_array(permuted, nengine, igt_exchange_int);
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i]);
+
 		for (j = 0; j < nengine; j++) {
 			execbuf.flags &= ~ENGINE_MASK;
 			execbuf.flags |= permuted[j];
 			gem_execbuf(fd, &execbuf);
 		}
-		obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
+
 		execbuf.batch_start_offset = (2*i+1)*sizeof(batch);
 		execbuf.flags &= ~ENGINE_MASK;
 		execbuf.flags |= engines[i];
+		if (do_relocs)
+			obj[1].relocs_ptr = to_user_pointer(&reloc[2*i+1]);
+
 		gem_execbuf(fd, &execbuf);
 	}
 	gem_close(fd, obj[1].handle);
+	intel_allocator_free(ahnd, obj[1].handle);
 
 	gem_read(fd, obj[0].handle, 0, engines, nengine*sizeof(engines[0]));
 	gem_close(fd, obj[0].handle);
+	intel_allocator_free(ahnd, obj[0].handle);
 
 	for (i = 0; i < nengine; i++)
 		igt_assert_eq_u32(engines[i], i);
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 
+	intel_allocator_close(ahnd);
 	free(permuted);
 	free(engines);
 	free(reloc);
-- 
2.25.1

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[igt-dev] ✗ Fi.CI.BAT: failure for Keep tests working without relocations (rev3)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 10348 bytes --]

== Series Details ==

Series: Keep tests working without relocations (rev3)
URL   : https://patchwork.freedesktop.org/series/90049/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10196 -> IGTPW_5903
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_5903 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_5903, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_5903:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_gttfill@basic:
    - fi-icl-y:           [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-icl-y/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-icl-y/igt@gem_exec_gttfill@basic.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@execlists:
    - {fi-ehl-2}:         [DMESG-FAIL][3] ([i915#1222]) -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-ehl-2/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-ehl-2/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gtt:
    - {fi-tgl-dsi}:       [PASS][5] -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-tgl-dsi/igt@i915_selftest@live@gtt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-tgl-dsi/igt@i915_selftest@live@gtt.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10196 and IGTPW_5903:

### New IGT tests (8) ###

  * igt@i915_selftest@atomic-pipe-a-tiling-x:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@blt:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@client:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@execlists:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@gem_execbuf:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@hangcheck:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@memory_region:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_selftest@atomic-pipe-a-tiling-x@reset:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in IGTPW_5903 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][8] -> [FAIL][9] ([i915#2203] / [i915#579])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@evict:
    - fi-tgl-u2:          [PASS][10] -> [DMESG-WARN][11] ([i915#2867]) +7 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-tgl-u2/igt@i915_selftest@live@evict.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-tgl-u2/igt@i915_selftest@live@evict.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-tgl-u2:          [FAIL][12] ([i915#1888]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live@gem_execbuf:
    - {fi-ehl-2}:         [DMESG-WARN][14] ([i915#1222]) -> [PASS][15] +5 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-ehl-2/igt@i915_selftest@live@gem_execbuf.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-ehl-2/igt@i915_selftest@live@gem_execbuf.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][16] ([i915#2782]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [DMESG-WARN][18] ([i915#2868]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_selftest@live@execlists:
    - fi-cfl-8109u:       [INCOMPLETE][20] ([i915#3462]) -> [DMESG-FAIL][21] ([i915#3462])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-cfl-8109u/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - fi-kbl-x1275:       [FAIL][22] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][23] ([i915#1436] / [i915#3363])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-kbl-x1275/igt@runner@aborted.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-kbl-x1275/igt@runner@aborted.html
    - fi-cfl-8109u:       [FAIL][24] ([i915#3363]) -> [FAIL][25] ([i915#2426] / [i915#3363])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-cfl-8109u/igt@runner@aborted.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-cfl-8109u/igt@runner@aborted.html
    - fi-glk-dsi:         [FAIL][26] ([i915#3363] / [k.org#202321]) -> [FAIL][27] ([i915#2426] / [i915#3363] / [k.org#202321])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-glk-dsi/igt@runner@aborted.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-glk-dsi/igt@runner@aborted.html
    - fi-bdw-5557u:       [FAIL][28] ([i915#2426] / [i915#3462]) -> [FAIL][29] ([i915#3462])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-bdw-5557u/igt@runner@aborted.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-bdw-5557u/igt@runner@aborted.html
    - fi-bxt-dsi:         [FAIL][30] ([i915#3363]) -> [FAIL][31] ([i915#2426] / [i915#3363])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-bxt-dsi/igt@runner@aborted.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-bxt-dsi/igt@runner@aborted.html
    - fi-cfl-guc:         [FAIL][32] ([i915#3363]) -> [FAIL][33] ([i915#2426] / [i915#3363])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-cfl-guc/igt@runner@aborted.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-cfl-guc/igt@runner@aborted.html
    - fi-skl-6700k2:      [FAIL][34] ([i915#1436] / [i915#3363]) -> [FAIL][35] ([i915#1436] / [i915#2426] / [i915#3363])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10196/fi-skl-6700k2/igt@runner@aborted.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/fi-skl-6700k2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
  [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (44 -> 40)
------------------------------

  Additional (1): fi-rkl-11500t 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-apl-guc fi-dg1-1 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6103 -> IGTPW_5903

  CI-20190529: 20190529
  CI_DRM_10196: 1588f8e61fe15d12826ca07d41c0a108a26006cc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_5903: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/index.html
  IGT_6103: 3aa79e55e73d4a49a5222e5dfde486b800a29fe7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5903/index.html

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