* [PATCH v2] drm/i915: Document the Virtual Engine uAPI @ 2021-06-14 9:09 ` Tvrtko Ursulin 0 siblings, 0 replies; 9+ messages in thread From: Tvrtko Ursulin @ 2021-06-14 9:09 UTC (permalink / raw) To: Intel-gfx; +Cc: dri-devel, Tvrtko Ursulin From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A little bit of documentation covering the topics of engine discovery, context engine maps and virtual engines. It is not very detailed but supposed to be a starting point of giving a brief high level overview of general principles and intended use cases. v2: * Have the text in uapi header and link from there. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> --- Documentation/gpu/i915.rst | 18 ++++ include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 42ce0196930a..00aa55bbe0fd 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation. +Engine Discovery uAPI +--------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Engine Discovery uAPI + +Context Engine Map uAPI +----------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Context Engine Map uAPI + +Virtual Engine uAPI +------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Virtual Engine uAPI + Locking Guidelines ------------------ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index a1cb4aa035a9..2f70c48567c0 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { __u32 rsvd; }; +/** + * DOC: Virtual Engine uAPI + * + * Virtual engine is a concept where userspace is able to configure a set of + * physical engines, submit a batch buffer, and let the driver execute it on any + * engine from the set as it sees fit. + * + * This is primarily useful on parts which have multiple instances of a same + * class engine, like for example GT3+ Skylake parts with their two VCS engines. + * + * For instance userspace can enumerate all engines of a certain class using the + * previously described `Engine Discovery uAPI`_. After that userspace can + * create a GEM context with a placeholder slot for the virtual engine (using + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class + * and instance respectively) and finally using the + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in + * the same reserved slot. + * + * Example of creating a virtual engine and submitting a batch buffer to it: + * + * .. code-block:: C + * + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, + * .engine_index = 0, // Place this virtual engine into engine map slot 0 + * .num_siblings = 2, + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, + * }; + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { + * .engines = { { I915_ENGINE_CLASS_INVALID, + * I915_ENGINE_CLASS_INVALID_NONE } }, + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension + * }; + * struct drm_i915_gem_context_create_ext_setparam p_engines = { + * .base = { + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + * }, + * .param = { + * .param = I915_CONTEXT_PARAM_ENGINES, + * .value = to_user_pointer(&engines), + * .size = sizeof(engines), + * }, + * }; + * struct drm_i915_gem_context_create_ext create = { + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + * .extensions = to_user_pointer(&p_engines); + * }; + * + * ctx_id = gem_context_create_ext(drm_fd, &create); + * + * // Now we have created a GEM context with its engine map containing a + * // single virtual engine. Submissions to this slot can go either to + * // vcs0 or vcs1, depending on the load balancing algorithm used inside + * // the driver. The load balancing is dynamic from one batch buffer to + * // another and transparent to userspace. + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine + * gem_execbuf(drm_fd, &execbuf); + */ + /* * i915_context_engines_load_balance: * @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { struct i915_engine_class_instance engines[N__]; \ } __attribute__((packed)) name__ +/** + * DOC: Context Engine Map uAPI + * + * Context engine map is a new way of addressing engines when submitting batch- + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` + * inside the flags field of `struct drm_i915_gem_execbuffer2`. + * + * To use it created GEM contexts need to be configured with a list of engines + * the user is intending to submit to. This is accomplished using the + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct + * i915_context_param_engines`. + * + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the + * configured map. + * + * Example of creating such context and submitting against it: + * + * .. code-block:: C + * + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, + * { I915_ENGINE_CLASS_COPY, 0 } } + * }; + * struct drm_i915_gem_context_create_ext_setparam p_engines = { + * .base = { + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + * }, + * .param = { + * .param = I915_CONTEXT_PARAM_ENGINES, + * .value = to_user_pointer(&engines), + * .size = sizeof(engines), + * }, + * }; + * struct drm_i915_gem_context_create_ext create = { + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + * .extensions = to_user_pointer(&p_engines); + * }; + * + * ctx_id = gem_context_create_ext(drm_fd, &create); + * + * // We have now created a GEM context with two engines in the map: + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines + * // will not be accessible from this context. + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context + * gem_execbuf(drm_fd, &execbuf); + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context + * gem_execbuf(drm_fd, &execbuf); + */ + struct i915_context_param_engines { __u64 extensions; /* linked chain of extension blocks, 0 terminates */ #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/** + * DOC: Engine Discovery uAPI + * + * Engine discovery uAPI is a way of enumerating physical engines present in a + * GPU associated with an open i915 DRM file descriptor. This supersedes the old + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like + * `I915_PARAM_HAS_BLT`. + * + * The need for this interface came starting with Icelake and newer GPUs, which + * started to establish a pattern of having multiple engines of a same class, + * where not all instances were always completely functionally equivalent. + * + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. + * + * Example for getting the list of engines: + * + * .. code-block:: C + * + * struct drm_i915_query_engine_info *info; + * struct drm_i915_query_item item = { + * .query_id = DRM_I915_QUERY_ENGINE_INFO; + * }; + * struct drm_i915_query query = { + * .num_items = 1, + * .items_ptr = (uintptr_t)&item, + * }; + * int err, i; + * + * // First query the size of the blob we need, this needs to be large + * // enough to hold our array of engines. The kernel will fill out the + * // item.length for us, which is the number of bytes we need. + * // + * // Alternatively a large buffer can be allocated straight away enabling + * // querying in one pass, in which case item.length should contain the + * // length of the provided buffer. + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * info = calloc(1, item.length); + * // Now that we allocated the required number of bytes, we call the ioctl + * // again, this time with the data_ptr pointing to our newly allocated + * // blob, which the kernel can then populate with info on all engines. + * item.data_ptr = (uintptr_t)&info, + * + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * // We can now access each engine in the array + * for (i = 0; i < info->num_engines; i++) { + * struct drm_i915_engine_info einfo = info->engines[i]; + * u16 class = einfo.engine.class; + * u16 instance = einfo.engine.instance; + * .... + * } + * + * free(info); + * + * Each of the enumerated engines, apart from being defined by its class and + * instance (see `struct i915_engine_class_instance`), also can have flags and + * capabilities defined as documented in i915_drm.h. + * + * For instance video engines which support HEVC encoding will have the + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. + * + * Engine discovery only fully comes to its own when combined with the new way + * of addressing engines when submitting batch buffers using contexts with + * engine maps configured. + */ + /** * struct drm_i915_engine_info * -- 2.30.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915: Document the Virtual Engine uAPI @ 2021-06-14 9:09 ` Tvrtko Ursulin 0 siblings, 0 replies; 9+ messages in thread From: Tvrtko Ursulin @ 2021-06-14 9:09 UTC (permalink / raw) To: Intel-gfx; +Cc: dri-devel From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A little bit of documentation covering the topics of engine discovery, context engine maps and virtual engines. It is not very detailed but supposed to be a starting point of giving a brief high level overview of general principles and intended use cases. v2: * Have the text in uapi header and link from there. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> --- Documentation/gpu/i915.rst | 18 ++++ include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ 2 files changed, 206 insertions(+) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 42ce0196930a..00aa55bbe0fd 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that refer to GPU-addresses so that the kernel can edit the buffer correctly. This process is dubbed relocation. +Engine Discovery uAPI +--------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Engine Discovery uAPI + +Context Engine Map uAPI +----------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Context Engine Map uAPI + +Virtual Engine uAPI +------------------- + +.. kernel-doc:: include/uapi/drm/i915_drm.h + :doc: Virtual Engine uAPI + Locking Guidelines ------------------ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index a1cb4aa035a9..2f70c48567c0 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { __u32 rsvd; }; +/** + * DOC: Virtual Engine uAPI + * + * Virtual engine is a concept where userspace is able to configure a set of + * physical engines, submit a batch buffer, and let the driver execute it on any + * engine from the set as it sees fit. + * + * This is primarily useful on parts which have multiple instances of a same + * class engine, like for example GT3+ Skylake parts with their two VCS engines. + * + * For instance userspace can enumerate all engines of a certain class using the + * previously described `Engine Discovery uAPI`_. After that userspace can + * create a GEM context with a placeholder slot for the virtual engine (using + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class + * and instance respectively) and finally using the + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in + * the same reserved slot. + * + * Example of creating a virtual engine and submitting a batch buffer to it: + * + * .. code-block:: C + * + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, + * .engine_index = 0, // Place this virtual engine into engine map slot 0 + * .num_siblings = 2, + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, + * }; + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { + * .engines = { { I915_ENGINE_CLASS_INVALID, + * I915_ENGINE_CLASS_INVALID_NONE } }, + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension + * }; + * struct drm_i915_gem_context_create_ext_setparam p_engines = { + * .base = { + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + * }, + * .param = { + * .param = I915_CONTEXT_PARAM_ENGINES, + * .value = to_user_pointer(&engines), + * .size = sizeof(engines), + * }, + * }; + * struct drm_i915_gem_context_create_ext create = { + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + * .extensions = to_user_pointer(&p_engines); + * }; + * + * ctx_id = gem_context_create_ext(drm_fd, &create); + * + * // Now we have created a GEM context with its engine map containing a + * // single virtual engine. Submissions to this slot can go either to + * // vcs0 or vcs1, depending on the load balancing algorithm used inside + * // the driver. The load balancing is dynamic from one batch buffer to + * // another and transparent to userspace. + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine + * gem_execbuf(drm_fd, &execbuf); + */ + /* * i915_context_engines_load_balance: * @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { struct i915_engine_class_instance engines[N__]; \ } __attribute__((packed)) name__ +/** + * DOC: Context Engine Map uAPI + * + * Context engine map is a new way of addressing engines when submitting batch- + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` + * inside the flags field of `struct drm_i915_gem_execbuffer2`. + * + * To use it created GEM contexts need to be configured with a list of engines + * the user is intending to submit to. This is accomplished using the + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct + * i915_context_param_engines`. + * + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the + * configured map. + * + * Example of creating such context and submitting against it: + * + * .. code-block:: C + * + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, + * { I915_ENGINE_CLASS_COPY, 0 } } + * }; + * struct drm_i915_gem_context_create_ext_setparam p_engines = { + * .base = { + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, + * }, + * .param = { + * .param = I915_CONTEXT_PARAM_ENGINES, + * .value = to_user_pointer(&engines), + * .size = sizeof(engines), + * }, + * }; + * struct drm_i915_gem_context_create_ext create = { + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, + * .extensions = to_user_pointer(&p_engines); + * }; + * + * ctx_id = gem_context_create_ext(drm_fd, &create); + * + * // We have now created a GEM context with two engines in the map: + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines + * // will not be accessible from this context. + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context + * gem_execbuf(drm_fd, &execbuf); + * + * ... + * execbuf.rsvd1 = ctx_id; + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context + * gem_execbuf(drm_fd, &execbuf); + */ + struct i915_context_param_engines { __u64 extensions; /* linked chain of extension blocks, 0 terminates */ #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/** + * DOC: Engine Discovery uAPI + * + * Engine discovery uAPI is a way of enumerating physical engines present in a + * GPU associated with an open i915 DRM file descriptor. This supersedes the old + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like + * `I915_PARAM_HAS_BLT`. + * + * The need for this interface came starting with Icelake and newer GPUs, which + * started to establish a pattern of having multiple engines of a same class, + * where not all instances were always completely functionally equivalent. + * + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. + * + * Example for getting the list of engines: + * + * .. code-block:: C + * + * struct drm_i915_query_engine_info *info; + * struct drm_i915_query_item item = { + * .query_id = DRM_I915_QUERY_ENGINE_INFO; + * }; + * struct drm_i915_query query = { + * .num_items = 1, + * .items_ptr = (uintptr_t)&item, + * }; + * int err, i; + * + * // First query the size of the blob we need, this needs to be large + * // enough to hold our array of engines. The kernel will fill out the + * // item.length for us, which is the number of bytes we need. + * // + * // Alternatively a large buffer can be allocated straight away enabling + * // querying in one pass, in which case item.length should contain the + * // length of the provided buffer. + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * info = calloc(1, item.length); + * // Now that we allocated the required number of bytes, we call the ioctl + * // again, this time with the data_ptr pointing to our newly allocated + * // blob, which the kernel can then populate with info on all engines. + * item.data_ptr = (uintptr_t)&info, + * + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); + * if (err) ... + * + * // We can now access each engine in the array + * for (i = 0; i < info->num_engines; i++) { + * struct drm_i915_engine_info einfo = info->engines[i]; + * u16 class = einfo.engine.class; + * u16 instance = einfo.engine.instance; + * .... + * } + * + * free(info); + * + * Each of the enumerated engines, apart from being defined by its class and + * instance (see `struct i915_engine_class_instance`), also can have flags and + * capabilities defined as documented in i915_drm.h. + * + * For instance video engines which support HEVC encoding will have the + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. + * + * Engine discovery only fully comes to its own when combined with the new way + * of addressing engines when submitting batch buffers using contexts with + * engine maps configured. + */ + /** * struct drm_i915_engine_info * -- 2.30.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Document the Virtual Engine uAPI (rev2) 2021-06-14 9:09 ` [Intel-gfx] " Tvrtko Ursulin (?) @ 2021-06-14 13:32 ` Patchwork -1 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-06-14 13:32 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev2) URL : https://patchwork.freedesktop.org/series/91406/ State : warning == Summary == $ dim checkpatch origin/drm-tip af02f5aa318e drm/i915: Document the Virtual Engine uAPI -:76: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #76: FILE: include/uapi/drm/i915_drm.h:1831: + * ^II915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {$ -:77: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #77: FILE: include/uapi/drm/i915_drm.h:1832: + * ^I^I.base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,$ -:78: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #78: FILE: include/uapi/drm/i915_drm.h:1833: + * ^I^I.engine_index = 0, // Place this virtual engine into engine map slot 0$ -:79: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #79: FILE: include/uapi/drm/i915_drm.h:1834: + * ^I^I.num_siblings = 2,$ -:80: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #80: FILE: include/uapi/drm/i915_drm.h:1835: + * ^I^I.engines = { { I915_ENGINE_CLASS_VIDEO, 0 },$ -:81: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #81: FILE: include/uapi/drm/i915_drm.h:1836: + * ^I^I^I { I915_ENGINE_CLASS_VIDEO, 1 }, },$ -:82: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #82: FILE: include/uapi/drm/i915_drm.h:1837: + * ^I};$ -:83: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #83: FILE: include/uapi/drm/i915_drm.h:1838: + * ^II915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {$ -:84: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #84: FILE: include/uapi/drm/i915_drm.h:1839: + * ^I^I.engines = { { I915_ENGINE_CLASS_INVALID,$ -:85: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #85: FILE: include/uapi/drm/i915_drm.h:1840: + * ^I^I^I I915_ENGINE_CLASS_INVALID_NONE } },$ -:86: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #86: FILE: include/uapi/drm/i915_drm.h:1841: + * ^I^I.extensions = to_user_pointer(&virtual), // Chains after load_balance extension$ -:87: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #87: FILE: include/uapi/drm/i915_drm.h:1842: + * ^I};$ -:88: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #88: FILE: include/uapi/drm/i915_drm.h:1843: + * ^Istruct drm_i915_gem_context_create_ext_setparam p_engines = {$ -:89: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #89: FILE: include/uapi/drm/i915_drm.h:1844: + * ^I^I.base = {$ -:90: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #90: FILE: include/uapi/drm/i915_drm.h:1845: + * ^I^I^I.name = I915_CONTEXT_CREATE_EXT_SETPARAM,$ -:91: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #91: FILE: include/uapi/drm/i915_drm.h:1846: + * ^I^I},$ -:92: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #92: FILE: include/uapi/drm/i915_drm.h:1847: + * ^I^I.param = {$ -:93: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #93: FILE: include/uapi/drm/i915_drm.h:1848: + * ^I^I^I.param = I915_CONTEXT_PARAM_ENGINES,$ -:94: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #94: FILE: include/uapi/drm/i915_drm.h:1849: + * ^I^I^I.value = to_user_pointer(&engines),$ -:95: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #95: FILE: include/uapi/drm/i915_drm.h:1850: + * ^I^I^I.size = sizeof(engines),$ -:96: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #96: FILE: include/uapi/drm/i915_drm.h:1851: + * ^I^I},$ -:97: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #97: FILE: include/uapi/drm/i915_drm.h:1852: + * ^I};$ -:98: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #98: FILE: include/uapi/drm/i915_drm.h:1853: + * ^Istruct drm_i915_gem_context_create_ext create = {$ -:99: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #99: FILE: include/uapi/drm/i915_drm.h:1854: + * ^I^I.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,$ -:100: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #100: FILE: include/uapi/drm/i915_drm.h:1855: + * ^I^I.extensions = to_user_pointer(&p_engines);$ -:101: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #101: FILE: include/uapi/drm/i915_drm.h:1856: + * ^I};$ -:103: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #103: FILE: include/uapi/drm/i915_drm.h:1858: + * ^Ictx_id = gem_context_create_ext(drm_fd, &create);$ -:105: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #105: FILE: include/uapi/drm/i915_drm.h:1860: + * ^I// Now we have created a GEM context with its engine map containing a$ -:106: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #106: FILE: include/uapi/drm/i915_drm.h:1861: + * ^I// single virtual engine. Submissions to this slot can go either to$ -:107: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #107: FILE: include/uapi/drm/i915_drm.h:1862: + * ^I// vcs0 or vcs1, depending on the load balancing algorithm used inside$ -:108: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #108: FILE: include/uapi/drm/i915_drm.h:1863: + * ^I// the driver. The load balancing is dynamic from one batch buffer to$ -:109: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #109: FILE: include/uapi/drm/i915_drm.h:1864: + * ^I// another and transparent to userspace.$ -:111: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #111: FILE: include/uapi/drm/i915_drm.h:1866: + * ^I...$ -:112: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #112: FILE: include/uapi/drm/i915_drm.h:1867: + * ^Iexecbuf.rsvd1 = ctx_id;$ -:113: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #113: FILE: include/uapi/drm/i915_drm.h:1868: + * ^Iexecbuf.flags = 0; // Submits to index 0 which is the virtual engine$ -:114: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #114: FILE: include/uapi/drm/i915_drm.h:1869: + * ^Igem_execbuf(drm_fd, &execbuf);$ -:143: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #143: FILE: include/uapi/drm/i915_drm.h:1967: + * ^II915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {$ -:144: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #144: FILE: include/uapi/drm/i915_drm.h:1968: + * ^I^I.engines = { { I915_ENGINE_CLASS_RENDER, 0 },$ -:145: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #145: FILE: include/uapi/drm/i915_drm.h:1969: + * ^I^I^I { I915_ENGINE_CLASS_COPY, 0 } }$ -:146: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #146: FILE: include/uapi/drm/i915_drm.h:1970: + * ^I};$ -:147: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #147: FILE: include/uapi/drm/i915_drm.h:1971: + * ^Istruct drm_i915_gem_context_create_ext_setparam p_engines = {$ -:148: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #148: FILE: include/uapi/drm/i915_drm.h:1972: + * ^I^I.base = {$ -:149: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #149: FILE: include/uapi/drm/i915_drm.h:1973: + * ^I^I^I.name = I915_CONTEXT_CREATE_EXT_SETPARAM,$ -:150: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #150: FILE: include/uapi/drm/i915_drm.h:1974: + * ^I^I},$ -:151: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #151: FILE: include/uapi/drm/i915_drm.h:1975: + * ^I^I.param = {$ -:152: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #152: FILE: include/uapi/drm/i915_drm.h:1976: + * ^I^I^I.param = I915_CONTEXT_PARAM_ENGINES,$ -:153: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #153: FILE: include/uapi/drm/i915_drm.h:1977: + * ^I^I^I.value = to_user_pointer(&engines),$ -:154: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #154: FILE: include/uapi/drm/i915_drm.h:1978: + * ^I^I^I.size = sizeof(engines),$ -:155: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #155: FILE: include/uapi/drm/i915_drm.h:1979: + * ^I^I},$ -:156: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #156: FILE: include/uapi/drm/i915_drm.h:1980: + * ^I};$ -:157: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #157: FILE: include/uapi/drm/i915_drm.h:1981: + * ^Istruct drm_i915_gem_context_create_ext create = {$ -:158: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #158: FILE: include/uapi/drm/i915_drm.h:1982: + * ^I^I.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,$ -:159: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #159: FILE: include/uapi/drm/i915_drm.h:1983: + * ^I^I.extensions = to_user_pointer(&p_engines);$ -:160: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #160: FILE: include/uapi/drm/i915_drm.h:1984: + * ^I};$ -:162: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #162: FILE: include/uapi/drm/i915_drm.h:1986: + * ^Ictx_id = gem_context_create_ext(drm_fd, &create);$ -:164: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #164: FILE: include/uapi/drm/i915_drm.h:1988: + * ^I// We have now created a GEM context with two engines in the map:$ -:165: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #165: FILE: include/uapi/drm/i915_drm.h:1989: + * ^I// Index 0 points to rcs0 while index 1 points to bcs0. Other engines$ -:166: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #166: FILE: include/uapi/drm/i915_drm.h:1990: + * ^I// will not be accessible from this context.$ -:168: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #168: FILE: include/uapi/drm/i915_drm.h:1992: + * ^I...$ -:169: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #169: FILE: include/uapi/drm/i915_drm.h:1993: + * ^Iexecbuf.rsvd1 = ctx_id;$ -:170: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #170: FILE: include/uapi/drm/i915_drm.h:1994: + * ^Iexecbuf.flags = 0; // Submits to index 0, which is rcs0 for this context$ -:171: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #171: FILE: include/uapi/drm/i915_drm.h:1995: + * ^Igem_execbuf(drm_fd, &execbuf);$ -:173: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #173: FILE: include/uapi/drm/i915_drm.h:1997: + * ^I...$ -:174: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #174: FILE: include/uapi/drm/i915_drm.h:1998: + * ^Iexecbuf.rsvd1 = ctx_id;$ -:175: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #175: FILE: include/uapi/drm/i915_drm.h:1999: + * ^Iexecbuf.flags = 1; // Submits to index 0, which is bcs0 for this context$ -:176: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #176: FILE: include/uapi/drm/i915_drm.h:2000: + * ^Igem_execbuf(drm_fd, &execbuf);$ -:205: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #205: FILE: include/uapi/drm/i915_drm.h:2515: + * ^Istruct drm_i915_query_engine_info *info;$ -:206: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #206: FILE: include/uapi/drm/i915_drm.h:2516: + * ^Istruct drm_i915_query_item item = {$ -:207: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #207: FILE: include/uapi/drm/i915_drm.h:2517: + * ^I^I.query_id = DRM_I915_QUERY_ENGINE_INFO;$ -:208: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #208: FILE: include/uapi/drm/i915_drm.h:2518: + * ^I};$ -:209: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #209: FILE: include/uapi/drm/i915_drm.h:2519: + * ^Istruct drm_i915_query query = {$ -:210: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #210: FILE: include/uapi/drm/i915_drm.h:2520: + * ^I^I.num_items = 1,$ -:211: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #211: FILE: include/uapi/drm/i915_drm.h:2521: + * ^I^I.items_ptr = (uintptr_t)&item,$ -:212: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #212: FILE: include/uapi/drm/i915_drm.h:2522: + * ^I};$ -:213: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #213: FILE: include/uapi/drm/i915_drm.h:2523: + * ^Iint err, i;$ -:215: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #215: FILE: include/uapi/drm/i915_drm.h:2525: + * ^I// First query the size of the blob we need, this needs to be large$ -:216: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #216: FILE: include/uapi/drm/i915_drm.h:2526: + * ^I// enough to hold our array of engines. The kernel will fill out the$ -:217: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #217: FILE: include/uapi/drm/i915_drm.h:2527: + * ^I// item.length for us, which is the number of bytes we need.$ -:218: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #218: FILE: include/uapi/drm/i915_drm.h:2528: + * ^I//$ -:219: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #219: FILE: include/uapi/drm/i915_drm.h:2529: + * ^I// Alternatively a large buffer can be allocated straight away enabling$ -:220: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #220: FILE: include/uapi/drm/i915_drm.h:2530: + * ^I// querying in one pass, in which case item.length should contain the$ -:221: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #221: FILE: include/uapi/drm/i915_drm.h:2531: + * ^I// length of the provided buffer.$ -:222: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #222: FILE: include/uapi/drm/i915_drm.h:2532: + * ^Ierr = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);$ -:223: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #223: FILE: include/uapi/drm/i915_drm.h:2533: + * ^Iif (err) ...$ -:225: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #225: FILE: include/uapi/drm/i915_drm.h:2535: + * ^Iinfo = calloc(1, item.length);$ -:226: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #226: FILE: include/uapi/drm/i915_drm.h:2536: + * ^I// Now that we allocated the required number of bytes, we call the ioctl$ -:227: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #227: FILE: include/uapi/drm/i915_drm.h:2537: + * ^I// again, this time with the data_ptr pointing to our newly allocated$ -:228: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #228: FILE: include/uapi/drm/i915_drm.h:2538: + * ^I// blob, which the kernel can then populate with info on all engines.$ -:229: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #229: FILE: include/uapi/drm/i915_drm.h:2539: + * ^Iitem.data_ptr = (uintptr_t)&info,$ -:231: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #231: FILE: include/uapi/drm/i915_drm.h:2541: + * ^Ierr = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);$ -:232: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #232: FILE: include/uapi/drm/i915_drm.h:2542: + * ^Iif (err) ...$ -:234: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #234: FILE: include/uapi/drm/i915_drm.h:2544: + * ^I// We can now access each engine in the array$ -:235: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #235: FILE: include/uapi/drm/i915_drm.h:2545: + * ^Ifor (i = 0; i < info->num_engines; i++) {$ -:236: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #236: FILE: include/uapi/drm/i915_drm.h:2546: + * ^I^Istruct drm_i915_engine_info einfo = info->engines[i];$ -:237: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #237: FILE: include/uapi/drm/i915_drm.h:2547: + * ^I^Iu16 class = einfo.engine.class;$ -:238: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #238: FILE: include/uapi/drm/i915_drm.h:2548: + * ^I^Iu16 instance = einfo.engine.instance;$ -:239: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #239: FILE: include/uapi/drm/i915_drm.h:2549: + * ^I^I....$ -:240: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #240: FILE: include/uapi/drm/i915_drm.h:2550: + * ^I}$ -:242: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #242: FILE: include/uapi/drm/i915_drm.h:2552: + * ^Ifree(info);$ total: 0 errors, 99 warnings, 0 checks, 230 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Document the Virtual Engine uAPI (rev2) 2021-06-14 9:09 ` [Intel-gfx] " Tvrtko Ursulin (?) (?) @ 2021-06-14 14:02 ` Patchwork -1 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-06-14 14:02 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3366 bytes --] == Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev2) URL : https://patchwork.freedesktop.org/series/91406/ State : success == Summary == CI Bug Log - changes from CI_DRM_10218 -> Patchwork_20354 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/index.html Known issues ------------ Here are the changes found in Patchwork_20354 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][2] -> [FAIL][3] ([i915#1372]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [INCOMPLETE][4] ([i915#2782] / [i915#2940]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/fi-bsw-kefka/igt@i915_selftest@live@execlists.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/fi-bsw-kefka/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@hangcheck: - {fi-hsw-gt1}: [INCOMPLETE][6] ([i915#2782]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: [FAIL][8] -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 Participating hosts (44 -> 40) ------------------------------ Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes ------------- * Linux: CI_DRM_10218 -> Patchwork_20354 CI-20190529: 20190529 CI_DRM_10218: d02d55c2c7574218d5f23a7eaef42c6c2f19805e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6104: f8f81bd3752f3126a47d9dbba2d0ab29f7c17a19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20354: af02f5aa318e0448522d43c0cfacb6e436735bf0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af02f5aa318e drm/i915: Document the Virtual Engine uAPI == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/index.html [-- Attachment #1.2: Type: text/html, Size: 4097 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Document the Virtual Engine uAPI (rev2) 2021-06-14 9:09 ` [Intel-gfx] " Tvrtko Ursulin ` (2 preceding siblings ...) (?) @ 2021-06-14 17:16 ` Patchwork -1 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2021-06-14 17:16 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30272 bytes --] == Series Details == Series: drm/i915: Document the Virtual Engine uAPI (rev2) URL : https://patchwork.freedesktop.org/series/91406/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10218_full -> Patchwork_20354_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_20354_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20354_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_20354_full: ### IGT changes ### #### Possible regressions #### * igt@gem_ctx_persistence@replace@vcs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb5/igt@gem_ctx_persistence@replace@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb2/igt@gem_ctx_persistence@replace@vcs0.html Known issues ------------ Here are the changes found in Patchwork_20354_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@blit-noreloc-purge-cache-random: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271]) +301 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb6/igt@api_intel_bb@blit-noreloc-purge-cache-random.html * igt@gem_create@create-clear: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#1888] / [i915#3160]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-glk5/igt@gem_create@create-clear.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-glk2/igt@gem_create@create-clear.html * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl3/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-hang: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hang.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][10] ([i915#2846]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl6/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html - shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_reloc@basic-wide-active@rcs0: - shard-kbl: NOTRUN -> [FAIL][15] ([i915#2389]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@gem_exec_reloc@basic-wide-active@rcs0.html * igt@gem_exec_reloc@basic-wide-active@vcs1: - shard-iclb: NOTRUN -> [FAIL][16] ([i915#2389]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb1/igt@gem_exec_reloc@basic-wide-active@vcs1.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#307]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl8/igt@gem_pread@exhaustion.html - shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl2/igt@gem_pread@exhaustion.html - shard-skl: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl8/igt@gem_pread@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][22] ([i915#2658]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb7/igt@gem_pwrite@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][23] ([i915#3002]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb2/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][24] ([i915#2724]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb6/igt@gem_userptr_blits@vma-merge.html * igt@gem_workarounds@suspend-resume-context: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl5/igt@gem_workarounds@suspend-resume-context.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl10/igt@gem_workarounds@suspend-resume-context.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html * igt@i915_pm_dc@dc6-psr: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#454]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl7/igt@i915_pm_dc@dc6-psr.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl1/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1937]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271]) +230 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl8/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_selftest@live@hangcheck: - shard-snb: NOTRUN -> [INCOMPLETE][33] ([i915#2782]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb2/igt@i915_selftest@live@hangcheck.html * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html * igt@kms_color@pipe-d-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271]) +23 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl10/igt@kms_color@pipe-d-ctm-0-5.html * igt@kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +21 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl7/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html * igt@kms_color_chamelium@pipe-a-ctm-negative: - shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +16 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-negative.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +7 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl2/igt@kms_color_chamelium@pipe-c-ctm-0-25.html - shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_content_protection@uevent: - shard-apl: NOTRUN -> [FAIL][41] ([i915#2105]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl6/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen: - shard-tglb: NOTRUN -> [SKIP][42] ([fdo#109279] / [i915#3359]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen: - shard-tglb: NOTRUN -> [SKIP][43] ([i915#3359]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen.html * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-glk: [PASS][44] -> [FAIL][45] ([i915#72]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-glk4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-glk3/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-glk: [PASS][46] -> [FAIL][47] ([i915#2346]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_dp_tiled_display@basic-test-pattern: - shard-tglb: NOTRUN -> [SKIP][48] ([i915#426]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_dp_tiled_display@basic-test-pattern.html * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled: - shard-skl: [PASS][49] -> [FAIL][50] ([i915#3451]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt: - shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271]) +78 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt: - shard-tglb: NOTRUN -> [SKIP][52] ([fdo#111825]) +7 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][53] -> [FAIL][54] ([i915#1188]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-apl: [PASS][55] -> [DMESG-WARN][56] ([i915#180]) +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +4 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][58] ([i915#265]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-kbl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][60] -> [FAIL][61] ([fdo#108145] / [i915#265]) +2 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-c-tiling-none: - shard-tglb: NOTRUN -> [SKIP][62] ([i915#3536]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_plane_lowres@pipe-c-tiling-none.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl8/igt@kms_psr2_sf@cursor-plane-update-sf.html - shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl2/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +4 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl3/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2: - shard-tglb: NOTRUN -> [SKIP][66] ([i915#2920]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][67] -> [SKIP][68] ([fdo#109441]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-d-wait-idle: - shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html * igt@perf@polling: - shard-skl: [PASS][70] -> [FAIL][71] ([i915#1542]) +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl2/igt@perf@polling.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl7/igt@perf@polling.html * igt@sysfs_clients@create: - shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994]) +4 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl1/igt@sysfs_clients@create.html * igt@sysfs_clients@sema-10: - shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2994]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@sysfs_clients@sema-10.html * igt@sysfs_heartbeat_interval@mixed@vecs0: - shard-skl: [PASS][74] -> [FAIL][75] ([i915#1731]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl5/igt@sysfs_heartbeat_interval@mixed@vecs0.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vecs0.html #### Possible fixes #### * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][76] ([i915#2842]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_fenced_exec_thrash@2-spare-fences: - shard-snb: [INCOMPLETE][78] ([i915#2055]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-snb2/igt@gem_fenced_exec_thrash@2-spare-fences.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-snb2/igt@gem_fenced_exec_thrash@2-spare-fences.html * igt@gem_mmap_gtt@big-copy: - shard-glk: [FAIL][80] ([i915#307]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-glk5/igt@gem_mmap_gtt@big-copy.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-glk2/igt@gem_mmap_gtt@big-copy.html * igt@gem_workarounds@suspend-resume: - shard-skl: [INCOMPLETE][82] ([i915#146] / [i915#198]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl6/igt@gem_workarounds@suspend-resume.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl8/igt@gem_workarounds@suspend-resume.html * igt@i915_selftest@live@execlists: - shard-skl: [INCOMPLETE][84] ([i915#2782]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl1/igt@i915_selftest@live@execlists.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl6/igt@i915_selftest@live@execlists.html * igt@i915_suspend@forcewake: - shard-skl: [INCOMPLETE][86] ([i915#636]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl10/igt@i915_suspend@forcewake.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl10/igt@i915_suspend@forcewake.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][88] ([i915#180]) -> [PASS][89] +3 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled: - shard-glk: [FAIL][90] ([i915#3451]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-glk7/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-glk4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-skl: [DMESG-WARN][92] ([i915#1982]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-apl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][96] ([fdo#108145] / [i915#265]) -> [PASS][97] +1 similar issue [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][98] ([fdo#109441]) -> [PASS][99] +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb7/igt@kms_psr@psr2_cursor_render.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb2/igt@kms_psr@psr2_cursor_render.html * igt@perf_pmu@enable-race@vcs0: - shard-tglb: [INCOMPLETE][100] -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb8/igt@perf_pmu@enable-race@vcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb5/igt@perf_pmu@enable-race@vcs0.html #### Warnings #### * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-iclb: [FAIL][102] ([i915#2852]) -> [FAIL][103] ([i915#2842]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][104] ([i915#1804] / [i915#2684]) -> [WARN][105] ([i915#2684]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][106] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][107] ([fdo#108145] / [i915#1982] / [i915#265]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-0: - shard-iclb: [SKIP][108] ([i915#2920]) -> [SKIP][109] ([i915#658]) +2 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb6/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-1: - shard-iclb: [SKIP][110] ([i915#658]) -> [SKIP][111] ([i915#2920]) +1 similar issue [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html * igt@runner@aborted: - shard-kbl: ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl3/igt@runner@aborted.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl4/igt@runner@aborted.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl7/igt@runner@aborted.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl3/igt@runner@aborted.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl3/igt@runner@aborted.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl4/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-kbl7/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl3/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl4/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl7/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl7/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-kbl1/igt@runner@aborted.html - shard-apl: ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#1814] / [i915#3002] / [i915#3363]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl1/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl3/igt@runner@aborted.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl8/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-apl1/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl1/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl3/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl3/igt@runner@aborted.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-apl8/igt@runner@aborted.html - shard-tglb: ([FAIL][132], [FAIL][133]) ([i915#3002]) -> ([FAIL][134], [FAIL][135], [FAIL][136]) ([i915#2426] / [i915#3002]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb3/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-tglb1/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb6/igt@runner@aborted.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb2/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-tglb2/igt@runner@aborted.html - shard-skl: ([FAIL][137], [FAIL][138]) ([i915#3002] / [i915#3363]) -> ([FAIL][139], [FAIL][140], [FAIL][141]) ([i915#1814] / [i915#2029] / [i915#3002] / [i915#3363]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl3/igt@runner@aborted.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10218/shard-skl8/igt@runner@aborted.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl3/igt@runner@aborted.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl2/igt@runner@aborted.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/shard-skl7/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307 [i915#3160]: == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20354/index.html [-- Attachment #1.2: Type: text/html, Size: 37566 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: Document the Virtual Engine uAPI 2021-06-14 9:09 ` [Intel-gfx] " Tvrtko Ursulin @ 2021-06-17 17:17 ` Daniel Vetter -1 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2021-06-17 17:17 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx, dri-devel, Tvrtko Ursulin On Mon, Jun 14, 2021 at 10:09:59AM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A little bit of documentation covering the topics of engine discovery, > context engine maps and virtual engines. It is not very detailed but > supposed to be a starting point of giving a brief high level overview of > general principles and intended use cases. > > v2: > * Have the text in uapi header and link from there. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Daniel Vetter <daniel@ffwll.ch> What I meant was the kerneldoc directly as kerneldoc for the uapi structs, like Matt has done for e.g. drm_i915_gem_create_ext_memory_regions. But then I also realized that Matt hasn't set up the include for this, so it's not automatic at all yet :-/ -Daniel > --- > Documentation/gpu/i915.rst | 18 ++++ > include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 206 insertions(+) > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index 42ce0196930a..00aa55bbe0fd 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that > refer to GPU-addresses so that the kernel can edit the buffer correctly. > This process is dubbed relocation. > > +Engine Discovery uAPI > +--------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Engine Discovery uAPI > + > +Context Engine Map uAPI > +----------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Context Engine Map uAPI > + > +Virtual Engine uAPI > +------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Virtual Engine uAPI > + > Locking Guidelines > ------------------ > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index a1cb4aa035a9..2f70c48567c0 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { > __u32 rsvd; > }; > > +/** > + * DOC: Virtual Engine uAPI > + * > + * Virtual engine is a concept where userspace is able to configure a set of > + * physical engines, submit a batch buffer, and let the driver execute it on any > + * engine from the set as it sees fit. > + * > + * This is primarily useful on parts which have multiple instances of a same > + * class engine, like for example GT3+ Skylake parts with their two VCS engines. > + * > + * For instance userspace can enumerate all engines of a certain class using the > + * previously described `Engine Discovery uAPI`_. After that userspace can > + * create a GEM context with a placeholder slot for the virtual engine (using > + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class > + * and instance respectively) and finally using the > + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in > + * the same reserved slot. > + * > + * Example of creating a virtual engine and submitting a batch buffer to it: > + * > + * .. code-block:: C > + * > + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { > + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, > + * .engine_index = 0, // Place this virtual engine into engine map slot 0 > + * .num_siblings = 2, > + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, > + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, > + * }; > + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { > + * .engines = { { I915_ENGINE_CLASS_INVALID, > + * I915_ENGINE_CLASS_INVALID_NONE } }, > + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension > + * }; > + * struct drm_i915_gem_context_create_ext_setparam p_engines = { > + * .base = { > + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, > + * }, > + * .param = { > + * .param = I915_CONTEXT_PARAM_ENGINES, > + * .value = to_user_pointer(&engines), > + * .size = sizeof(engines), > + * }, > + * }; > + * struct drm_i915_gem_context_create_ext create = { > + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, > + * .extensions = to_user_pointer(&p_engines); > + * }; > + * > + * ctx_id = gem_context_create_ext(drm_fd, &create); > + * > + * // Now we have created a GEM context with its engine map containing a > + * // single virtual engine. Submissions to this slot can go either to > + * // vcs0 or vcs1, depending on the load balancing algorithm used inside > + * // the driver. The load balancing is dynamic from one batch buffer to > + * // another and transparent to userspace. > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine > + * gem_execbuf(drm_fd, &execbuf); > + */ > + > /* > * i915_context_engines_load_balance: > * > @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { > struct i915_engine_class_instance engines[N__]; \ > } __attribute__((packed)) name__ > > +/** > + * DOC: Context Engine Map uAPI > + * > + * Context engine map is a new way of addressing engines when submitting batch- > + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` > + * inside the flags field of `struct drm_i915_gem_execbuffer2`. > + * > + * To use it created GEM contexts need to be configured with a list of engines > + * the user is intending to submit to. This is accomplished using the > + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct > + * i915_context_param_engines`. > + * > + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the > + * configured map. > + * > + * Example of creating such context and submitting against it: > + * > + * .. code-block:: C > + * > + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { > + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, > + * { I915_ENGINE_CLASS_COPY, 0 } } > + * }; > + * struct drm_i915_gem_context_create_ext_setparam p_engines = { > + * .base = { > + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, > + * }, > + * .param = { > + * .param = I915_CONTEXT_PARAM_ENGINES, > + * .value = to_user_pointer(&engines), > + * .size = sizeof(engines), > + * }, > + * }; > + * struct drm_i915_gem_context_create_ext create = { > + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, > + * .extensions = to_user_pointer(&p_engines); > + * }; > + * > + * ctx_id = gem_context_create_ext(drm_fd, &create); > + * > + * // We have now created a GEM context with two engines in the map: > + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines > + * // will not be accessible from this context. > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context > + * gem_execbuf(drm_fd, &execbuf); > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context > + * gem_execbuf(drm_fd, &execbuf); > + */ > + > struct i915_context_param_engines { > __u64 extensions; /* linked chain of extension blocks, 0 terminates */ > #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ > @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { > __u8 data[]; > }; > > +/** > + * DOC: Engine Discovery uAPI > + * > + * Engine discovery uAPI is a way of enumerating physical engines present in a > + * GPU associated with an open i915 DRM file descriptor. This supersedes the old > + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like > + * `I915_PARAM_HAS_BLT`. > + * > + * The need for this interface came starting with Icelake and newer GPUs, which > + * started to establish a pattern of having multiple engines of a same class, > + * where not all instances were always completely functionally equivalent. > + * > + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the > + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. > + * > + * Example for getting the list of engines: > + * > + * .. code-block:: C > + * > + * struct drm_i915_query_engine_info *info; > + * struct drm_i915_query_item item = { > + * .query_id = DRM_I915_QUERY_ENGINE_INFO; > + * }; > + * struct drm_i915_query query = { > + * .num_items = 1, > + * .items_ptr = (uintptr_t)&item, > + * }; > + * int err, i; > + * > + * // First query the size of the blob we need, this needs to be large > + * // enough to hold our array of engines. The kernel will fill out the > + * // item.length for us, which is the number of bytes we need. > + * // > + * // Alternatively a large buffer can be allocated straight away enabling > + * // querying in one pass, in which case item.length should contain the > + * // length of the provided buffer. > + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); > + * if (err) ... > + * > + * info = calloc(1, item.length); > + * // Now that we allocated the required number of bytes, we call the ioctl > + * // again, this time with the data_ptr pointing to our newly allocated > + * // blob, which the kernel can then populate with info on all engines. > + * item.data_ptr = (uintptr_t)&info, > + * > + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); > + * if (err) ... > + * > + * // We can now access each engine in the array > + * for (i = 0; i < info->num_engines; i++) { > + * struct drm_i915_engine_info einfo = info->engines[i]; > + * u16 class = einfo.engine.class; > + * u16 instance = einfo.engine.instance; > + * .... > + * } > + * > + * free(info); > + * > + * Each of the enumerated engines, apart from being defined by its class and > + * instance (see `struct i915_engine_class_instance`), also can have flags and > + * capabilities defined as documented in i915_drm.h. > + * > + * For instance video engines which support HEVC encoding will have the > + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. > + * > + * Engine discovery only fully comes to its own when combined with the new way > + * of addressing engines when submitting batch buffers using contexts with > + * engine maps configured. > + */ > + > /** > * struct drm_i915_engine_info > * > -- > 2.30.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Document the Virtual Engine uAPI @ 2021-06-17 17:17 ` Daniel Vetter 0 siblings, 0 replies; 9+ messages in thread From: Daniel Vetter @ 2021-06-17 17:17 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Intel-gfx, dri-devel On Mon, Jun 14, 2021 at 10:09:59AM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A little bit of documentation covering the topics of engine discovery, > context engine maps and virtual engines. It is not very detailed but > supposed to be a starting point of giving a brief high level overview of > general principles and intended use cases. > > v2: > * Have the text in uapi header and link from there. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Daniel Vetter <daniel@ffwll.ch> What I meant was the kerneldoc directly as kerneldoc for the uapi structs, like Matt has done for e.g. drm_i915_gem_create_ext_memory_regions. But then I also realized that Matt hasn't set up the include for this, so it's not automatic at all yet :-/ -Daniel > --- > Documentation/gpu/i915.rst | 18 ++++ > include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ > 2 files changed, 206 insertions(+) > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index 42ce0196930a..00aa55bbe0fd 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that > refer to GPU-addresses so that the kernel can edit the buffer correctly. > This process is dubbed relocation. > > +Engine Discovery uAPI > +--------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Engine Discovery uAPI > + > +Context Engine Map uAPI > +----------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Context Engine Map uAPI > + > +Virtual Engine uAPI > +------------------- > + > +.. kernel-doc:: include/uapi/drm/i915_drm.h > + :doc: Virtual Engine uAPI > + > Locking Guidelines > ------------------ > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index a1cb4aa035a9..2f70c48567c0 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { > __u32 rsvd; > }; > > +/** > + * DOC: Virtual Engine uAPI > + * > + * Virtual engine is a concept where userspace is able to configure a set of > + * physical engines, submit a batch buffer, and let the driver execute it on any > + * engine from the set as it sees fit. > + * > + * This is primarily useful on parts which have multiple instances of a same > + * class engine, like for example GT3+ Skylake parts with their two VCS engines. > + * > + * For instance userspace can enumerate all engines of a certain class using the > + * previously described `Engine Discovery uAPI`_. After that userspace can > + * create a GEM context with a placeholder slot for the virtual engine (using > + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class > + * and instance respectively) and finally using the > + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in > + * the same reserved slot. > + * > + * Example of creating a virtual engine and submitting a batch buffer to it: > + * > + * .. code-block:: C > + * > + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { > + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, > + * .engine_index = 0, // Place this virtual engine into engine map slot 0 > + * .num_siblings = 2, > + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, > + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, > + * }; > + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { > + * .engines = { { I915_ENGINE_CLASS_INVALID, > + * I915_ENGINE_CLASS_INVALID_NONE } }, > + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension > + * }; > + * struct drm_i915_gem_context_create_ext_setparam p_engines = { > + * .base = { > + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, > + * }, > + * .param = { > + * .param = I915_CONTEXT_PARAM_ENGINES, > + * .value = to_user_pointer(&engines), > + * .size = sizeof(engines), > + * }, > + * }; > + * struct drm_i915_gem_context_create_ext create = { > + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, > + * .extensions = to_user_pointer(&p_engines); > + * }; > + * > + * ctx_id = gem_context_create_ext(drm_fd, &create); > + * > + * // Now we have created a GEM context with its engine map containing a > + * // single virtual engine. Submissions to this slot can go either to > + * // vcs0 or vcs1, depending on the load balancing algorithm used inside > + * // the driver. The load balancing is dynamic from one batch buffer to > + * // another and transparent to userspace. > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine > + * gem_execbuf(drm_fd, &execbuf); > + */ > + > /* > * i915_context_engines_load_balance: > * > @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { > struct i915_engine_class_instance engines[N__]; \ > } __attribute__((packed)) name__ > > +/** > + * DOC: Context Engine Map uAPI > + * > + * Context engine map is a new way of addressing engines when submitting batch- > + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` > + * inside the flags field of `struct drm_i915_gem_execbuffer2`. > + * > + * To use it created GEM contexts need to be configured with a list of engines > + * the user is intending to submit to. This is accomplished using the > + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct > + * i915_context_param_engines`. > + * > + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the > + * configured map. > + * > + * Example of creating such context and submitting against it: > + * > + * .. code-block:: C > + * > + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { > + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, > + * { I915_ENGINE_CLASS_COPY, 0 } } > + * }; > + * struct drm_i915_gem_context_create_ext_setparam p_engines = { > + * .base = { > + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, > + * }, > + * .param = { > + * .param = I915_CONTEXT_PARAM_ENGINES, > + * .value = to_user_pointer(&engines), > + * .size = sizeof(engines), > + * }, > + * }; > + * struct drm_i915_gem_context_create_ext create = { > + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, > + * .extensions = to_user_pointer(&p_engines); > + * }; > + * > + * ctx_id = gem_context_create_ext(drm_fd, &create); > + * > + * // We have now created a GEM context with two engines in the map: > + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines > + * // will not be accessible from this context. > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context > + * gem_execbuf(drm_fd, &execbuf); > + * > + * ... > + * execbuf.rsvd1 = ctx_id; > + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context > + * gem_execbuf(drm_fd, &execbuf); > + */ > + > struct i915_context_param_engines { > __u64 extensions; /* linked chain of extension blocks, 0 terminates */ > #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ > @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { > __u8 data[]; > }; > > +/** > + * DOC: Engine Discovery uAPI > + * > + * Engine discovery uAPI is a way of enumerating physical engines present in a > + * GPU associated with an open i915 DRM file descriptor. This supersedes the old > + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like > + * `I915_PARAM_HAS_BLT`. > + * > + * The need for this interface came starting with Icelake and newer GPUs, which > + * started to establish a pattern of having multiple engines of a same class, > + * where not all instances were always completely functionally equivalent. > + * > + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the > + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. > + * > + * Example for getting the list of engines: > + * > + * .. code-block:: C > + * > + * struct drm_i915_query_engine_info *info; > + * struct drm_i915_query_item item = { > + * .query_id = DRM_I915_QUERY_ENGINE_INFO; > + * }; > + * struct drm_i915_query query = { > + * .num_items = 1, > + * .items_ptr = (uintptr_t)&item, > + * }; > + * int err, i; > + * > + * // First query the size of the blob we need, this needs to be large > + * // enough to hold our array of engines. The kernel will fill out the > + * // item.length for us, which is the number of bytes we need. > + * // > + * // Alternatively a large buffer can be allocated straight away enabling > + * // querying in one pass, in which case item.length should contain the > + * // length of the provided buffer. > + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); > + * if (err) ... > + * > + * info = calloc(1, item.length); > + * // Now that we allocated the required number of bytes, we call the ioctl > + * // again, this time with the data_ptr pointing to our newly allocated > + * // blob, which the kernel can then populate with info on all engines. > + * item.data_ptr = (uintptr_t)&info, > + * > + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); > + * if (err) ... > + * > + * // We can now access each engine in the array > + * for (i = 0; i < info->num_engines; i++) { > + * struct drm_i915_engine_info einfo = info->engines[i]; > + * u16 class = einfo.engine.class; > + * u16 instance = einfo.engine.instance; > + * .... > + * } > + * > + * free(info); > + * > + * Each of the enumerated engines, apart from being defined by its class and > + * instance (see `struct i915_engine_class_instance`), also can have flags and > + * capabilities defined as documented in i915_drm.h. > + * > + * For instance video engines which support HEVC encoding will have the > + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. > + * > + * Engine discovery only fully comes to its own when combined with the new way > + * of addressing engines when submitting batch buffers using contexts with > + * engine maps configured. > + */ > + > /** > * struct drm_i915_engine_info > * > -- > 2.30.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: Document the Virtual Engine uAPI 2021-06-17 17:17 ` [Intel-gfx] " Daniel Vetter @ 2021-06-17 20:12 ` Tvrtko Ursulin -1 siblings, 0 replies; 9+ messages in thread From: Tvrtko Ursulin @ 2021-06-17 20:12 UTC (permalink / raw) To: Daniel Vetter; +Cc: Intel-gfx, dri-devel, Tvrtko Ursulin On 17/06/2021 18:17, Daniel Vetter wrote: > On Mon, Jun 14, 2021 at 10:09:59AM +0100, Tvrtko Ursulin wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> A little bit of documentation covering the topics of engine discovery, >> context engine maps and virtual engines. It is not very detailed but >> supposed to be a starting point of giving a brief high level overview of >> general principles and intended use cases. >> >> v2: >> * Have the text in uapi header and link from there. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Daniel Vetter <daniel@ffwll.ch> > > What I meant was the kerneldoc directly as kerneldoc for the uapi structs, > like Matt has done for e.g. drm_i915_gem_create_ext_memory_regions. Hm I wanted to add some commentary to give a high level picture of this area and not necessarily focus on uapi structs details. Some of them (at least one I think) already have their own documentation and the rest could be added in detail. But I do think a short "story" in the order of chapters I added to i915.rst makes sense as reading material. > But then I also realized that Matt hasn't set up the include for this, so > it's not automatic at all yet :-/ No idea what where how you mean. The fact i915_drm.h docs are not pulled in anywhere? Regards, Tvrtko > -Daniel > >> --- >> Documentation/gpu/i915.rst | 18 ++++ >> include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ >> 2 files changed, 206 insertions(+) >> >> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst >> index 42ce0196930a..00aa55bbe0fd 100644 >> --- a/Documentation/gpu/i915.rst >> +++ b/Documentation/gpu/i915.rst >> @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that >> refer to GPU-addresses so that the kernel can edit the buffer correctly. >> This process is dubbed relocation. >> >> +Engine Discovery uAPI >> +--------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Engine Discovery uAPI >> + >> +Context Engine Map uAPI >> +----------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Context Engine Map uAPI >> + >> +Virtual Engine uAPI >> +------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Virtual Engine uAPI >> + >> Locking Guidelines >> ------------------ >> >> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >> index a1cb4aa035a9..2f70c48567c0 100644 >> --- a/include/uapi/drm/i915_drm.h >> +++ b/include/uapi/drm/i915_drm.h >> @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { >> __u32 rsvd; >> }; >> >> +/** >> + * DOC: Virtual Engine uAPI >> + * >> + * Virtual engine is a concept where userspace is able to configure a set of >> + * physical engines, submit a batch buffer, and let the driver execute it on any >> + * engine from the set as it sees fit. >> + * >> + * This is primarily useful on parts which have multiple instances of a same >> + * class engine, like for example GT3+ Skylake parts with their two VCS engines. >> + * >> + * For instance userspace can enumerate all engines of a certain class using the >> + * previously described `Engine Discovery uAPI`_. After that userspace can >> + * create a GEM context with a placeholder slot for the virtual engine (using >> + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class >> + * and instance respectively) and finally using the >> + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in >> + * the same reserved slot. >> + * >> + * Example of creating a virtual engine and submitting a batch buffer to it: >> + * >> + * .. code-block:: C >> + * >> + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { >> + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, >> + * .engine_index = 0, // Place this virtual engine into engine map slot 0 >> + * .num_siblings = 2, >> + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, >> + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, >> + * }; >> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { >> + * .engines = { { I915_ENGINE_CLASS_INVALID, >> + * I915_ENGINE_CLASS_INVALID_NONE } }, >> + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension >> + * }; >> + * struct drm_i915_gem_context_create_ext_setparam p_engines = { >> + * .base = { >> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, >> + * }, >> + * .param = { >> + * .param = I915_CONTEXT_PARAM_ENGINES, >> + * .value = to_user_pointer(&engines), >> + * .size = sizeof(engines), >> + * }, >> + * }; >> + * struct drm_i915_gem_context_create_ext create = { >> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, >> + * .extensions = to_user_pointer(&p_engines); >> + * }; >> + * >> + * ctx_id = gem_context_create_ext(drm_fd, &create); >> + * >> + * // Now we have created a GEM context with its engine map containing a >> + * // single virtual engine. Submissions to this slot can go either to >> + * // vcs0 or vcs1, depending on the load balancing algorithm used inside >> + * // the driver. The load balancing is dynamic from one batch buffer to >> + * // another and transparent to userspace. >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine >> + * gem_execbuf(drm_fd, &execbuf); >> + */ >> + >> /* >> * i915_context_engines_load_balance: >> * >> @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { >> struct i915_engine_class_instance engines[N__]; \ >> } __attribute__((packed)) name__ >> >> +/** >> + * DOC: Context Engine Map uAPI >> + * >> + * Context engine map is a new way of addressing engines when submitting batch- >> + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` >> + * inside the flags field of `struct drm_i915_gem_execbuffer2`. >> + * >> + * To use it created GEM contexts need to be configured with a list of engines >> + * the user is intending to submit to. This is accomplished using the >> + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct >> + * i915_context_param_engines`. >> + * >> + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the >> + * configured map. >> + * >> + * Example of creating such context and submitting against it: >> + * >> + * .. code-block:: C >> + * >> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { >> + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, >> + * { I915_ENGINE_CLASS_COPY, 0 } } >> + * }; >> + * struct drm_i915_gem_context_create_ext_setparam p_engines = { >> + * .base = { >> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, >> + * }, >> + * .param = { >> + * .param = I915_CONTEXT_PARAM_ENGINES, >> + * .value = to_user_pointer(&engines), >> + * .size = sizeof(engines), >> + * }, >> + * }; >> + * struct drm_i915_gem_context_create_ext create = { >> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, >> + * .extensions = to_user_pointer(&p_engines); >> + * }; >> + * >> + * ctx_id = gem_context_create_ext(drm_fd, &create); >> + * >> + * // We have now created a GEM context with two engines in the map: >> + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines >> + * // will not be accessible from this context. >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context >> + * gem_execbuf(drm_fd, &execbuf); >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context >> + * gem_execbuf(drm_fd, &execbuf); >> + */ >> + >> struct i915_context_param_engines { >> __u64 extensions; /* linked chain of extension blocks, 0 terminates */ >> #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ >> @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { >> __u8 data[]; >> }; >> >> +/** >> + * DOC: Engine Discovery uAPI >> + * >> + * Engine discovery uAPI is a way of enumerating physical engines present in a >> + * GPU associated with an open i915 DRM file descriptor. This supersedes the old >> + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like >> + * `I915_PARAM_HAS_BLT`. >> + * >> + * The need for this interface came starting with Icelake and newer GPUs, which >> + * started to establish a pattern of having multiple engines of a same class, >> + * where not all instances were always completely functionally equivalent. >> + * >> + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the >> + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. >> + * >> + * Example for getting the list of engines: >> + * >> + * .. code-block:: C >> + * >> + * struct drm_i915_query_engine_info *info; >> + * struct drm_i915_query_item item = { >> + * .query_id = DRM_I915_QUERY_ENGINE_INFO; >> + * }; >> + * struct drm_i915_query query = { >> + * .num_items = 1, >> + * .items_ptr = (uintptr_t)&item, >> + * }; >> + * int err, i; >> + * >> + * // First query the size of the blob we need, this needs to be large >> + * // enough to hold our array of engines. The kernel will fill out the >> + * // item.length for us, which is the number of bytes we need. >> + * // >> + * // Alternatively a large buffer can be allocated straight away enabling >> + * // querying in one pass, in which case item.length should contain the >> + * // length of the provided buffer. >> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); >> + * if (err) ... >> + * >> + * info = calloc(1, item.length); >> + * // Now that we allocated the required number of bytes, we call the ioctl >> + * // again, this time with the data_ptr pointing to our newly allocated >> + * // blob, which the kernel can then populate with info on all engines. >> + * item.data_ptr = (uintptr_t)&info, >> + * >> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); >> + * if (err) ... >> + * >> + * // We can now access each engine in the array >> + * for (i = 0; i < info->num_engines; i++) { >> + * struct drm_i915_engine_info einfo = info->engines[i]; >> + * u16 class = einfo.engine.class; >> + * u16 instance = einfo.engine.instance; >> + * .... >> + * } >> + * >> + * free(info); >> + * >> + * Each of the enumerated engines, apart from being defined by its class and >> + * instance (see `struct i915_engine_class_instance`), also can have flags and >> + * capabilities defined as documented in i915_drm.h. >> + * >> + * For instance video engines which support HEVC encoding will have the >> + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. >> + * >> + * Engine discovery only fully comes to its own when combined with the new way >> + * of addressing engines when submitting batch buffers using contexts with >> + * engine maps configured. >> + */ >> + >> /** >> * struct drm_i915_engine_info >> * >> -- >> 2.30.2 >> > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Document the Virtual Engine uAPI @ 2021-06-17 20:12 ` Tvrtko Ursulin 0 siblings, 0 replies; 9+ messages in thread From: Tvrtko Ursulin @ 2021-06-17 20:12 UTC (permalink / raw) To: Daniel Vetter; +Cc: Intel-gfx, dri-devel On 17/06/2021 18:17, Daniel Vetter wrote: > On Mon, Jun 14, 2021 at 10:09:59AM +0100, Tvrtko Ursulin wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> A little bit of documentation covering the topics of engine discovery, >> context engine maps and virtual engines. It is not very detailed but >> supposed to be a starting point of giving a brief high level overview of >> general principles and intended use cases. >> >> v2: >> * Have the text in uapi header and link from there. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Daniel Vetter <daniel@ffwll.ch> > > What I meant was the kerneldoc directly as kerneldoc for the uapi structs, > like Matt has done for e.g. drm_i915_gem_create_ext_memory_regions. Hm I wanted to add some commentary to give a high level picture of this area and not necessarily focus on uapi structs details. Some of them (at least one I think) already have their own documentation and the rest could be added in detail. But I do think a short "story" in the order of chapters I added to i915.rst makes sense as reading material. > But then I also realized that Matt hasn't set up the include for this, so > it's not automatic at all yet :-/ No idea what where how you mean. The fact i915_drm.h docs are not pulled in anywhere? Regards, Tvrtko > -Daniel > >> --- >> Documentation/gpu/i915.rst | 18 ++++ >> include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++++++++ >> 2 files changed, 206 insertions(+) >> >> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst >> index 42ce0196930a..00aa55bbe0fd 100644 >> --- a/Documentation/gpu/i915.rst >> +++ b/Documentation/gpu/i915.rst >> @@ -335,6 +335,24 @@ for execution also include a list of all locations within buffers that >> refer to GPU-addresses so that the kernel can edit the buffer correctly. >> This process is dubbed relocation. >> >> +Engine Discovery uAPI >> +--------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Engine Discovery uAPI >> + >> +Context Engine Map uAPI >> +----------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Context Engine Map uAPI >> + >> +Virtual Engine uAPI >> +------------------- >> + >> +.. kernel-doc:: include/uapi/drm/i915_drm.h >> + :doc: Virtual Engine uAPI >> + >> Locking Guidelines >> ------------------ >> >> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >> index a1cb4aa035a9..2f70c48567c0 100644 >> --- a/include/uapi/drm/i915_drm.h >> +++ b/include/uapi/drm/i915_drm.h >> @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu { >> __u32 rsvd; >> }; >> >> +/** >> + * DOC: Virtual Engine uAPI >> + * >> + * Virtual engine is a concept where userspace is able to configure a set of >> + * physical engines, submit a batch buffer, and let the driver execute it on any >> + * engine from the set as it sees fit. >> + * >> + * This is primarily useful on parts which have multiple instances of a same >> + * class engine, like for example GT3+ Skylake parts with their two VCS engines. >> + * >> + * For instance userspace can enumerate all engines of a certain class using the >> + * previously described `Engine Discovery uAPI`_. After that userspace can >> + * create a GEM context with a placeholder slot for the virtual engine (using >> + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class >> + * and instance respectively) and finally using the >> + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in >> + * the same reserved slot. >> + * >> + * Example of creating a virtual engine and submitting a batch buffer to it: >> + * >> + * .. code-block:: C >> + * >> + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = { >> + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE, >> + * .engine_index = 0, // Place this virtual engine into engine map slot 0 >> + * .num_siblings = 2, >> + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 }, >> + * { I915_ENGINE_CLASS_VIDEO, 1 }, }, >> + * }; >> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = { >> + * .engines = { { I915_ENGINE_CLASS_INVALID, >> + * I915_ENGINE_CLASS_INVALID_NONE } }, >> + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension >> + * }; >> + * struct drm_i915_gem_context_create_ext_setparam p_engines = { >> + * .base = { >> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, >> + * }, >> + * .param = { >> + * .param = I915_CONTEXT_PARAM_ENGINES, >> + * .value = to_user_pointer(&engines), >> + * .size = sizeof(engines), >> + * }, >> + * }; >> + * struct drm_i915_gem_context_create_ext create = { >> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, >> + * .extensions = to_user_pointer(&p_engines); >> + * }; >> + * >> + * ctx_id = gem_context_create_ext(drm_fd, &create); >> + * >> + * // Now we have created a GEM context with its engine map containing a >> + * // single virtual engine. Submissions to this slot can go either to >> + * // vcs0 or vcs1, depending on the load balancing algorithm used inside >> + * // the driver. The load balancing is dynamic from one batch buffer to >> + * // another and transparent to userspace. >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine >> + * gem_execbuf(drm_fd, &execbuf); >> + */ >> + >> /* >> * i915_context_engines_load_balance: >> * >> @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond { >> struct i915_engine_class_instance engines[N__]; \ >> } __attribute__((packed)) name__ >> >> +/** >> + * DOC: Context Engine Map uAPI >> + * >> + * Context engine map is a new way of addressing engines when submitting batch- >> + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT` >> + * inside the flags field of `struct drm_i915_gem_execbuffer2`. >> + * >> + * To use it created GEM contexts need to be configured with a list of engines >> + * the user is intending to submit to. This is accomplished using the >> + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct >> + * i915_context_param_engines`. >> + * >> + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the >> + * configured map. >> + * >> + * Example of creating such context and submitting against it: >> + * >> + * .. code-block:: C >> + * >> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = { >> + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 }, >> + * { I915_ENGINE_CLASS_COPY, 0 } } >> + * }; >> + * struct drm_i915_gem_context_create_ext_setparam p_engines = { >> + * .base = { >> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM, >> + * }, >> + * .param = { >> + * .param = I915_CONTEXT_PARAM_ENGINES, >> + * .value = to_user_pointer(&engines), >> + * .size = sizeof(engines), >> + * }, >> + * }; >> + * struct drm_i915_gem_context_create_ext create = { >> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS, >> + * .extensions = to_user_pointer(&p_engines); >> + * }; >> + * >> + * ctx_id = gem_context_create_ext(drm_fd, &create); >> + * >> + * // We have now created a GEM context with two engines in the map: >> + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines >> + * // will not be accessible from this context. >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context >> + * gem_execbuf(drm_fd, &execbuf); >> + * >> + * ... >> + * execbuf.rsvd1 = ctx_id; >> + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context >> + * gem_execbuf(drm_fd, &execbuf); >> + */ >> + >> struct i915_context_param_engines { >> __u64 extensions; /* linked chain of extension blocks, 0 terminates */ >> #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */ >> @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info { >> __u8 data[]; >> }; >> >> +/** >> + * DOC: Engine Discovery uAPI >> + * >> + * Engine discovery uAPI is a way of enumerating physical engines present in a >> + * GPU associated with an open i915 DRM file descriptor. This supersedes the old >> + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like >> + * `I915_PARAM_HAS_BLT`. >> + * >> + * The need for this interface came starting with Icelake and newer GPUs, which >> + * started to establish a pattern of having multiple engines of a same class, >> + * where not all instances were always completely functionally equivalent. >> + * >> + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the >> + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id. >> + * >> + * Example for getting the list of engines: >> + * >> + * .. code-block:: C >> + * >> + * struct drm_i915_query_engine_info *info; >> + * struct drm_i915_query_item item = { >> + * .query_id = DRM_I915_QUERY_ENGINE_INFO; >> + * }; >> + * struct drm_i915_query query = { >> + * .num_items = 1, >> + * .items_ptr = (uintptr_t)&item, >> + * }; >> + * int err, i; >> + * >> + * // First query the size of the blob we need, this needs to be large >> + * // enough to hold our array of engines. The kernel will fill out the >> + * // item.length for us, which is the number of bytes we need. >> + * // >> + * // Alternatively a large buffer can be allocated straight away enabling >> + * // querying in one pass, in which case item.length should contain the >> + * // length of the provided buffer. >> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); >> + * if (err) ... >> + * >> + * info = calloc(1, item.length); >> + * // Now that we allocated the required number of bytes, we call the ioctl >> + * // again, this time with the data_ptr pointing to our newly allocated >> + * // blob, which the kernel can then populate with info on all engines. >> + * item.data_ptr = (uintptr_t)&info, >> + * >> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query); >> + * if (err) ... >> + * >> + * // We can now access each engine in the array >> + * for (i = 0; i < info->num_engines; i++) { >> + * struct drm_i915_engine_info einfo = info->engines[i]; >> + * u16 class = einfo.engine.class; >> + * u16 instance = einfo.engine.instance; >> + * .... >> + * } >> + * >> + * free(info); >> + * >> + * Each of the enumerated engines, apart from being defined by its class and >> + * instance (see `struct i915_engine_class_instance`), also can have flags and >> + * capabilities defined as documented in i915_drm.h. >> + * >> + * For instance video engines which support HEVC encoding will have the >> + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set. >> + * >> + * Engine discovery only fully comes to its own when combined with the new way >> + * of addressing engines when submitting batch buffers using contexts with >> + * engine maps configured. >> + */ >> + >> /** >> * struct drm_i915_engine_info >> * >> -- >> 2.30.2 >> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-17 20:13 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-14 9:09 [PATCH v2] drm/i915: Document the Virtual Engine uAPI Tvrtko Ursulin 2021-06-14 9:09 ` [Intel-gfx] " Tvrtko Ursulin 2021-06-14 13:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Document the Virtual Engine uAPI (rev2) Patchwork 2021-06-14 14:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-06-14 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-06-17 17:17 ` [PATCH v2] drm/i915: Document the Virtual Engine uAPI Daniel Vetter 2021-06-17 17:17 ` [Intel-gfx] " Daniel Vetter 2021-06-17 20:12 ` Tvrtko Ursulin 2021-06-17 20:12 ` [Intel-gfx] " Tvrtko Ursulin
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