* [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA architecture is updated, and doesn't support slew rate
calibration anymore on 7nm or advanced process, add a new version
number to support it.
Due to the FreqMeter bank is not used but reserved, it's backward
with v2 until now.
For mt8195, no function changes when use generic v2 or v3 compatible,
but prefer to use v3's compatible, it will not waste the time to
calibrate the slew rate, and also correspond with hardware version.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: add more commit log suggested by Rob
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b8a7651a3d9a..939c09296b5f 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -15,7 +15,7 @@ description: |
controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
- T-PHY V2 (mt2712) when works on USB mode:
+ T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
-----------------------------------
Version 1:
port offset bank
@@ -34,7 +34,7 @@ description: |
u2 port2 0x1800 U2PHY_COM
...
- Version 2:
+ Version 2/3:
port offset bank
u2 port0 0x0000 MISC
0x0100 FMREG
@@ -59,7 +59,8 @@ description: |
SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
- added on V2.
+ added on V2; the FMREG bank for slew rate calibration is not used anymore
+ and reserved on V3;
properties:
$nodename:
@@ -79,8 +80,11 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
- - mediatek,mt8195-tphy
- const: mediatek,generic-tphy-v2
+ - items:
+ - enum:
+ - mediatek,mt8195-tphy
+ - const: mediatek,generic-tphy-v3
- const: mediatek,mt2701-u3phy
deprecated: true
- const: mediatek,mt2712-u3phy
@@ -91,7 +95,7 @@ properties:
description:
Register shared by multiple ports, exclude port's private register.
It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
- T-PHY V2, such as mt2712.
+ T-PHY V2/V3, such as mt2712.
maxItems: 1
"#address-cells":
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA architecture is updated, and doesn't support slew rate
calibration anymore on 7nm or advanced process, add a new version
number to support it.
Due to the FreqMeter bank is not used but reserved, it's backward
with v2 until now.
For mt8195, no function changes when use generic v2 or v3 compatible,
but prefer to use v3's compatible, it will not waste the time to
calibrate the slew rate, and also correspond with hardware version.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: add more commit log suggested by Rob
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b8a7651a3d9a..939c09296b5f 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -15,7 +15,7 @@ description: |
controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
- T-PHY V2 (mt2712) when works on USB mode:
+ T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
-----------------------------------
Version 1:
port offset bank
@@ -34,7 +34,7 @@ description: |
u2 port2 0x1800 U2PHY_COM
...
- Version 2:
+ Version 2/3:
port offset bank
u2 port0 0x0000 MISC
0x0100 FMREG
@@ -59,7 +59,8 @@ description: |
SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
- added on V2.
+ added on V2; the FMREG bank for slew rate calibration is not used anymore
+ and reserved on V3;
properties:
$nodename:
@@ -79,8 +80,11 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
- - mediatek,mt8195-tphy
- const: mediatek,generic-tphy-v2
+ - items:
+ - enum:
+ - mediatek,mt8195-tphy
+ - const: mediatek,generic-tphy-v3
- const: mediatek,mt2701-u3phy
deprecated: true
- const: mediatek,mt2712-u3phy
@@ -91,7 +95,7 @@ properties:
description:
Register shared by multiple ports, exclude port's private register.
It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
- T-PHY V2, such as mt2712.
+ T-PHY V2/V3, such as mt2712.
maxItems: 1
"#address-cells":
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA architecture is updated, and doesn't support slew rate
calibration anymore on 7nm or advanced process, add a new version
number to support it.
Due to the FreqMeter bank is not used but reserved, it's backward
with v2 until now.
For mt8195, no function changes when use generic v2 or v3 compatible,
but prefer to use v3's compatible, it will not waste the time to
calibrate the slew rate, and also correspond with hardware version.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: add more commit log suggested by Rob
---
.../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b8a7651a3d9a..939c09296b5f 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -15,7 +15,7 @@ description: |
controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
- T-PHY V2 (mt2712) when works on USB mode:
+ T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
-----------------------------------
Version 1:
port offset bank
@@ -34,7 +34,7 @@ description: |
u2 port2 0x1800 U2PHY_COM
...
- Version 2:
+ Version 2/3:
port offset bank
u2 port0 0x0000 MISC
0x0100 FMREG
@@ -59,7 +59,8 @@ description: |
SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
- added on V2.
+ added on V2; the FMREG bank for slew rate calibration is not used anymore
+ and reserved on V3;
properties:
$nodename:
@@ -79,8 +80,11 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
- - mediatek,mt8195-tphy
- const: mediatek,generic-tphy-v2
+ - items:
+ - enum:
+ - mediatek,mt8195-tphy
+ - const: mediatek,generic-tphy-v3
- const: mediatek,mt2701-u3phy
deprecated: true
- const: mediatek,mt2712-u3phy
@@ -91,7 +95,7 @@ properties:
description:
Register shared by multiple ports, exclude port's private register.
It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
- T-PHY V2, such as mt2712.
+ T-PHY V2/V3, such as mt2712.
maxItems: 1
"#address-cells":
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/3] phy: phy-mtk-tphy: support new hardware version
2021-06-19 2:47 ` Chunfeng Yun
(?)
(?)
@ 2021-06-19 2:47 ` Chunfeng Yun
-1 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA arch is updated, and doesn't support slew rate calibrate
anymore on 7nm or advanced process, add a new version number to
support it.
Note: the FreqMeter bank is not used but reserved.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 40 +++++++++++++++++++++--------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 731c483a04de..42a1174da6cc 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -27,7 +27,8 @@
#define SSUSB_SIFSLV_V1_U3PHYD 0x000
#define SSUSB_SIFSLV_V1_U3PHYA 0x200
-/* version V2 sub-banks offset base address */
+/* version V2/V3 sub-banks offset base address */
+/* V3: U2FREQ is not used anymore, but reserved */
/* u2 phy banks */
#define SSUSB_SIFSLV_V2_MISC 0x000
#define SSUSB_SIFSLV_V2_U2FREQ 0x100
@@ -270,6 +271,7 @@
enum mtk_phy_version {
MTK_PHY_V1 = 1,
MTK_PHY_V2,
+ MTK_PHY_V3,
};
struct mtk_phy_pdata {
@@ -330,6 +332,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
int fm_out;
u32 tmp;
+ /* HW V3 doesn't support slew rate cal anymore */
+ if (tphy->pdata->version == MTK_PHY_V3)
+ return;
+
/* use force value */
if (instance->eye_src)
return;
@@ -878,7 +884,7 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
writel(tmp, com + U3P_U2PHYBC12C);
}
- if (instance->eye_src) {
+ if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {
tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
@@ -1042,11 +1048,15 @@ static struct phy *mtk_phy_xlate(struct device *dev,
return ERR_PTR(-EINVAL);
}
- if (tphy->pdata->version == MTK_PHY_V1) {
+ switch (tphy->pdata->version) {
+ case MTK_PHY_V1:
phy_v1_banks_init(tphy, instance);
- } else if (tphy->pdata->version == MTK_PHY_V2) {
+ break;
+ case MTK_PHY_V2:
+ case MTK_PHY_V3:
phy_v2_banks_init(tphy, instance);
- } else {
+ break;
+ default:
dev_err(dev, "phy version is not supported\n");
return ERR_PTR(-EINVAL);
}
@@ -1075,6 +1085,10 @@ static const struct mtk_phy_pdata tphy_v2_pdata = {
.version = MTK_PHY_V2,
};
+static const struct mtk_phy_pdata tphy_v3_pdata = {
+ .version = MTK_PHY_V3,
+};
+
static const struct mtk_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
.version = MTK_PHY_V1,
@@ -1086,6 +1100,7 @@ static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
+ { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
@@ -1129,12 +1144,15 @@ static int mtk_tphy_probe(struct platform_device *pdev)
}
}
- tphy->src_ref_clk = U3P_REF_CLK;
- tphy->src_coef = U3P_SLEW_RATE_COEF;
- /* update parameters of slew rate calibrate if exist */
- device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
- &tphy->src_ref_clk);
- device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+ if (tphy->pdata->version < MTK_PHY_V3) {
+ tphy->src_ref_clk = U3P_REF_CLK;
+ tphy->src_coef = U3P_SLEW_RATE_COEF;
+ /* update parameters of slew rate calibrate if exist */
+ device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+ &tphy->src_ref_clk);
+ device_property_read_u32(dev, "mediatek,src-coef",
+ &tphy->src_coef);
+ }
port = 0;
for_each_child_of_node(np, child_np) {
--
2.18.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/3] phy: phy-mtk-tphy: support new hardware version
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA arch is updated, and doesn't support slew rate calibrate
anymore on 7nm or advanced process, add a new version number to
support it.
Note: the FreqMeter bank is not used but reserved.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 40 +++++++++++++++++++++--------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 731c483a04de..42a1174da6cc 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -27,7 +27,8 @@
#define SSUSB_SIFSLV_V1_U3PHYD 0x000
#define SSUSB_SIFSLV_V1_U3PHYA 0x200
-/* version V2 sub-banks offset base address */
+/* version V2/V3 sub-banks offset base address */
+/* V3: U2FREQ is not used anymore, but reserved */
/* u2 phy banks */
#define SSUSB_SIFSLV_V2_MISC 0x000
#define SSUSB_SIFSLV_V2_U2FREQ 0x100
@@ -270,6 +271,7 @@
enum mtk_phy_version {
MTK_PHY_V1 = 1,
MTK_PHY_V2,
+ MTK_PHY_V3,
};
struct mtk_phy_pdata {
@@ -330,6 +332,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
int fm_out;
u32 tmp;
+ /* HW V3 doesn't support slew rate cal anymore */
+ if (tphy->pdata->version == MTK_PHY_V3)
+ return;
+
/* use force value */
if (instance->eye_src)
return;
@@ -878,7 +884,7 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
writel(tmp, com + U3P_U2PHYBC12C);
}
- if (instance->eye_src) {
+ if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {
tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
@@ -1042,11 +1048,15 @@ static struct phy *mtk_phy_xlate(struct device *dev,
return ERR_PTR(-EINVAL);
}
- if (tphy->pdata->version == MTK_PHY_V1) {
+ switch (tphy->pdata->version) {
+ case MTK_PHY_V1:
phy_v1_banks_init(tphy, instance);
- } else if (tphy->pdata->version == MTK_PHY_V2) {
+ break;
+ case MTK_PHY_V2:
+ case MTK_PHY_V3:
phy_v2_banks_init(tphy, instance);
- } else {
+ break;
+ default:
dev_err(dev, "phy version is not supported\n");
return ERR_PTR(-EINVAL);
}
@@ -1075,6 +1085,10 @@ static const struct mtk_phy_pdata tphy_v2_pdata = {
.version = MTK_PHY_V2,
};
+static const struct mtk_phy_pdata tphy_v3_pdata = {
+ .version = MTK_PHY_V3,
+};
+
static const struct mtk_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
.version = MTK_PHY_V1,
@@ -1086,6 +1100,7 @@ static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
+ { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
@@ -1129,12 +1144,15 @@ static int mtk_tphy_probe(struct platform_device *pdev)
}
}
- tphy->src_ref_clk = U3P_REF_CLK;
- tphy->src_coef = U3P_SLEW_RATE_COEF;
- /* update parameters of slew rate calibrate if exist */
- device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
- &tphy->src_ref_clk);
- device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+ if (tphy->pdata->version < MTK_PHY_V3) {
+ tphy->src_ref_clk = U3P_REF_CLK;
+ tphy->src_coef = U3P_SLEW_RATE_COEF;
+ /* update parameters of slew rate calibrate if exist */
+ device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+ &tphy->src_ref_clk);
+ device_property_read_u32(dev, "mediatek,src-coef",
+ &tphy->src_coef);
+ }
port = 0;
for_each_child_of_node(np, child_np) {
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/3] phy: phy-mtk-tphy: support new hardware version
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA arch is updated, and doesn't support slew rate calibrate
anymore on 7nm or advanced process, add a new version number to
support it.
Note: the FreqMeter bank is not used but reserved.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 40 +++++++++++++++++++++--------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 731c483a04de..42a1174da6cc 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -27,7 +27,8 @@
#define SSUSB_SIFSLV_V1_U3PHYD 0x000
#define SSUSB_SIFSLV_V1_U3PHYA 0x200
-/* version V2 sub-banks offset base address */
+/* version V2/V3 sub-banks offset base address */
+/* V3: U2FREQ is not used anymore, but reserved */
/* u2 phy banks */
#define SSUSB_SIFSLV_V2_MISC 0x000
#define SSUSB_SIFSLV_V2_U2FREQ 0x100
@@ -270,6 +271,7 @@
enum mtk_phy_version {
MTK_PHY_V1 = 1,
MTK_PHY_V2,
+ MTK_PHY_V3,
};
struct mtk_phy_pdata {
@@ -330,6 +332,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
int fm_out;
u32 tmp;
+ /* HW V3 doesn't support slew rate cal anymore */
+ if (tphy->pdata->version == MTK_PHY_V3)
+ return;
+
/* use force value */
if (instance->eye_src)
return;
@@ -878,7 +884,7 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
writel(tmp, com + U3P_U2PHYBC12C);
}
- if (instance->eye_src) {
+ if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {
tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
@@ -1042,11 +1048,15 @@ static struct phy *mtk_phy_xlate(struct device *dev,
return ERR_PTR(-EINVAL);
}
- if (tphy->pdata->version == MTK_PHY_V1) {
+ switch (tphy->pdata->version) {
+ case MTK_PHY_V1:
phy_v1_banks_init(tphy, instance);
- } else if (tphy->pdata->version == MTK_PHY_V2) {
+ break;
+ case MTK_PHY_V2:
+ case MTK_PHY_V3:
phy_v2_banks_init(tphy, instance);
- } else {
+ break;
+ default:
dev_err(dev, "phy version is not supported\n");
return ERR_PTR(-EINVAL);
}
@@ -1075,6 +1085,10 @@ static const struct mtk_phy_pdata tphy_v2_pdata = {
.version = MTK_PHY_V2,
};
+static const struct mtk_phy_pdata tphy_v3_pdata = {
+ .version = MTK_PHY_V3,
+};
+
static const struct mtk_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
.version = MTK_PHY_V1,
@@ -1086,6 +1100,7 @@ static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
+ { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
@@ -1129,12 +1144,15 @@ static int mtk_tphy_probe(struct platform_device *pdev)
}
}
- tphy->src_ref_clk = U3P_REF_CLK;
- tphy->src_coef = U3P_SLEW_RATE_COEF;
- /* update parameters of slew rate calibrate if exist */
- device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
- &tphy->src_ref_clk);
- device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+ if (tphy->pdata->version < MTK_PHY_V3) {
+ tphy->src_ref_clk = U3P_REF_CLK;
+ tphy->src_coef = U3P_SLEW_RATE_COEF;
+ /* update parameters of slew rate calibrate if exist */
+ device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+ &tphy->src_ref_clk);
+ device_property_read_u32(dev, "mediatek,src-coef",
+ &tphy->src_coef);
+ }
port = 0;
for_each_child_of_node(np, child_np) {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/3] phy: phy-mtk-tphy: support new hardware version
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The PHYA arch is updated, and doesn't support slew rate calibrate
anymore on 7nm or advanced process, add a new version number to
support it.
Note: the FreqMeter bank is not used but reserved.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 40 +++++++++++++++++++++--------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 731c483a04de..42a1174da6cc 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -27,7 +27,8 @@
#define SSUSB_SIFSLV_V1_U3PHYD 0x000
#define SSUSB_SIFSLV_V1_U3PHYA 0x200
-/* version V2 sub-banks offset base address */
+/* version V2/V3 sub-banks offset base address */
+/* V3: U2FREQ is not used anymore, but reserved */
/* u2 phy banks */
#define SSUSB_SIFSLV_V2_MISC 0x000
#define SSUSB_SIFSLV_V2_U2FREQ 0x100
@@ -270,6 +271,7 @@
enum mtk_phy_version {
MTK_PHY_V1 = 1,
MTK_PHY_V2,
+ MTK_PHY_V3,
};
struct mtk_phy_pdata {
@@ -330,6 +332,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
int fm_out;
u32 tmp;
+ /* HW V3 doesn't support slew rate cal anymore */
+ if (tphy->pdata->version == MTK_PHY_V3)
+ return;
+
/* use force value */
if (instance->eye_src)
return;
@@ -878,7 +884,7 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
writel(tmp, com + U3P_U2PHYBC12C);
}
- if (instance->eye_src) {
+ if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {
tmp = readl(com + U3P_USBPHYACR5);
tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
@@ -1042,11 +1048,15 @@ static struct phy *mtk_phy_xlate(struct device *dev,
return ERR_PTR(-EINVAL);
}
- if (tphy->pdata->version == MTK_PHY_V1) {
+ switch (tphy->pdata->version) {
+ case MTK_PHY_V1:
phy_v1_banks_init(tphy, instance);
- } else if (tphy->pdata->version == MTK_PHY_V2) {
+ break;
+ case MTK_PHY_V2:
+ case MTK_PHY_V3:
phy_v2_banks_init(tphy, instance);
- } else {
+ break;
+ default:
dev_err(dev, "phy version is not supported\n");
return ERR_PTR(-EINVAL);
}
@@ -1075,6 +1085,10 @@ static const struct mtk_phy_pdata tphy_v2_pdata = {
.version = MTK_PHY_V2,
};
+static const struct mtk_phy_pdata tphy_v3_pdata = {
+ .version = MTK_PHY_V3,
+};
+
static const struct mtk_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
.version = MTK_PHY_V1,
@@ -1086,6 +1100,7 @@ static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
+ { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
{ },
};
MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
@@ -1129,12 +1144,15 @@ static int mtk_tphy_probe(struct platform_device *pdev)
}
}
- tphy->src_ref_clk = U3P_REF_CLK;
- tphy->src_coef = U3P_SLEW_RATE_COEF;
- /* update parameters of slew rate calibrate if exist */
- device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
- &tphy->src_ref_clk);
- device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+ if (tphy->pdata->version < MTK_PHY_V3) {
+ tphy->src_ref_clk = U3P_REF_CLK;
+ tphy->src_coef = U3P_SLEW_RATE_COEF;
+ /* update parameters of slew rate calibrate if exist */
+ device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+ &tphy->src_ref_clk);
+ device_property_read_u32(dev, "mediatek,src-coef",
+ &tphy->src_coef);
+ }
port = 0;
for_each_child_of_node(np, child_np) {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/3] phy: phy-mtk-tphy: add support mt8195
2021-06-19 2:47 ` Chunfeng Yun
(?)
(?)
@ 2021-06-19 2:47 ` Chunfeng Yun
-1 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: noc changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 52 +++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 42a1174da6cc..c3dc1763a7eb 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -41,6 +41,8 @@
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
+#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
+#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004
@@ -52,6 +54,8 @@
#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define U3P_USBPHYACR2 0x008
+#define PA2_RG_U2PLL_BW GENMASK(21, 19)
+#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
#define U3P_USBPHYACR5 0x014
@@ -73,6 +77,14 @@
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
+#define U3P_U2PHYA_RESV 0x030
+#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b
+#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000
+
+#define U3P_U2PHYA_RESV1 0x044
+#define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
+#define P2R_RG_U2PLL_FRA_EN BIT(3)
+
#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
@@ -277,6 +289,12 @@ enum mtk_phy_version {
struct mtk_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ /*
+ * u2phy should use integer mode instead of fractional mode of
+ * 48M PLL, fix it by switching PLL to 26M from default 48M
+ * for mt8195
+ */
+ bool sw_pll_48m_to_26m;
enum mtk_phy_version version;
};
@@ -456,6 +474,33 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
+static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
+ u32 tmp;
+
+ if (!tphy->pdata->sw_pll_48m_to_26m)
+ return;
+
+ tmp = readl(com + U3P_USBPHYACR0);
+ tmp &= ~PA0_USB20_PLL_PREDIV;
+ tmp |= PA0_USB20_PLL_PREDIV_VAL(0);
+ writel(tmp, com + U3P_USBPHYACR0);
+
+ tmp = readl(com + U3P_USBPHYACR2);
+ tmp &= ~PA2_RG_U2PLL_BW;
+ tmp |= PA2_RG_U2PLL_BW_VAL(3);
+ writel(tmp, com + U3P_USBPHYACR2);
+
+ writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
+
+ tmp = readl(com + U3P_U2PHYA_RESV1);
+ tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL;
+ writel(tmp, com + U3P_U2PHYA_RESV1);
+}
+
static void u2_phy_instance_init(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
@@ -941,6 +986,7 @@ static int mtk_phy_init(struct phy *phy)
switch (instance->type) {
case PHY_TYPE_USB2:
+ u2_phy_pll_26m_set(tphy, instance);
u2_phy_instance_init(tphy, instance);
u2_phy_props_set(tphy, instance);
break;
@@ -1094,10 +1140,16 @@ static const struct mtk_phy_pdata mt8173_pdata = {
.version = MTK_PHY_V1,
};
+static const struct mtk_phy_pdata mt8195_pdata = {
+ .sw_pll_48m_to_26m = true,
+ .version = MTK_PHY_V3,
+};
+
static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
+ { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
--
2.18.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/3] phy: phy-mtk-tphy: add support mt8195
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: noc changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 52 +++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 42a1174da6cc..c3dc1763a7eb 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -41,6 +41,8 @@
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
+#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
+#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004
@@ -52,6 +54,8 @@
#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define U3P_USBPHYACR2 0x008
+#define PA2_RG_U2PLL_BW GENMASK(21, 19)
+#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
#define U3P_USBPHYACR5 0x014
@@ -73,6 +77,14 @@
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
+#define U3P_U2PHYA_RESV 0x030
+#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b
+#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000
+
+#define U3P_U2PHYA_RESV1 0x044
+#define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
+#define P2R_RG_U2PLL_FRA_EN BIT(3)
+
#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
@@ -277,6 +289,12 @@ enum mtk_phy_version {
struct mtk_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ /*
+ * u2phy should use integer mode instead of fractional mode of
+ * 48M PLL, fix it by switching PLL to 26M from default 48M
+ * for mt8195
+ */
+ bool sw_pll_48m_to_26m;
enum mtk_phy_version version;
};
@@ -456,6 +474,33 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
+static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
+ u32 tmp;
+
+ if (!tphy->pdata->sw_pll_48m_to_26m)
+ return;
+
+ tmp = readl(com + U3P_USBPHYACR0);
+ tmp &= ~PA0_USB20_PLL_PREDIV;
+ tmp |= PA0_USB20_PLL_PREDIV_VAL(0);
+ writel(tmp, com + U3P_USBPHYACR0);
+
+ tmp = readl(com + U3P_USBPHYACR2);
+ tmp &= ~PA2_RG_U2PLL_BW;
+ tmp |= PA2_RG_U2PLL_BW_VAL(3);
+ writel(tmp, com + U3P_USBPHYACR2);
+
+ writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
+
+ tmp = readl(com + U3P_U2PHYA_RESV1);
+ tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL;
+ writel(tmp, com + U3P_U2PHYA_RESV1);
+}
+
static void u2_phy_instance_init(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
@@ -941,6 +986,7 @@ static int mtk_phy_init(struct phy *phy)
switch (instance->type) {
case PHY_TYPE_USB2:
+ u2_phy_pll_26m_set(tphy, instance);
u2_phy_instance_init(tphy, instance);
u2_phy_props_set(tphy, instance);
break;
@@ -1094,10 +1140,16 @@ static const struct mtk_phy_pdata mt8173_pdata = {
.version = MTK_PHY_V1,
};
+static const struct mtk_phy_pdata mt8195_pdata = {
+ .sw_pll_48m_to_26m = true,
+ .version = MTK_PHY_V3,
+};
+
static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
+ { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
--
2.18.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/3] phy: phy-mtk-tphy: add support mt8195
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: noc changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 52 +++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 42a1174da6cc..c3dc1763a7eb 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -41,6 +41,8 @@
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
+#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
+#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004
@@ -52,6 +54,8 @@
#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define U3P_USBPHYACR2 0x008
+#define PA2_RG_U2PLL_BW GENMASK(21, 19)
+#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
#define U3P_USBPHYACR5 0x014
@@ -73,6 +77,14 @@
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
+#define U3P_U2PHYA_RESV 0x030
+#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b
+#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000
+
+#define U3P_U2PHYA_RESV1 0x044
+#define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
+#define P2R_RG_U2PLL_FRA_EN BIT(3)
+
#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
@@ -277,6 +289,12 @@ enum mtk_phy_version {
struct mtk_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ /*
+ * u2phy should use integer mode instead of fractional mode of
+ * 48M PLL, fix it by switching PLL to 26M from default 48M
+ * for mt8195
+ */
+ bool sw_pll_48m_to_26m;
enum mtk_phy_version version;
};
@@ -456,6 +474,33 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
+static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
+ u32 tmp;
+
+ if (!tphy->pdata->sw_pll_48m_to_26m)
+ return;
+
+ tmp = readl(com + U3P_USBPHYACR0);
+ tmp &= ~PA0_USB20_PLL_PREDIV;
+ tmp |= PA0_USB20_PLL_PREDIV_VAL(0);
+ writel(tmp, com + U3P_USBPHYACR0);
+
+ tmp = readl(com + U3P_USBPHYACR2);
+ tmp &= ~PA2_RG_U2PLL_BW;
+ tmp |= PA2_RG_U2PLL_BW_VAL(3);
+ writel(tmp, com + U3P_USBPHYACR2);
+
+ writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
+
+ tmp = readl(com + U3P_U2PHYA_RESV1);
+ tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL;
+ writel(tmp, com + U3P_U2PHYA_RESV1);
+}
+
static void u2_phy_instance_init(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
@@ -941,6 +986,7 @@ static int mtk_phy_init(struct phy *phy)
switch (instance->type) {
case PHY_TYPE_USB2:
+ u2_phy_pll_26m_set(tphy, instance);
u2_phy_instance_init(tphy, instance);
u2_phy_props_set(tphy, instance);
break;
@@ -1094,10 +1140,16 @@ static const struct mtk_phy_pdata mt8173_pdata = {
.version = MTK_PHY_V1,
};
+static const struct mtk_phy_pdata mt8195_pdata = {
+ .sw_pll_48m_to_26m = true,
+ .version = MTK_PHY_V3,
+};
+
static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
+ { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
--
2.18.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/3] phy: phy-mtk-tphy: add support mt8195
@ 2021-06-19 2:47 ` Chunfeng Yun
0 siblings, 0 replies; 16+ messages in thread
From: Chunfeng Yun @ 2021-06-19 2:47 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul, Rob Herring
Cc: Chunfeng Yun, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-phy, devicetree, linux-kernel
The controller is designed to use use PLL integer mode, but
in fact used fractional mode for some ones on mt8195, this
causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve
signal quality.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: noc changes
---
drivers/phy/mediatek/phy-mtk-tphy.c | 52 +++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 42a1174da6cc..c3dc1763a7eb 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -41,6 +41,8 @@
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
+#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
+#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004
@@ -52,6 +54,8 @@
#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define U3P_USBPHYACR2 0x008
+#define PA2_RG_U2PLL_BW GENMASK(21, 19)
+#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
#define U3P_USBPHYACR5 0x014
@@ -73,6 +77,14 @@
#define P2C_USB20_GPIO_MODE BIT(8)
#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
+#define U3P_U2PHYA_RESV 0x030
+#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b
+#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000
+
+#define U3P_U2PHYA_RESV1 0x044
+#define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
+#define P2R_RG_U2PLL_FRA_EN BIT(3)
+
#define U3D_U2PHYDCR0 0x060
#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
@@ -277,6 +289,12 @@ enum mtk_phy_version {
struct mtk_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
+ /*
+ * u2phy should use integer mode instead of fractional mode of
+ * 48M PLL, fix it by switching PLL to 26M from default 48M
+ * for mt8195
+ */
+ bool sw_pll_48m_to_26m;
enum mtk_phy_version version;
};
@@ -456,6 +474,33 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
+static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u2phy_banks *u2_banks = &instance->u2_banks;
+ void __iomem *com = u2_banks->com;
+ u32 tmp;
+
+ if (!tphy->pdata->sw_pll_48m_to_26m)
+ return;
+
+ tmp = readl(com + U3P_USBPHYACR0);
+ tmp &= ~PA0_USB20_PLL_PREDIV;
+ tmp |= PA0_USB20_PLL_PREDIV_VAL(0);
+ writel(tmp, com + U3P_USBPHYACR0);
+
+ tmp = readl(com + U3P_USBPHYACR2);
+ tmp &= ~PA2_RG_U2PLL_BW;
+ tmp |= PA2_RG_U2PLL_BW_VAL(3);
+ writel(tmp, com + U3P_USBPHYACR2);
+
+ writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
+
+ tmp = readl(com + U3P_U2PHYA_RESV1);
+ tmp |= P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL;
+ writel(tmp, com + U3P_U2PHYA_RESV1);
+}
+
static void u2_phy_instance_init(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
@@ -941,6 +986,7 @@ static int mtk_phy_init(struct phy *phy)
switch (instance->type) {
case PHY_TYPE_USB2:
+ u2_phy_pll_26m_set(tphy, instance);
u2_phy_instance_init(tphy, instance);
u2_phy_props_set(tphy, instance);
break;
@@ -1094,10 +1140,16 @@ static const struct mtk_phy_pdata mt8173_pdata = {
.version = MTK_PHY_V1,
};
+static const struct mtk_phy_pdata mt8195_pdata = {
+ .sw_pll_48m_to_26m = true,
+ .version = MTK_PHY_V3,
+};
+
static const struct of_device_id mtk_tphy_id_table[] = {
{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
+ { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
2021-06-19 2:47 ` Chunfeng Yun
(?)
(?)
@ 2021-07-12 20:12 ` Rob Herring
-1 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-07-12 20:12 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-mediatek, devicetree, linux-kernel, linux-phy,
linux-arm-kernel, Vinod Koul, Rob Herring,
Kishon Vijay Abraham I, Matthias Brugger
On Sat, 19 Jun 2021 10:47:17 +0800, Chunfeng Yun wrote:
> The PHYA architecture is updated, and doesn't support slew rate
> calibration anymore on 7nm or advanced process, add a new version
> number to support it.
> Due to the FreqMeter bank is not used but reserved, it's backward
> with v2 until now.
> For mt8195, no function changes when use generic v2 or v3 compatible,
> but prefer to use v3's compatible, it will not waste the time to
> calibrate the slew rate, and also correspond with hardware version.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: add more commit log suggested by Rob
> ---
> .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-07-12 20:12 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-07-12 20:12 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-mediatek, devicetree, linux-kernel, linux-phy,
linux-arm-kernel, Vinod Koul, Rob Herring,
Kishon Vijay Abraham I, Matthias Brugger
On Sat, 19 Jun 2021 10:47:17 +0800, Chunfeng Yun wrote:
> The PHYA architecture is updated, and doesn't support slew rate
> calibration anymore on 7nm or advanced process, add a new version
> number to support it.
> Due to the FreqMeter bank is not used but reserved, it's backward
> with v2 until now.
> For mt8195, no function changes when use generic v2 or v3 compatible,
> but prefer to use v3's compatible, it will not waste the time to
> calibrate the slew rate, and also correspond with hardware version.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: add more commit log suggested by Rob
> ---
> .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-07-12 20:12 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-07-12 20:12 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-mediatek, devicetree, linux-kernel, linux-phy,
linux-arm-kernel, Vinod Koul, Rob Herring,
Kishon Vijay Abraham I, Matthias Brugger
On Sat, 19 Jun 2021 10:47:17 +0800, Chunfeng Yun wrote:
> The PHYA architecture is updated, and doesn't support slew rate
> calibration anymore on 7nm or advanced process, add a new version
> number to support it.
> Due to the FreqMeter bank is not used but reserved, it's backward
> with v2 until now.
> For mt8195, no function changes when use generic v2 or v3 compatible,
> but prefer to use v3's compatible, it will not waste the time to
> calibrate the slew rate, and also correspond with hardware version.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: add more commit log suggested by Rob
> ---
> .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: phy: mediatek: tphy: add support hardware version 3
@ 2021-07-12 20:12 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2021-07-12 20:12 UTC (permalink / raw)
To: Chunfeng Yun
Cc: linux-mediatek, devicetree, linux-kernel, linux-phy,
linux-arm-kernel, Vinod Koul, Rob Herring,
Kishon Vijay Abraham I, Matthias Brugger
On Sat, 19 Jun 2021 10:47:17 +0800, Chunfeng Yun wrote:
> The PHYA architecture is updated, and doesn't support slew rate
> calibration anymore on 7nm or advanced process, add a new version
> number to support it.
> Due to the FreqMeter bank is not used but reserved, it's backward
> with v2 until now.
> For mt8195, no function changes when use generic v2 or v3 compatible,
> but prefer to use v3's compatible, it will not waste the time to
> calibrate the slew rate, and also correspond with hardware version.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v2: add more commit log suggested by Rob
> ---
> .../devicetree/bindings/phy/mediatek,tphy.yaml | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 16+ messages in thread