* [PATCH v6, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group base 5.13-rc1 Change since v5: - squash ddp component into one patch - add 8192 mmsys compatible data Yongqiang Niu (2): soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 soc: mediatek: mmsys: Add mt8192 mmsys routing table drivers/soc/mediatek/mt8192-mmsys.h | 68 ++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 ++ 3 files changed, 82 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h -- 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie, Jassi Brar, linux-kernel, dri-devel, Yongqiang Niu, Dennis YC Hsieh, Fabien Parent, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel base 5.13-rc1 Change since v5: - squash ddp component into one patch - add 8192 mmsys compatible data Yongqiang Niu (2): soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 soc: mediatek: mmsys: Add mt8192 mmsys routing table drivers/soc/mediatek/mt8192-mmsys.h | 68 ++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 ++ 3 files changed, 82 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h -- 1.8.1.1.dirty ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group base 5.13-rc1 Change since v5: - squash ddp component into one patch - add 8192 mmsys compatible data Yongqiang Niu (2): soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 soc: mediatek: mmsys: Add mt8192 mmsys routing table drivers/soc/mediatek/mt8192-mmsys.h | 68 ++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 ++ 3 files changed, 82 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group base 5.13-rc1 Change since v5: - squash ddp component into one patch - add 8192 mmsys compatible data Yongqiang Niu (2): soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 soc: mediatek: mmsys: Add mt8192 mmsys routing table drivers/soc/mediatek/mt8192-mmsys.h | 68 ++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 ++ 3 files changed, 82 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 2021-06-20 11:14 ` Yongqiang Niu (?) (?) @ 2021-06-20 11:14 ` Yongqiang Niu -1 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group This patch add some more ddp component OVL_2L2 is ovl which include 2 layers overlay POSTMASK control round corner for display frame RDMA4 read dma buffer Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..4bba275 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie, Jassi Brar, linux-kernel, dri-devel, Yongqiang Niu, Dennis YC Hsieh, Fabien Parent, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel This patch add some more ddp component OVL_2L2 is ovl which include 2 layers overlay POSTMASK control round corner for display frame RDMA4 read dma buffer Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..4bba275 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group This patch add some more ddp component OVL_2L2 is ovl which include 2 layers overlay POSTMASK control round corner for display frame RDMA4 read dma buffer Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..4bba275 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group This patch add some more ddp component OVL_2L2 is ovl which include 2 layers overlay POSTMASK control round corner for display frame RDMA4 read dma buffer Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6..4bba275 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 2021-06-20 11:14 ` Yongqiang Niu (?) (?) @ 2021-06-21 8:30 ` Chun-Kuang Hu -1 siblings, 0 replies; 16+ messages in thread From: Chun-Kuang Hu @ 2021-06-21 8:30 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent, Dennis YC Hsieh, DTML, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年6月20日 週日 下午7:15寫道： > > This patch add some more ddp component > OVL_2L2 is ovl which include 2 layers overlay > POSTMASK control round corner for display frame > RDMA4 read dma buffer > > Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Remove this. Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..4bba275 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > + DDP_COMPONENT_POSTMASK0, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > DDP_COMPONENT_PWM2, > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-21 8:30 ` Chun-Kuang Hu 0 siblings, 0 replies; 16+ messages in thread From: Chun-Kuang Hu @ 2021-06-21 8:30 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, Project_Global_Chrome_Upstream_Group, DTML, David Airlie, Jassi Brar, linux-kernel, DRI Development, Dennis YC Hsieh, Fabien Parent, Rob Herring, moderated list:ARM/Mediatek SoC support, Matthias Brugger, Linux ARM Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年6月20日 週日 下午7:15寫道： > > This patch add some more ddp component > OVL_2L2 is ovl which include 2 layers overlay > POSTMASK control round corner for display frame > RDMA4 read dma buffer > > Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Remove this. Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..4bba275 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > + DDP_COMPONENT_POSTMASK0, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > DDP_COMPONENT_PWM2, > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-21 8:30 ` Chun-Kuang Hu 0 siblings, 0 replies; 16+ messages in thread From: Chun-Kuang Hu @ 2021-06-21 8:30 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent, Dennis YC Hsieh, DTML, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年6月20日 週日 下午7:15寫道： > > This patch add some more ddp component > OVL_2L2 is ovl which include 2 layers overlay > POSTMASK control round corner for display frame > RDMA4 read dma buffer > > Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Remove this. Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..4bba275 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > + DDP_COMPONENT_POSTMASK0, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > DDP_COMPONENT_PWM2, > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 @ 2021-06-21 8:30 ` Chun-Kuang Hu 0 siblings, 0 replies; 16+ messages in thread From: Chun-Kuang Hu @ 2021-06-21 8:30 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent, Dennis YC Hsieh, DTML, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, DRI Development, Project_Global_Chrome_Upstream_Group Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年6月20日 週日 下午7:15寫道： > > This patch add some more ddp component > OVL_2L2 is ovl which include 2 layers overlay > POSTMASK control round corner for display frame > RDMA4 read dma buffer > > Change-Id: I464ea2dce6a312de8fad2cdbd94a4c71ab45af8f Remove this. Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6..4bba275 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > + DDP_COMPONENT_OVL_2L2, > DDP_COMPONENT_OVL1, > + DDP_COMPONENT_POSTMASK0, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1, > DDP_COMPONENT_PWM2, > DDP_COMPONENT_RDMA0, > DDP_COMPONENT_RDMA1, > DDP_COMPONENT_RDMA2, > + DDP_COMPONENT_RDMA4, > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > -- > 1.8.1.1.dirty > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table 2021-06-20 11:14 ` Yongqiang Niu (?) (?) @ 2021-06-20 11:14 ` Yongqiang Niu -1 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 68 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ 2 files changed, 79 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 0000000..3179029 --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ + diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 080660e..de7b122 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -52,6 +53,12 @@ .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -157,6 +164,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie, Jassi Brar, linux-kernel, dri-devel, Yongqiang Niu, Dennis YC Hsieh, Fabien Parent, Rob Herring, linux-mediatek, Matthias Brugger, linux-arm-kernel mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 68 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ 2 files changed, 79 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 0000000..3179029 --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ + diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 080660e..de7b122 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -52,6 +53,12 @@ .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -157,6 +164,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 68 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ 2 files changed, 79 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 0000000..3179029 --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ + diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 080660e..de7b122 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -52,6 +53,12 @@ .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -157,6 +164,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; -- 1.8.1.1.dirty _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v6, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table @ 2021-06-20 11:14 ` Yongqiang Niu 0 siblings, 0 replies; 16+ messages in thread From: Yongqiang Niu @ 2021-06-20 11:14 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 68 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ 2 files changed, 79 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 0000000..3179029 --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ + diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 080660e..de7b122 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -52,6 +53,12 @@ .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -157,6 +164,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; -- 1.8.1.1.dirty _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-06-21 8:33 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-20 11:14 [PATCH v6, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` [PATCH v6, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-21 8:30 ` Chun-Kuang Hu 2021-06-21 8:30 ` Chun-Kuang Hu 2021-06-21 8:30 ` Chun-Kuang Hu 2021-06-21 8:30 ` Chun-Kuang Hu 2021-06-20 11:14 ` [PATCH v6, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu 2021-06-20 11:14 ` Yongqiang Niu
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