* [PATCH 1/4] MIPS: X1830: Respect cell count of common properties.
2021-06-22 7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
@ 2021-06-22 7:37 ` 周琰杰 (Zhou Yanjie)
2021-06-22 12:30 ` Paul Cercueil
2021-06-22 7:37 ` [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
` (2 subsequent siblings)
3 siblings, 1 reply; 13+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 7:37 UTC (permalink / raw)
To: tsbogend, paul, robh+dt
Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
If N fields of X cells should be provided, then that's what the
devicetree should represent, instead of having one single field of
(N * X) cells.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index b21c930..59ca3a8 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -97,9 +97,9 @@
#clock-cells = <1>;
- clocks = <&cgu X1830_CLK_RTCLK
- &cgu X1830_CLK_EXCLK
- &cgu X1830_CLK_PCLK>;
+ clocks = <&cgu X1830_CLK_RTCLK>,
+ <&cgu X1830_CLK_EXCLK>,
+ <&cgu X1830_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@@ -274,8 +274,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
- reg = <0x13420000 0x400
- 0x13421000 0x40>;
+ reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/4] MIPS: X1830: Respect cell count of common properties.
2021-06-22 7:37 ` [PATCH 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
@ 2021-06-22 12:30 ` Paul Cercueil
0 siblings, 0 replies; 13+ messages in thread
From: Paul Cercueil @ 2021-06-22 12:30 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Zhou,
Le mar., juin 22 2021 at 15:37:22 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> If N fields of X cells should be provided, then that's what the
> devicetree should represent, instead of having one single field of
> (N * X) cells.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
-Paul
> ---
> arch/mips/boot/dts/ingenic/x1830.dtsi | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index b21c930..59ca3a8 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -97,9 +97,9 @@
>
> #clock-cells = <1>;
>
> - clocks = <&cgu X1830_CLK_RTCLK
> - &cgu X1830_CLK_EXCLK
> - &cgu X1830_CLK_PCLK>;
> + clocks = <&cgu X1830_CLK_RTCLK>,
> + <&cgu X1830_CLK_EXCLK>,
> + <&cgu X1830_CLK_PCLK>;
> clock-names = "rtc", "ext", "pclk";
>
> interrupt-controller;
> @@ -274,8 +274,7 @@
>
> pdma: dma-controller@13420000 {
> compatible = "ingenic,x1830-dma";
> - reg = <0x13420000 0x400
> - 0x13421000 0x40>;
> + reg = <0x13420000 0x400>, <0x13421000 0x40>;
> #dma-cells = <2>;
>
> interrupt-parent = <&intc>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
2021-06-22 7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 7:37 ` [PATCH 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
@ 2021-06-22 7:37 ` 周琰杰 (Zhou Yanjie)
2021-06-22 12:31 ` Paul Cercueil
2021-06-22 7:37 ` [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree 周琰杰 (Zhou Yanjie)
2021-06-22 7:37 ` [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
3 siblings, 1 reply; 13+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 7:37 UTC (permalink / raw)
To: tsbogend, paul, robh+dt
Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index aac9ded..dec7909 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -80,6 +80,11 @@
status = "disabled";
};
+
+ mac_phy_ctrl: mac-phy-ctrl@e8 {
+ compatible = "syscon";
+ reg = <0xe8 0x4>;
+ };
};
ost: timer@12000000 {
@@ -347,6 +352,8 @@
clocks = <&cgu X1000_CLK_MAC>;
clock-names = "stmmaceth";
+ mode-reg = <&mac_phy_ctrl>;
+
status = "disabled";
mdio: mdio {
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index 59ca3a8..215257f 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -73,6 +73,11 @@
status = "disabled";
};
+
+ mac_phy_ctrl: mac-phy-ctrl@e8 {
+ compatible = "syscon";
+ reg = <0xe8 0x4>;
+ };
};
ost: timer@12000000 {
@@ -336,6 +341,8 @@
clocks = <&cgu X1830_CLK_MAC>;
clock-names = "stmmaceth";
+ mode-reg = <&mac_phy_ctrl>;
+
status = "disabled";
mdio: mdio {
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
2021-06-22 7:37 ` [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2021-06-22 12:31 ` Paul Cercueil
0 siblings, 0 replies; 13+ messages in thread
From: Paul Cercueil @ 2021-06-22 12:31 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi,
Le mar., juin 22 2021 at 15:37:23 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
> arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
> arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index aac9ded..dec7909 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -80,6 +80,11 @@
>
> status = "disabled";
> };
> +
> + mac_phy_ctrl: mac-phy-ctrl@e8 {
> + compatible = "syscon";
> + reg = <0xe8 0x4>;
> + };
> };
>
> ost: timer@12000000 {
> @@ -347,6 +352,8 @@
> clocks = <&cgu X1000_CLK_MAC>;
> clock-names = "stmmaceth";
>
> + mode-reg = <&mac_phy_ctrl>;
> +
> status = "disabled";
>
> mdio: mdio {
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index 59ca3a8..215257f 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -73,6 +73,11 @@
>
> status = "disabled";
> };
> +
> + mac_phy_ctrl: mac-phy-ctrl@e8 {
> + compatible = "syscon";
> + reg = <0xe8 0x4>;
> + };
> };
>
> ost: timer@12000000 {
> @@ -336,6 +341,8 @@
> clocks = <&cgu X1830_CLK_MAC>;
> clock-names = "stmmaceth";
>
> + mode-reg = <&mac_phy_ctrl>;
> +
> status = "disabled";
>
> mdio: mdio {
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree.
2021-06-22 7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 7:37 ` [PATCH 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 7:37 ` [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2021-06-22 7:37 ` 周琰杰 (Zhou Yanjie)
2021-06-22 12:46 ` Paul Cercueil
2021-06-22 7:37 ` [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
3 siblings, 1 reply; 13+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 7:37 UTC (permalink / raw)
To: tsbogend, paul, robh+dt
Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
Change the "lcd-24bit" in the pinctrl groups to "lcd-8bit",
"lcd-16bit", "lcd-18bit", "lcd-24bit", since the pinctrl
driver has done the necessary splitting of the lcd group,
and it is convenient to further streamline the lcd-24bit
group in the subsequent pinctrl driver.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/boot/dts/ingenic/gcw0.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
index f4c04f2..dec3ba6f 100644
--- a/arch/mips/boot/dts/ingenic/gcw0.dts
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -393,7 +393,7 @@
&pinctrl {
pins_lcd: lcd {
function = "lcd";
- groups = "lcd-24bit";
+ groups = "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit";
};
pins_uart2: uart2 {
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree.
2021-06-22 7:37 ` [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree 周琰杰 (Zhou Yanjie)
@ 2021-06-22 12:46 ` Paul Cercueil
2021-06-22 13:51 ` 周琰杰
0 siblings, 1 reply; 13+ messages in thread
From: Paul Cercueil @ 2021-06-22 12:46 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Zhou,
Le mar., juin 22 2021 at 15:37:24 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Change the "lcd-24bit" in the pinctrl groups to "lcd-8bit",
> "lcd-16bit", "lcd-18bit", "lcd-24bit", since the pinctrl
> driver has done the necessary splitting of the lcd group,
> and it is convenient to further streamline the lcd-24bit
> group in the subsequent pinctrl driver.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
> arch/mips/boot/dts/ingenic/gcw0.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts
> b/arch/mips/boot/dts/ingenic/gcw0.dts
> index f4c04f2..dec3ba6f 100644
> --- a/arch/mips/boot/dts/ingenic/gcw0.dts
> +++ b/arch/mips/boot/dts/ingenic/gcw0.dts
> @@ -393,7 +393,7 @@
> &pinctrl {
> pins_lcd: lcd {
> function = "lcd";
> - groups = "lcd-24bit";
> + groups = "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit";
No, I'm pretty sure this won't work, since "lcd-24bit" contains pins
that are also contained by the other groups.
-Paul
> };
>
> pins_uart2: uart2 {
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree.
2021-06-22 12:46 ` Paul Cercueil
@ 2021-06-22 13:51 ` 周琰杰
2021-06-22 14:05 ` Paul Cercueil
0 siblings, 1 reply; 13+ messages in thread
From: 周琰杰 @ 2021-06-22 13:51 UTC (permalink / raw)
To: Paul Cercueil
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Paul,
于 Tue, 22 Jun 2021 13:46:57 +0100
Paul Cercueil <paul@opendingux.net> 写道:
> Hi Zhou,
>
> Le mar., juin 22 2021 at 15:37:24 +0800, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
> > Change the "lcd-24bit" in the pinctrl groups to "lcd-8bit",
> > "lcd-16bit", "lcd-18bit", "lcd-24bit", since the pinctrl
> > driver has done the necessary splitting of the lcd group,
> > and it is convenient to further streamline the lcd-24bit
> > group in the subsequent pinctrl driver.
> >
> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> > ---
> > arch/mips/boot/dts/ingenic/gcw0.dts | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts
> > b/arch/mips/boot/dts/ingenic/gcw0.dts
> > index f4c04f2..dec3ba6f 100644
> > --- a/arch/mips/boot/dts/ingenic/gcw0.dts
> > +++ b/arch/mips/boot/dts/ingenic/gcw0.dts
> > @@ -393,7 +393,7 @@
> > &pinctrl {
> > pins_lcd: lcd {
> > function = "lcd";
> > - groups = "lcd-24bit";
> > + groups = "lcd-8bit", "lcd-16bit", "lcd-18bit",
> > "lcd-24bit";
>
> No, I'm pretty sure this won't work, since "lcd-24bit" contains pins
> that are also contained by the other groups.
>
Sure, it seems that we should modify the pinctrl first, then modify the
dts, and then put them in the same series, so as to ensure that they do
not cause damage.
Thanks and best regards!
> -Paul
>
> > };
> >
> > pins_uart2: uart2 {
> > --
> > 2.7.4
> >
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree.
2021-06-22 13:51 ` 周琰杰
@ 2021-06-22 14:05 ` Paul Cercueil
2021-06-22 14:41 ` 周琰杰
0 siblings, 1 reply; 13+ messages in thread
From: Paul Cercueil @ 2021-06-22 14:05 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Zhou,
Le mar., juin 22 2021 at 21:51:19 +0800, 周琰杰
<zhouyanjie@wanyeetech.com> a écrit :
> Hi Paul,
>
> 于 Tue, 22 Jun 2021 13:46:57 +0100
> Paul Cercueil <paul@opendingux.net> 写道:
>
>> Hi Zhou,
>>
>> Le mar., juin 22 2021 at 15:37:24 +0800, 周琰杰 (Zhou Yanjie)
>> <zhouyanjie@wanyeetech.com> a écrit :
>> > Change the "lcd-24bit" in the pinctrl groups to "lcd-8bit",
>> > "lcd-16bit", "lcd-18bit", "lcd-24bit", since the pinctrl
>> > driver has done the necessary splitting of the lcd group,
>> > and it is convenient to further streamline the lcd-24bit
>> > group in the subsequent pinctrl driver.
>> >
>> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> > ---
>> > arch/mips/boot/dts/ingenic/gcw0.dts | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts
>> > b/arch/mips/boot/dts/ingenic/gcw0.dts
>> > index f4c04f2..dec3ba6f 100644
>> > --- a/arch/mips/boot/dts/ingenic/gcw0.dts
>> > +++ b/arch/mips/boot/dts/ingenic/gcw0.dts
>> > @@ -393,7 +393,7 @@
>> > &pinctrl {
>> > pins_lcd: lcd {
>> > function = "lcd";
>> > - groups = "lcd-24bit";
>> > + groups = "lcd-8bit", "lcd-16bit", "lcd-18bit",
>> > "lcd-24bit";
>>
>> No, I'm pretty sure this won't work, since "lcd-24bit" contains pins
>> that are also contained by the other groups.
>>
>
> Sure, it seems that we should modify the pinctrl first, then modify
> the
> dts, and then put them in the same series, so as to ensure that they
> do
> not cause damage.
No, the "lcd-24bit" group is ABI now. We can't change it...
-Paul
>
> Thanks and best regards!
>
>> -Paul
>>
>> > };
>> >
>> > pins_uart2: uart2 {
>> > --
>> > 2.7.4
>> >
>>
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree.
2021-06-22 14:05 ` Paul Cercueil
@ 2021-06-22 14:41 ` 周琰杰
0 siblings, 0 replies; 13+ messages in thread
From: 周琰杰 @ 2021-06-22 14:41 UTC (permalink / raw)
To: Paul Cercueil
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Paul,
于 Tue, 22 Jun 2021 15:05:25 +0100
Paul Cercueil <paul@opendingux.net> 写道:
> Hi Zhou,
>
> Le mar., juin 22 2021 at 21:51:19 +0800, 周琰杰
> <zhouyanjie@wanyeetech.com> a écrit :
> > Hi Paul,
> >
> > 于 Tue, 22 Jun 2021 13:46:57 +0100
> > Paul Cercueil <paul@opendingux.net> 写道:
> >
> >> Hi Zhou,
> >>
> >> Le mar., juin 22 2021 at 15:37:24 +0800, 周琰杰 (Zhou Yanjie)
> >> <zhouyanjie@wanyeetech.com> a écrit :
> >> > Change the "lcd-24bit" in the pinctrl groups to "lcd-8bit",
> >> > "lcd-16bit", "lcd-18bit", "lcd-24bit", since the pinctrl
> >> > driver has done the necessary splitting of the lcd group,
> >> > and it is convenient to further streamline the lcd-24bit
> >> > group in the subsequent pinctrl driver.
> >> >
> >> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> >> > ---
> >> > arch/mips/boot/dts/ingenic/gcw0.dts | 2 +-
> >> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >> >
> >> > diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts
> >> > b/arch/mips/boot/dts/ingenic/gcw0.dts
> >> > index f4c04f2..dec3ba6f 100644
> >> > --- a/arch/mips/boot/dts/ingenic/gcw0.dts
> >> > +++ b/arch/mips/boot/dts/ingenic/gcw0.dts
> >> > @@ -393,7 +393,7 @@
> >> > &pinctrl {
> >> > pins_lcd: lcd {
> >> > function = "lcd";
> >> > - groups = "lcd-24bit";
> >> > + groups = "lcd-8bit", "lcd-16bit", "lcd-18bit",
> >> > "lcd-24bit";
> >>
> >> No, I'm pretty sure this won't work, since "lcd-24bit" contains
> >> pins that are also contained by the other groups.
> >>
> >
> > Sure, it seems that we should modify the pinctrl first, then modify
> > the
> > dts, and then put them in the same series, so as to ensure that
> > they do
> > not cause damage.
>
> No, the "lcd-24bit" group is ABI now. We can't change it...
>
Sure.
Thanks and best regards!
> -Paul
>
> >
> > Thanks and best regards!
> >
> >> -Paul
> >>
> >> > };
> >> >
> >> > pins_uart2: uart2 {
> >> > --
> >> > 2.7.4
> >> >
> >>
> >
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP.
2021-06-22 7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
` (2 preceding siblings ...)
2021-06-22 7:37 ` [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree 周琰杰 (Zhou Yanjie)
@ 2021-06-22 7:37 ` 周琰杰 (Zhou Yanjie)
2021-06-22 12:39 ` Paul Cercueil
3 siblings, 1 reply; 13+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-06-22 7:37 UTC (permalink / raw)
To: tsbogend, paul, robh+dt
Cc: linux-mips, devicetree, linux-kernel, dongsheng.qiu, aric.pzqi,
rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
1.On the hardware of CI20 v1, when the MSC0 clock is 50MHz, there is
a certain probability that the communication with the SD card will
be abnormal, and the file system will be damaged in severe cases.
Limiting the maximum MSC0 clock frequency to 25MHz can solve this
problem.
2.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
3.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/boot/dts/ingenic/ci20.dts | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..58123e0 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,11 +118,22 @@
assigned-clock-rates = <48000000>;
};
+&tcu {
+ /*
+ * 750 kHz for the system timers and 3 MHz for the clocksources,
+ * use channel #0 and #1 for the per cpu system timers, and use
+ * channel #2 for the clocksource.
+ */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+ assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>;
+};
+
&mmc0 {
status = "okay";
bus-width = <4>;
- max-frequency = <50000000>;
+ max-frequency = <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&pins_mmc0>;
@@ -522,13 +533,3 @@
bias-disable;
};
};
-
-&tcu {
- /*
- * 750 kHz for the system timer and 3 MHz for the clocksource,
- * use channel #0 for the system timer, #1 for the clocksource.
- */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
- <&tcu TCU_CLK_OST>;
- assigned-clock-rates = <750000>, <3000000>, <3000000>;
-};
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP.
2021-06-22 7:37 ` [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
@ 2021-06-22 12:39 ` Paul Cercueil
2021-06-22 13:55 ` 周琰杰
0 siblings, 1 reply; 13+ messages in thread
From: Paul Cercueil @ 2021-06-22 12:39 UTC (permalink / raw)
To: 周琰杰
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Zhou,
Le mar., juin 22 2021 at 15:37:25 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> 1.On the hardware of CI20 v1, when the MSC0 clock is 50MHz, there is
> a certain probability that the communication with the SD card will
> be abnormal, and the file system will be damaged in severe cases.
> Limiting the maximum MSC0 clock frequency to 25MHz can solve this
> problem.
That doesn't prevent anything, since you could very well use a recent
kernel with an older device tree.
Besides, the PM does say that 50 MHz bus clock is supported, so I
suspect that your problem is actually a driver issue.
The proper way to work around it, temporarily or not, would be to set
the max frequency to 25 MHz in the driver itself, if the board's
compatible strings matches ingenic,ci20.
Cheers,
-Paul
> 2.Add a new TCU channel as the percpu timer of core1, this is to
> prepare for the subsequent SMP support. The newly added channel
> will not adversely affect the current single-core state.
> 3.Adjust the position of TCU node to make it consistent with the
> order in jz4780.dtsi file.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
> arch/mips/boot/dts/ingenic/ci20.dts | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
> b/arch/mips/boot/dts/ingenic/ci20.dts
> index 8877c62..58123e0 100644
> --- a/arch/mips/boot/dts/ingenic/ci20.dts
> +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> @@ -118,11 +118,22 @@
> assigned-clock-rates = <48000000>;
> };
>
> +&tcu {
> + /*
> + * 750 kHz for the system timers and 3 MHz for the clocksources,
> + * use channel #0 and #1 for the per cpu system timers, and use
> + * channel #2 for the clocksource.
> + */
> + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
> + assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>;
> +};
> +
> &mmc0 {
> status = "okay";
>
> bus-width = <4>;
> - max-frequency = <50000000>;
> + max-frequency = <25000000>;
>
> pinctrl-names = "default";
> pinctrl-0 = <&pins_mmc0>;
> @@ -522,13 +533,3 @@
> bias-disable;
> };
> };
> -
> -&tcu {
> - /*
> - * 750 kHz for the system timer and 3 MHz for the clocksource,
> - * use channel #0 for the system timer, #1 for the clocksource.
> - */
> - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
> - <&tcu TCU_CLK_OST>;
> - assigned-clock-rates = <750000>, <3000000>, <3000000>;
> -};
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP.
2021-06-22 12:39 ` Paul Cercueil
@ 2021-06-22 13:55 ` 周琰杰
0 siblings, 0 replies; 13+ messages in thread
From: 周琰杰 @ 2021-06-22 13:55 UTC (permalink / raw)
To: Paul Cercueil
Cc: tsbogend, robh+dt, linux-mips, devicetree, linux-kernel,
dongsheng.qiu, aric.pzqi, rick.tyliu, sihui.liu, jun.jiang,
sernia.zhou
Hi Paul,
于 Tue, 22 Jun 2021 13:39:02 +0100
Paul Cercueil <paul@crapouillou.net> 写道:
> Hi Zhou,
>
> Le mar., juin 22 2021 at 15:37:25 +0800, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
> > 1.On the hardware of CI20 v1, when the MSC0 clock is 50MHz, there is
> > a certain probability that the communication with the SD card will
> > be abnormal, and the file system will be damaged in severe cases.
> > Limiting the maximum MSC0 clock frequency to 25MHz can solve this
> > problem.
>
> That doesn't prevent anything, since you could very well use a recent
> kernel with an older device tree.
>
> Besides, the PM does say that 50 MHz bus clock is supported, so I
> suspect that your problem is actually a driver issue.
>
> The proper way to work around it, temporarily or not, would be to set
> the max frequency to 25 MHz in the driver itself, if the board's
> compatible strings matches ingenic,ci20.
>
Sure, then let's focus on tcu first, I will send the v2 version.
Thanks and best regards!
> Cheers,
> -Paul
>
> > 2.Add a new TCU channel as the percpu timer of core1, this is to
> > prepare for the subsequent SMP support. The newly added channel
> > will not adversely affect the current single-core state.
> > 3.Adjust the position of TCU node to make it consistent with the
> > order in jz4780.dtsi file.
> >
> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> > ---
> > arch/mips/boot/dts/ingenic/ci20.dts | 23 ++++++++++++-----------
> > 1 file changed, 12 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
> > b/arch/mips/boot/dts/ingenic/ci20.dts
> > index 8877c62..58123e0 100644
> > --- a/arch/mips/boot/dts/ingenic/ci20.dts
> > +++ b/arch/mips/boot/dts/ingenic/ci20.dts
> > @@ -118,11 +118,22 @@
> > assigned-clock-rates = <48000000>;
> > };
> >
> > +&tcu {
> > + /*
> > + * 750 kHz for the system timers and 3 MHz for the
> > clocksources,
> > + * use channel #0 and #1 for the per cpu system timers,
> > and use
> > + * channel #2 for the clocksource.
> > + */
> > + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu
> > TCU_CLK_TIMER1>,
> > + <&tcu TCU_CLK_TIMER2>,
> > <&tcu TCU_CLK_OST>;
> > + assigned-clock-rates = <750000>, <750000>, <3000000>,
> > <3000000>; +};
> > +
> > &mmc0 {
> > status = "okay";
> >
> > bus-width = <4>;
> > - max-frequency = <50000000>;
> > + max-frequency = <25000000>;
> >
> > pinctrl-names = "default";
> > pinctrl-0 = <&pins_mmc0>;
> > @@ -522,13 +533,3 @@
> > bias-disable;
> > };
> > };
> > -
> > -&tcu {
> > - /*
> > - * 750 kHz for the system timer and 3 MHz for the
> > clocksource,
> > - * use channel #0 for the system timer, #1 for the
> > clocksource.
> > - */
> > - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu
> > TCU_CLK_TIMER1>,
> > - <&tcu TCU_CLK_OST>;
> > - assigned-clock-rates = <750000>, <3000000>, <3000000>;
> > -};
> > --
> > 2.7.4
> >
>
^ permalink raw reply [flat|nested] 13+ messages in thread