From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: u-boot@lists.denx.de
Cc: Masami Hiramatsu <masami.hiramatsu@linaro.org>,
Jassi Brar <jaswinder.singh@linaro.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH 1/6] clk: uniphier: Add PCIe clock entry
Date: Tue, 6 Jul 2021 19:01:06 +0900 [thread overview]
Message-ID: <1625565671-30022-2-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1625565671-30022-1-git-send-email-hayashi.kunihiko@socionext.com>
Add clock control for PCIe controller on each SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index c627a4b..ff5d364 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -29,6 +29,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19), /* usb30-phy (PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20), /* usb31-phy (PXs2) */
+ UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2), /* pcie (Pro5) */
{ /* sentinel */ }
#endif
};
@@ -43,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */
UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13), /* usb30-phy1 (LD20) */
+ UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4), /* pcie */
{ /* sentinel */ }
#endif
};
@@ -62,6 +64,7 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20), /* usb30-phy2 */
UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17), /* usb31-phy0 */
UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19), /* usb31-phy1 */
+ UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 3), /* pcie */
{ /* sentinel */ }
#endif
};
--
2.7.4
next prev parent reply other threads:[~2021-07-06 10:01 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-06 10:01 [PATCH 0/6] uniphier: Add PCIe host controller and Akebi96 board support Kunihiko Hayashi
2021-07-06 10:01 ` Kunihiko Hayashi [this message]
2021-07-14 20:52 ` [PATCH 1/6] clk: uniphier: Add PCIe clock entry Tom Rini
2021-07-06 10:01 ` [PATCH 2/6] reset: uniphier: Add PCIe reset entry Kunihiko Hayashi
2021-07-14 20:52 ` Tom Rini
2021-07-06 10:01 ` [PATCH 3/6] phy: socionext: Add UniPhier PCIe PHY driver Kunihiko Hayashi
2021-07-14 20:52 ` Tom Rini
2021-07-06 10:01 ` [PATCH 4/6] pci: uniphier: Add UniPhier PCIe controller driver Kunihiko Hayashi
2021-07-14 20:52 ` Tom Rini
2021-07-06 10:01 ` [PATCH 5/6] configs: uniphier: Enable CONFIG_SYS_PCI_64BIT Kunihiko Hayashi
2021-07-14 20:53 ` Tom Rini
2021-07-06 10:01 ` [PATCH 6/6] ARM: dts: uniphier: Add support for Akebi96 Kunihiko Hayashi
2021-07-14 20:53 ` Tom Rini
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