All of lore.kernel.org
 help / color / mirror / Atom feed
From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Matt Roper" <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches
Date: Thu, 22 Jul 2021 00:06:50 -0000	[thread overview]
Message-ID: <162691241086.30345.2496249603599894290@emeril.freedesktop.org> (raw)
In-Reply-To: <20210721223043.834562-1-matthew.d.roper@intel.com>

== Series Details ==

Series: CI pass for reviewed Xe_HP SDV and DG2 patches
URL   : https://patchwork.freedesktop.org/series/92853/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
3c0d66813984 drm/i915: Add XE_HP initial definitions
35b61c43f3e6 drm/i915/xehpsdv: add initial XeHP SDV definitions
af8335fc25c0 drm/i915/dg2: add DG2 platform info
-:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#53: FILE: drivers/gpu/drm/i915/i915_drv.h:1580:
+#define IS_DG2_GT_STEP(__i915, variant, since, until) \
+	(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
+	 IS_GT_STEP(__i915, since, until))

-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#57: FILE: drivers/gpu/drm/i915/i915_drv.h:1584:
+#define IS_DG2_DISP_STEP(__i915, since, until) \
+	(IS_DG2(__i915) && \
+	 IS_DISPLAY_STEP(__i915, since, until))

total: 0 errors, 0 warnings, 2 checks, 117 lines checked
2e778d91bf0c drm/i915: Fork DG1 interrupt handler
2024f48f8303 drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
54b16faca000 drm/i915/gen12: Use fuse info to enable SFC
748de8c99157 drm/i915/selftests: Allow for larger engine counts
66471aa168d2 drm/i915/xehp: Handle new device context ID format
0f78529c87f9 drm/i915/xehp: New engine context offsets
bf4e9f961c54 drm/i915/dg2: Add fake PCH
ee4554dd0f46 drm/i915/dg2: Add cdclk table and reference clock
85a603e64280 drm/i915/dg2: Skip shared DPLL handling
ca6cdb06bc87 drm/i915/dg2: Don't wait for AUX power well enable ACKs
f8744c6d424a drm/i915/dg2: Setup display outputs
4d664ff3d52d drm/i915/dg2: Add dbuf programming
adb51870fc17 drm/i915/dg2: Don't program BW_BUDDY registers
358ea009b220 drm/i915/dg2: Don't read DRAM info
7704c9aa289a drm/i915/dg2: DG2 has fixed memory bandwidth


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2021-07-22  0:06 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 22:30 [Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-22  0:06 ` Patchwork [this message]
2021-07-22  0:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for CI pass for reviewed Xe_HP SDV and DG2 patches Patchwork
2021-07-22  0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22  7:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-22 16:42   ` Matt Roper

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=162691241086.30345.2496249603599894290@emeril.freedesktop.org \
    --to=patchwork@emeril.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.