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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 14/18] drm/i915/dg2: Setup display outputs
Date: Wed, 21 Jul 2021 15:30:39 -0700	[thread overview]
Message-ID: <20210721223043.834562-15-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210721223043.834562-1-matthew.d.roper@intel.com>

DG2 has outputs on DDI A-D attached to what the bspec diagram shows as
"Combo PHY A-D."  Note that despite being labelled "combo" the PHYs on
these outputs are Synopsys PHYs rather than traditional Intel combo PHY
technology.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a165bb8ca2f8..2b082e1827a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11333,7 +11333,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_C);
+		intel_ddi_init(dev_priv, PORT_D_XELPD);
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_TC1);
-- 
2.25.4

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  parent reply	other threads:[~2021-07-21 22:31 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 22:30 [Intel-gfx] [CI 00/18] CI pass for reviewed Xe_HP SDV and DG2 patches Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 01/18] drm/i915: Add XE_HP initial definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 02/18] drm/i915/xehpsdv: add initial XeHP SDV definitions Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 03/18] drm/i915/dg2: add DG2 platform info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 04/18] drm/i915: Fork DG1 interrupt handler Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 05/18] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 06/18] drm/i915/gen12: Use fuse info to enable SFC Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 07/18] drm/i915/selftests: Allow for larger engine counts Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 08/18] drm/i915/xehp: Handle new device context ID format Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 09/18] drm/i915/xehp: New engine context offsets Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 10/18] drm/i915/dg2: Add fake PCH Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 11/18] drm/i915/dg2: Add cdclk table and reference clock Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 12/18] drm/i915/dg2: Skip shared DPLL handling Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 13/18] drm/i915/dg2: Don't wait for AUX power well enable ACKs Matt Roper
2021-07-21 22:30 ` Matt Roper [this message]
2021-07-21 22:30 ` [Intel-gfx] [CI 15/18] drm/i915/dg2: Add dbuf programming Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 16/18] drm/i915/dg2: Don't program BW_BUDDY registers Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 17/18] drm/i915/dg2: Don't read DRAM info Matt Roper
2021-07-21 22:30 ` [Intel-gfx] [CI 18/18] drm/i915/dg2: DG2 has fixed memory bandwidth Matt Roper
2021-07-22  0:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI pass for reviewed Xe_HP SDV and DG2 patches Patchwork
2021-07-22  0:08 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-22  0:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-22  7:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-22 16:42   ` Matt Roper

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