* [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-07-28 11:54 ` Akhil P Oommen
0 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2021-07-28 11:54 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jordan Crouse, Douglas Anderson, Rob Clark, Matthias Kaehlcke,
Jonathan Marek, Andy Gross, linux-kernel
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
This has dependency on the below GPUCC bindings patch which is already
accepted in clk-next:
https://patchwork.kernel.org/project/linux-clk/list/?series=514831&state=%2A&archive=both
Changes in v3:
- Re-ordered the nodes based on address (Stephan)
- Added the patch for gpu cooling to the stack.
Changes in v2:
- formatting update and removed a duplicate header (Stephan)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 116 +++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 029723a..c88f366 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -592,6 +593,85 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpu@3d00000 {
+ compatible = "qcom,adreno-635.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <6832000>;
+ };
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1804000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d69000 {
+ compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0x400>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sc7280-gpucc";
reg = <0 0x03d90000 0 0x9000>;
@@ -606,6 +686,42 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-07-28 11:54 ` Akhil P Oommen
0 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2021-07-28 11:54 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jonathan Marek, linux-kernel, Douglas Anderson, Jordan Crouse,
Andy Gross, Matthias Kaehlcke
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
This has dependency on the below GPUCC bindings patch which is already
accepted in clk-next:
https://patchwork.kernel.org/project/linux-clk/list/?series=514831&state=%2A&archive=both
Changes in v3:
- Re-ordered the nodes based on address (Stephan)
- Added the patch for gpu cooling to the stack.
Changes in v2:
- formatting update and removed a duplicate header (Stephan)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 116 +++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 029723a..c88f366 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -592,6 +593,85 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpu@3d00000 {
+ compatible = "qcom,adreno-635.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <6832000>;
+ };
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1804000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d69000 {
+ compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0x400>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sc7280-gpucc";
reg = <0 0x03d90000 0 0x9000>;
@@ -606,6 +686,42 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support
2021-07-28 11:54 ` Akhil P Oommen
@ 2021-07-28 11:54 ` Akhil P Oommen
-1 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2021-07-28 11:54 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jordan Crouse, Douglas Anderson, Rob Clark, Matthias Kaehlcke,
Jonathan Marek, Andy Gross, linux-kernel
From: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c88f366..45a96d1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -593,7 +593,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- gpu@3d00000 {
+ gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x03d00000 0 0x40000>,
@@ -608,6 +608,7 @@
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2524,16 +2525,16 @@
};
gpuss0-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss0_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss0_crit: gpuss0-crit {
@@ -2542,19 +2543,26 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpuss1-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss1_crit: gpuss1-crit {
@@ -2563,6 +2571,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
nspss0-thermal {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support
@ 2021-07-28 11:54 ` Akhil P Oommen
0 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2021-07-28 11:54 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jonathan Marek, linux-kernel, Douglas Anderson, Jordan Crouse,
Andy Gross, Matthias Kaehlcke
From: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c88f366..45a96d1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -593,7 +593,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- gpu@3d00000 {
+ gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x03d00000 0 0x40000>,
@@ -608,6 +608,7 @@
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2524,16 +2525,16 @@
};
gpuss0-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss0_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss0_crit: gpuss0-crit {
@@ -2542,19 +2543,26 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpuss1-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss1_crit: gpuss1-crit {
@@ -2563,6 +2571,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
nspss0-thermal {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
2021-07-28 11:54 ` Akhil P Oommen
@ 2021-07-29 17:19 ` Stephen Boyd
-1 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:19 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm
Cc: Jordan Crouse, Douglas Anderson, Rob Clark, Matthias Kaehlcke,
Jonathan Marek, Andy Gross, linux-kernel
Quoting Akhil P Oommen (2021-07-28 04:54:01)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 029723a..c88f366 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -592,6 +593,85 @@
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + gpu@3d00000 {
> + compatible = "qcom,adreno-635.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0x401>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-550000000 {
> + opp-hz = /bits/ 64 <550000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <6832000>;
> + };
> +
> + opp-450000000 {
Why is 450000000 after 550000000? Is it on purpose? If not intended
please sort by frequency.
> + opp-hz = /bits/ 64 <450000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <4068000>;
> + };
> +
> + opp-315000000 {
> + opp-hz = /bits/ 64 <315000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <1804000>;
> + };
> + };
> + };
> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-07-29 17:19 ` Stephen Boyd
0 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:19 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm
Cc: Jonathan Marek, linux-kernel, Douglas Anderson, Jordan Crouse,
Andy Gross, Matthias Kaehlcke
Quoting Akhil P Oommen (2021-07-28 04:54:01)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 029723a..c88f366 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -592,6 +593,85 @@
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + gpu@3d00000 {
> + compatible = "qcom,adreno-635.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0x401>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-550000000 {
> + opp-hz = /bits/ 64 <550000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <6832000>;
> + };
> +
> + opp-450000000 {
Why is 450000000 after 550000000? Is it on purpose? If not intended
please sort by frequency.
> + opp-hz = /bits/ 64 <450000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <4068000>;
> + };
> +
> + opp-315000000 {
> + opp-hz = /bits/ 64 <315000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <1804000>;
> + };
> + };
> + };
> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support
2021-07-28 11:54 ` Akhil P Oommen
@ 2021-07-29 17:29 ` Stephen Boyd
-1 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:29 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm
Cc: Jordan Crouse, Douglas Anderson, Rob Clark, Matthias Kaehlcke,
Jonathan Marek, Andy Gross, linux-kernel
Quoting Akhil P Oommen (2021-07-28 04:54:02)
> From: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
>
> Add cooling-cells property and the cooling maps for the gpu thermal
> zones to support GPU thermal cooling.
>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support
@ 2021-07-29 17:29 ` Stephen Boyd
0 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:29 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm
Cc: Jonathan Marek, linux-kernel, Douglas Anderson, Jordan Crouse,
Andy Gross, Matthias Kaehlcke
Quoting Akhil P Oommen (2021-07-28 04:54:02)
> From: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
>
> Add cooling-cells property and the cooling maps for the gpu thermal
> zones to support GPU thermal cooling.
>
> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
2021-07-29 17:19 ` Stephen Boyd
@ 2021-07-29 17:35 ` Rob Clark
-1 siblings, 0 replies; 12+ messages in thread
From: Rob Clark @ 2021-07-29 17:35 UTC (permalink / raw)
To: Stephen Boyd
Cc: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm, Jordan Crouse,
Douglas Anderson, Matthias Kaehlcke, Jonathan Marek, Andy Gross,
Linux Kernel Mailing List
On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Akhil P Oommen (2021-07-28 04:54:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 029723a..c88f366 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -592,6 +593,85 @@
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > + gpu@3d00000 {
> > + compatible = "qcom,adreno-635.0", "qcom,adreno";
> > + #stream-id-cells = <16>;
> > + reg = <0 0x03d00000 0 0x40000>,
> > + <0 0x03d9e000 0 0x1000>,
> > + <0 0x03d61000 0 0x800>;
> > + reg-names = "kgsl_3d0_reg_memory",
> > + "cx_mem",
> > + "cx_dbgc";
> > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > + iommus = <&adreno_smmu 0 0x401>;
> > + operating-points-v2 = <&gpu_opp_table>;
> > + qcom,gmu = <&gmu>;
> > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "gfx-mem";
> > +
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-550000000 {
> > + opp-hz = /bits/ 64 <550000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > + opp-peak-kBps = <6832000>;
> > + };
> > +
> > + opp-450000000 {
>
> Why is 450000000 after 550000000? Is it on purpose? If not intended
> please sort by frequency.
We've used descending order, at least for gpu opp table, on other
gens, fwiw.. not sure if that just means we were doing it wrong
previously
BR,
-R
>
> > + opp-hz = /bits/ 64 <450000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> > + opp-peak-kBps = <4068000>;
> > + };
> > +
> > + opp-315000000 {
> > + opp-hz = /bits/ 64 <315000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> > + opp-peak-kBps = <1804000>;
> > + };
> > + };
> > + };
> > +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-07-29 17:35 ` Rob Clark
0 siblings, 0 replies; 12+ messages in thread
From: Rob Clark @ 2021-07-29 17:35 UTC (permalink / raw)
To: Stephen Boyd
Cc: OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Douglas Anderson, Jonathan Marek, freedreno, Akhil P Oommen,
dri-devel, Bjorn Andersson, Rob Herring, Andy Gross,
linux-arm-msm, Jordan Crouse, Manaf Meethalavalappu Pallikunhi,
Matthias Kaehlcke, Linux Kernel Mailing List
On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd <swboyd@chromium.org> wrote:
>
> Quoting Akhil P Oommen (2021-07-28 04:54:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 029723a..c88f366 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -592,6 +593,85 @@
> > qcom,bcm-voters = <&apps_bcm_voter>;
> > };
> >
> > + gpu@3d00000 {
> > + compatible = "qcom,adreno-635.0", "qcom,adreno";
> > + #stream-id-cells = <16>;
> > + reg = <0 0x03d00000 0 0x40000>,
> > + <0 0x03d9e000 0 0x1000>,
> > + <0 0x03d61000 0 0x800>;
> > + reg-names = "kgsl_3d0_reg_memory",
> > + "cx_mem",
> > + "cx_dbgc";
> > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > + iommus = <&adreno_smmu 0 0x401>;
> > + operating-points-v2 = <&gpu_opp_table>;
> > + qcom,gmu = <&gmu>;
> > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> > + interconnect-names = "gfx-mem";
> > +
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-550000000 {
> > + opp-hz = /bits/ 64 <550000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > + opp-peak-kBps = <6832000>;
> > + };
> > +
> > + opp-450000000 {
>
> Why is 450000000 after 550000000? Is it on purpose? If not intended
> please sort by frequency.
We've used descending order, at least for gpu opp table, on other
gens, fwiw.. not sure if that just means we were doing it wrong
previously
BR,
-R
>
> > + opp-hz = /bits/ 64 <450000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> > + opp-peak-kBps = <4068000>;
> > + };
> > +
> > + opp-315000000 {
> > + opp-hz = /bits/ 64 <315000000>;
> > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> > + opp-peak-kBps = <1804000>;
> > + };
> > + };
> > + };
> > +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
2021-07-29 17:35 ` Rob Clark
@ 2021-07-29 17:39 ` Stephen Boyd
-1 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:39 UTC (permalink / raw)
To: Rob Clark
Cc: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm, Jordan Crouse,
Douglas Anderson, Matthias Kaehlcke, Jonathan Marek, Andy Gross,
Linux Kernel Mailing List
Quoting Rob Clark (2021-07-29 10:35:32)
> On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd <swboyd@chromium.org> wrote:
> >
> >
> > Why is 450000000 after 550000000? Is it on purpose? If not intended
> > please sort by frequency.
>
> We've used descending order, at least for gpu opp table, on other
> gens, fwiw.. not sure if that just means we were doing it wrong
> previously
>
Ah I missed that. I don't think one way or the other is mandated, but
we're already sorting other OPP tables in the qcom dtsi files in
ascending so this is the only one that is different.
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-07-29 17:39 ` Stephen Boyd
0 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2021-07-29 17:39 UTC (permalink / raw)
To: Rob Clark
Cc: OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Douglas Anderson, Jonathan Marek, freedreno, Akhil P Oommen,
dri-devel, Bjorn Andersson, Rob Herring, Andy Gross,
linux-arm-msm, Jordan Crouse, Manaf Meethalavalappu Pallikunhi,
Matthias Kaehlcke, Linux Kernel Mailing List
Quoting Rob Clark (2021-07-29 10:35:32)
> On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd <swboyd@chromium.org> wrote:
> >
> >
> > Why is 450000000 after 550000000? Is it on purpose? If not intended
> > please sort by frequency.
>
> We've used descending order, at least for gpu opp table, on other
> gens, fwiw.. not sure if that just means we were doing it wrong
> previously
>
Ah I missed that. I don't think one way or the other is mandated, but
we're already sorting other OPP tables in the qcom dtsi files in
ascending so this is the only one that is different.
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-07-29 17:39 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-28 11:54 [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support Akhil P Oommen
2021-07-28 11:54 ` Akhil P Oommen
2021-07-28 11:54 ` [PATCH v3 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support Akhil P Oommen
2021-07-28 11:54 ` Akhil P Oommen
2021-07-29 17:29 ` Stephen Boyd
2021-07-29 17:29 ` Stephen Boyd
2021-07-29 17:19 ` [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support Stephen Boyd
2021-07-29 17:19 ` Stephen Boyd
2021-07-29 17:35 ` Rob Clark
2021-07-29 17:35 ` Rob Clark
2021-07-29 17:39 ` Stephen Boyd
2021-07-29 17:39 ` Stephen Boyd
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