* [PATCH 0/4] Remove CNL - for drm-intel-gt-next @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel This the part of https://patchwork.freedesktop.org/series/93056/ that should go through drm-intel-gt-next branch. Lucas De Marchi (4): drm/i915/gt: remove explicit CNL handling from intel_mocs.c drm/i915/gt: remove explicit CNL handling from intel_sseu.c drm/i915/gt: rename CNL references in intel_engine.h drm/i915/gt: remove GRAPHICS_VER == 10 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 +-- drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 - drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 +-- drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--------- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ------------------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- 14 files changed, 27 insertions(+), 149 deletions(-) -- 2.31.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 0/4] Remove CNL - for drm-intel-gt-next @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel This the part of https://patchwork.freedesktop.org/series/93056/ that should go through drm-intel-gt-next branch. Lucas De Marchi (4): drm/i915/gt: remove explicit CNL handling from intel_mocs.c drm/i915/gt: remove explicit CNL handling from intel_sseu.c drm/i915/gt: rename CNL references in intel_engine.h drm/i915/gt: remove GRAPHICS_VER == 10 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 +-- drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 - drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 +-- drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--------- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ------------------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 4 +- 14 files changed, 27 insertions(+), 149 deletions(-) -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/4] drm/i915/gt: remove explicit CNL handling from intel_mocs.c 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi @ 2021-07-28 22:03 ` Lucas De Marchi -1 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Only one reference to CNL that is not needed, but code is the same for GEN9_BC, so leave the code around and just remove the special case for CNL. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 17848807f111..582c4423b95d 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->size = ARRAY_SIZE(icl_mocs_table); table->table = icl_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; - } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) { + } else if (IS_GEN9_BC(i915)) { table->size = ARRAY_SIZE(skl_mocs_table); table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->table = skl_mocs_table; -- 2.31.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915/gt: remove explicit CNL handling from intel_mocs.c @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Only one reference to CNL that is not needed, but code is the same for GEN9_BC, so leave the code around and just remove the special case for CNL. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 17848807f111..582c4423b95d 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, table->size = ARRAY_SIZE(icl_mocs_table); table->table = icl_mocs_table; table->n_entries = GEN9_NUM_MOCS_ENTRIES; - } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) { + } else if (IS_GEN9_BC(i915)) { table->size = ARRAY_SIZE(skl_mocs_table); table->n_entries = GEN9_NUM_MOCS_ENTRIES; table->table = skl_mocs_table; -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/4] drm/i915/gt: remove explicit CNL handling from intel_sseu.c 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi @ 2021-07-28 22:03 ` Lucas De Marchi -1 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel CNL is the only platform with GRAPHICS_VER == 10. With its removal we don't need to handle that version anymore. Also we can now reduce the max number of slices: the call to intel_sseu_set_info() with the highest number of slices comes from SKL and BDW with 3 slices. Recent platforms actually increase the number of subslices so the number of slices remain 1. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ---------------------------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- 2 files changed, 1 insertion(+), 80 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 367fd44b81c8..9542c3f3822a 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -188,83 +188,6 @@ static void gen11_sseu_info_init(struct intel_gt *gt) sseu->has_eu_pg = 1; } -static void gen10_sseu_info_init(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - struct sseu_dev_info *sseu = >->info.sseu; - const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - const int eu_mask = 0xff; - u32 subslice_mask, eu_en; - int s, ss; - - intel_sseu_set_info(sseu, 6, 4, 8); - - sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> - GEN10_F2_S_ENA_SHIFT; - - /* Slice0 */ - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); - for (ss = 0; ss < sseu->max_subslices; ss++) - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); - /* Slice1 */ - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); - /* Slice2 */ - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); - /* Slice3 */ - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); - /* Slice4 */ - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); - /* Slice5 */ - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); - - subslice_mask = (1 << 4) - 1; - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> - GEN10_F2_SS_DIS_SHIFT); - - for (s = 0; s < sseu->max_slices; s++) { - u32 subslice_mask_with_eus = subslice_mask; - - for (ss = 0; ss < sseu->max_subslices; ss++) { - if (sseu_get_eus(sseu, s, ss) == 0) - subslice_mask_with_eus &= ~BIT(ss); - } - - /* - * Slice0 can have up to 3 subslices, but there are only 2 in - * slice1/2. - */ - intel_sseu_set_subslices(sseu, s, s == 0 ? - subslice_mask_with_eus : - subslice_mask_with_eus & 0x3); - } - - sseu->eu_total = compute_eu_total(sseu); - - /* - * CNL is expected to always have a uniform distribution - * of EU across subslices with the exception that any one - * EU in any one subslice may be fused off for die - * recovery. - */ - sseu->eu_per_subslice = - intel_sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : - 0; - - /* No restrictions on Power Gating */ - sseu->has_slice_pg = 1; - sseu->has_subslice_pg = 1; - sseu->has_eu_pg = 1; -} - static void cherryview_sseu_info_init(struct intel_gt *gt) { struct sseu_dev_info *sseu = >->info.sseu; @@ -592,8 +515,6 @@ void intel_sseu_info_init(struct intel_gt *gt) bdw_sseu_info_init(gt); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_info_init(gt); - else if (GRAPHICS_VER(i915) == 10) - gen10_sseu_info_init(gt); else if (GRAPHICS_VER(i915) == 11) gen11_sseu_info_init(gt); else if (GRAPHICS_VER(i915) >= 12) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 4cd1a8a7298a..8d85ec05f610 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -15,7 +15,7 @@ struct drm_i915_private; struct intel_gt; struct drm_printer; -#define GEN_MAX_SLICES (6) /* CNL upper bound */ +#define GEN_MAX_SLICES (3) /* SKL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) -- 2.31.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/gt: remove explicit CNL handling from intel_sseu.c @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel CNL is the only platform with GRAPHICS_VER == 10. With its removal we don't need to handle that version anymore. Also we can now reduce the max number of slices: the call to intel_sseu_set_info() with the highest number of slices comes from SKL and BDW with 3 slices. Recent platforms actually increase the number of subslices so the number of slices remain 1. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ---------------------------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- 2 files changed, 1 insertion(+), 80 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 367fd44b81c8..9542c3f3822a 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -188,83 +188,6 @@ static void gen11_sseu_info_init(struct intel_gt *gt) sseu->has_eu_pg = 1; } -static void gen10_sseu_info_init(struct intel_gt *gt) -{ - struct intel_uncore *uncore = gt->uncore; - struct sseu_dev_info *sseu = >->info.sseu; - const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - const int eu_mask = 0xff; - u32 subslice_mask, eu_en; - int s, ss; - - intel_sseu_set_info(sseu, 6, 4, 8); - - sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> - GEN10_F2_S_ENA_SHIFT; - - /* Slice0 */ - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); - for (ss = 0; ss < sseu->max_subslices; ss++) - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); - /* Slice1 */ - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); - /* Slice2 */ - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); - /* Slice3 */ - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); - /* Slice4 */ - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); - /* Slice5 */ - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); - - subslice_mask = (1 << 4) - 1; - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> - GEN10_F2_SS_DIS_SHIFT); - - for (s = 0; s < sseu->max_slices; s++) { - u32 subslice_mask_with_eus = subslice_mask; - - for (ss = 0; ss < sseu->max_subslices; ss++) { - if (sseu_get_eus(sseu, s, ss) == 0) - subslice_mask_with_eus &= ~BIT(ss); - } - - /* - * Slice0 can have up to 3 subslices, but there are only 2 in - * slice1/2. - */ - intel_sseu_set_subslices(sseu, s, s == 0 ? - subslice_mask_with_eus : - subslice_mask_with_eus & 0x3); - } - - sseu->eu_total = compute_eu_total(sseu); - - /* - * CNL is expected to always have a uniform distribution - * of EU across subslices with the exception that any one - * EU in any one subslice may be fused off for die - * recovery. - */ - sseu->eu_per_subslice = - intel_sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : - 0; - - /* No restrictions on Power Gating */ - sseu->has_slice_pg = 1; - sseu->has_subslice_pg = 1; - sseu->has_eu_pg = 1; -} - static void cherryview_sseu_info_init(struct intel_gt *gt) { struct sseu_dev_info *sseu = >->info.sseu; @@ -592,8 +515,6 @@ void intel_sseu_info_init(struct intel_gt *gt) bdw_sseu_info_init(gt); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_info_init(gt); - else if (GRAPHICS_VER(i915) == 10) - gen10_sseu_info_init(gt); else if (GRAPHICS_VER(i915) == 11) gen11_sseu_info_init(gt); else if (GRAPHICS_VER(i915) >= 12) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index 4cd1a8a7298a..8d85ec05f610 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -15,7 +15,7 @@ struct drm_i915_private; struct intel_gt; struct drm_printer; -#define GEN_MAX_SLICES (6) /* CNL upper bound */ +#define GEN_MAX_SLICES (3) /* SKL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/4] drm/i915/gt: rename CNL references in intel_engine.h 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi @ 2021-07-28 22:03 ` Lucas De Marchi -1 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel With the removal of CNL, let's consider ICL as the first platform using that index. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index c2a5640ae055..87579affb952 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) #define I915_HWS_CSB_BUF0_INDEX 0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f -#define CNL_HWS_CSB_WRITE_INDEX 0x2f +#define ICL_HWS_CSB_WRITE_INDEX 0x2f void intel_engine_stop(struct intel_engine_cs *engine); void intel_engine_cleanup(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d22cea642627..65000b57ddb6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1958,8 +1958,8 @@ int remap_io_sg(struct vm_area_struct *vma, static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) { - if (GRAPHICS_VER(i915) >= 10) - return CNL_HWS_CSB_WRITE_INDEX; + if (GRAPHICS_VER(i915) >= 11) + return ICL_HWS_CSB_WRITE_INDEX; else return I915_HWS_CSB_WRITE_INDEX; } -- 2.31.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/gt: rename CNL references in intel_engine.h @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel With the removal of CNL, let's consider ICL as the first platform using that index. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index c2a5640ae055..87579affb952 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) #define I915_HWS_CSB_BUF0_INDEX 0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f -#define CNL_HWS_CSB_WRITE_INDEX 0x2f +#define ICL_HWS_CSB_WRITE_INDEX 0x2f void intel_engine_stop(struct intel_engine_cs *engine); void intel_engine_cleanup(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d22cea642627..65000b57ddb6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1958,8 +1958,8 @@ int remap_io_sg(struct vm_area_struct *vma, static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) { - if (GRAPHICS_VER(i915) >= 10) - return CNL_HWS_CSB_WRITE_INDEX; + if (GRAPHICS_VER(i915) >= 11) + return ICL_HWS_CSB_WRITE_INDEX; else return I915_HWS_CSB_WRITE_INDEX; } -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/4] drm/i915/gt: remove GRAPHICS_VER == 10 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi @ 2021-07-28 22:03 ` Lucas De Marchi -1 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 -- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +-- drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +------------------ drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +-- 9 files changed, 22 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index 4270b5a34a83..d6f5836396f8 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused) max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n", @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data) intel_gpu_freq(rps, (gpu_freq * (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, ((ia_freq >> 8) & 0xff) * 100); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index dea0e522c5c7..0d9105a31d84 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -35,7 +35,6 @@ #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) -#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) @@ -186,8 +185,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) case 12: case 11: return GEN11_LR_CONTEXT_RENDER_SIZE; - case 10: - return GEN10_LR_CONTEXT_RENDER_SIZE; case 9: return GEN9_LR_CONTEXT_RENDER_SIZE; case 8: diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 9d445ad9a342..de3ac58fceec 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; /* - * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range + * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range * will be dropped. For WC mappings in general we have 64 byte burst * writes when the WC buffer is flushed, so we can't use it, but have to * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10) + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11) ggtt->gsm = ioremap(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 9f0e729d2d15..3513d6f90747 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -24,8 +24,8 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore) return base_freq + frac_freq; } -static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore, - u32 rpm_config_reg) +static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore, + u32 rpm_config_reg) { u32 f19_2_mhz = 19200000; u32 f24_mhz = 24000000; @@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore) } else { u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); - if (GRAPHICS_VER(uncore->i915) <= 10) - freq = gen10_get_crystal_clock_freq(uncore, c0); - else + if (GRAPHICS_VER(uncore->i915) >= 11) freq = gen11_get_crystal_clock_freq(uncore, c0); + else + freq = gen9_get_crystal_clock_freq(uncore, c0); /* * Now figure out how the command stream's timestamp diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index f7e0352edb62..e137dd32b5b8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore) intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); } -static void cnl_setup_private_ppat(struct intel_uncore *uncore) +static void icl_setup_private_ppat(struct intel_uncore *uncore) { intel_uncore_write(uncore, GEN10_PAT_INDEX(0), @@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore) if (GRAPHICS_VER(i915) >= 12) tgl_setup_private_ppat(uncore); - else if (GRAPHICS_VER(i915) >= 10) - cnl_setup_private_ppat(uncore); + else if (GRAPHICS_VER(i915) >= 11) + icl_setup_private_ppat(uncore); else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) chv_setup_private_ppat(uncore); else diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c3f5bec8ae15..bb4af4977920 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs, if (close) { /* Close the batch; used mainly by live_lrc_layout() */ *regs = MI_BATCH_BUFFER_END; - if (GRAPHICS_VER(engine->i915) >= 10) + if (GRAPHICS_VER(engine->i915) >= 11) *regs |= BIT(0); } } @@ -653,8 +653,6 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine) return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 11: return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - case 10: - return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 9: return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 8: @@ -1448,40 +1446,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) return batch; } -static u32 * -gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) -{ - int i; - - /* - * WaPipeControlBefore3DStateSamplePattern: cnl - * - * Ensure the engine is idle prior to programming a - * 3DSTATE_SAMPLE_PATTERN during a context restore. - */ - batch = gen8_emit_pipe_control(batch, - PIPE_CONTROL_CS_STALL, - 0); - /* - * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for - * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in - * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is - * confusing. Since gen8_emit_pipe_control() already advances the - * batch by 6 dwords, we advance the other 10 here, completing a - * cacheline. It's not clear if the workaround requires this padding - * before other commands, or if it's just the regular padding we would - * already have for the workaround bb, so leave it here for now. - */ - for (i = 0; i < 10; i++) - *batch++ = MI_NOOP; - - /* Pad to end of cacheline */ - while ((unsigned long)batch % CACHELINE_BYTES) - *batch++ = MI_NOOP; - - return batch; -} - #define CTX_WA_BB_SIZE (PAGE_SIZE) static int lrc_create_wa_ctx(struct intel_engine_cs *engine) @@ -1534,10 +1498,6 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine) case 12: case 11: return; - case 10: - wa_bb_fn[0] = gen10_init_indirectctx_bb; - wa_bb_fn[1] = NULL; - break; case 9: wa_bb_fn[0] = gen9_init_indirectctx_bb; wa_bb_fn[1] = NULL; diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 259d7eb4e165..a7d13fe35b2e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) enum intel_engine_id id; /* 2b: Program RC6 thresholds.*/ - if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) { + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 0c8e7f2b06f0..bc0f7d8baa84 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps) rps->efficient_freq = rps->rp1_freq; if (IS_HASWELL(i915) || IS_BROADWELL(i915) || - IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { u32 ddcc_status = 0; if (sandybridge_pcode_read(i915, @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps) rps->max_freq); } - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Store the frequency values in 16.66 MHZ units, which is * the natural hardware unit for SKL */ diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c index 714fe8495775..5e7b09c5e36f 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c @@ -50,7 +50,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt, #undef SS_MAX } -static void gen10_sseu_device_status(struct intel_gt *gt, +static void gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) { #define SS_MAX 6 @@ -267,8 +267,8 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt) bdw_sseu_device_status(gt, &sseu); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_device_status(gt, &sseu); - else if (GRAPHICS_VER(i915) >= 10) - gen10_sseu_device_status(gt, &sseu); + else if (GRAPHICS_VER(i915) >= 11) + gen11_sseu_device_status(gt, &sseu); } i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu); -- 2.31.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/gt: remove GRAPHICS_VER == 10 @ 2021-07-28 22:03 ` Lucas De Marchi 0 siblings, 0 replies; 15+ messages in thread From: Lucas De Marchi @ 2021-07-28 22:03 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 -- drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 ++--- drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +-- drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +------------------ drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +-- 9 files changed, 22 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index 4270b5a34a83..d6f5836396f8 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused) max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1); + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n", @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data) intel_gpu_freq(rps, (gpu_freq * (IS_GEN9_BC(i915) || - GRAPHICS_VER(i915) >= 10 ? + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, ((ia_freq >> 8) & 0xff) * 100); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index dea0e522c5c7..0d9105a31d84 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -35,7 +35,6 @@ #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) -#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE) #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE) #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE) @@ -186,8 +185,6 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) case 12: case 11: return GEN11_LR_CONTEXT_RENDER_SIZE; - case 10: - return GEN10_LR_CONTEXT_RENDER_SIZE; case 9: return GEN9_LR_CONTEXT_RENDER_SIZE; case 8: diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 9d445ad9a342..de3ac58fceec 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -826,13 +826,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; /* - * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range + * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range * will be dropped. For WC mappings in general we have 64 byte burst * writes when the WC buffer is flushed, so we can't use it, but have to * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10) + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11) ggtt->gsm = ioremap(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 9f0e729d2d15..3513d6f90747 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -24,8 +24,8 @@ static u32 read_reference_ts_freq(struct intel_uncore *uncore) return base_freq + frac_freq; } -static u32 gen10_get_crystal_clock_freq(struct intel_uncore *uncore, - u32 rpm_config_reg) +static u32 gen9_get_crystal_clock_freq(struct intel_uncore *uncore, + u32 rpm_config_reg) { u32 f19_2_mhz = 19200000; u32 f24_mhz = 24000000; @@ -128,10 +128,10 @@ static u32 read_clock_frequency(struct intel_uncore *uncore) } else { u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); - if (GRAPHICS_VER(uncore->i915) <= 10) - freq = gen10_get_crystal_clock_freq(uncore, c0); - else + if (GRAPHICS_VER(uncore->i915) >= 11) freq = gen11_get_crystal_clock_freq(uncore, c0); + else + freq = gen9_get_crystal_clock_freq(uncore, c0); /* * Now figure out how the command stream's timestamp diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index f7e0352edb62..e137dd32b5b8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -426,7 +426,7 @@ static void tgl_setup_private_ppat(struct intel_uncore *uncore) intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); } -static void cnl_setup_private_ppat(struct intel_uncore *uncore) +static void icl_setup_private_ppat(struct intel_uncore *uncore) { intel_uncore_write(uncore, GEN10_PAT_INDEX(0), @@ -526,8 +526,8 @@ void setup_private_pat(struct intel_uncore *uncore) if (GRAPHICS_VER(i915) >= 12) tgl_setup_private_ppat(uncore); - else if (GRAPHICS_VER(i915) >= 10) - cnl_setup_private_ppat(uncore); + else if (GRAPHICS_VER(i915) >= 11) + icl_setup_private_ppat(uncore); else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) chv_setup_private_ppat(uncore); else diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c3f5bec8ae15..bb4af4977920 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs, if (close) { /* Close the batch; used mainly by live_lrc_layout() */ *regs = MI_BATCH_BUFFER_END; - if (GRAPHICS_VER(engine->i915) >= 10) + if (GRAPHICS_VER(engine->i915) >= 11) *regs |= BIT(0); } } @@ -653,8 +653,6 @@ lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine) return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 11: return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - case 10: - return GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 9: return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; case 8: @@ -1448,40 +1446,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) return batch; } -static u32 * -gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) -{ - int i; - - /* - * WaPipeControlBefore3DStateSamplePattern: cnl - * - * Ensure the engine is idle prior to programming a - * 3DSTATE_SAMPLE_PATTERN during a context restore. - */ - batch = gen8_emit_pipe_control(batch, - PIPE_CONTROL_CS_STALL, - 0); - /* - * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for - * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in - * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is - * confusing. Since gen8_emit_pipe_control() already advances the - * batch by 6 dwords, we advance the other 10 here, completing a - * cacheline. It's not clear if the workaround requires this padding - * before other commands, or if it's just the regular padding we would - * already have for the workaround bb, so leave it here for now. - */ - for (i = 0; i < 10; i++) - *batch++ = MI_NOOP; - - /* Pad to end of cacheline */ - while ((unsigned long)batch % CACHELINE_BYTES) - *batch++ = MI_NOOP; - - return batch; -} - #define CTX_WA_BB_SIZE (PAGE_SIZE) static int lrc_create_wa_ctx(struct intel_engine_cs *engine) @@ -1534,10 +1498,6 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine) case 12: case 11: return; - case 10: - wa_bb_fn[0] = gen10_init_indirectctx_bb; - wa_bb_fn[1] = NULL; - break; case 9: wa_bb_fn[0] = gen9_init_indirectctx_bb; wa_bb_fn[1] = NULL; diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 259d7eb4e165..a7d13fe35b2e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) enum intel_engine_id id; /* 2b: Program RC6 thresholds.*/ - if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) { + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) { set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150); } else if (IS_SKYLAKE(rc6_to_i915(rc6))) { diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 0c8e7f2b06f0..bc0f7d8baa84 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps) rps->efficient_freq = rps->rp1_freq; if (IS_HASWELL(i915) || IS_BROADWELL(i915) || - IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { u32 ddcc_status = 0; if (sandybridge_pcode_read(i915, @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps) rps->max_freq); } - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) { + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) { /* Store the frequency values in 16.66 MHZ units, which is * the natural hardware unit for SKL */ diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c index 714fe8495775..5e7b09c5e36f 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c @@ -50,7 +50,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt, #undef SS_MAX } -static void gen10_sseu_device_status(struct intel_gt *gt, +static void gen11_sseu_device_status(struct intel_gt *gt, struct sseu_dev_info *sseu) { #define SS_MAX 6 @@ -267,8 +267,8 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt) bdw_sseu_device_status(gt, &sseu); else if (GRAPHICS_VER(i915) == 9) gen9_sseu_device_status(gt, &sseu); - else if (GRAPHICS_VER(i915) >= 10) - gen10_sseu_device_status(gt, &sseu); + else if (GRAPHICS_VER(i915) >= 11) + gen11_sseu_device_status(gt, &sseu); } i915_print_sseu_info(m, false, HAS_POOLED_EU(i915), &sseu); -- 2.31.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remove CNL - for drm-intel-gt-next 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi ` (4 preceding siblings ...) (?) @ 2021-07-28 23:29 ` Patchwork -1 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2021-07-28 23:29 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Remove CNL - for drm-intel-gt-next URL : https://patchwork.freedesktop.org/series/93143/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1900:21: expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1900:21: got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1410:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'xehp_fwtable_write8' - different lock contexts for basic block +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +./include/linux/stddef.h:17:9: this was the original definition +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined +/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Remove CNL - for drm-intel-gt-next 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi ` (5 preceding siblings ...) (?) @ 2021-07-28 23:56 ` Patchwork -1 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2021-07-28 23:56 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 3175 bytes --] == Series Details == Series: Remove CNL - for drm-intel-gt-next URL : https://patchwork.freedesktop.org/series/93143/ State : success == Summary == CI Bug Log - changes from CI_DRM_10415 -> Patchwork_20730 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/index.html Known issues ------------ Here are the changes found in Patchwork_20730 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@execlists: - fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([i915#2782] / [i915#2940]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/fi-bsw-nick/igt@i915_selftest@live@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/fi-bsw-nick/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@gt_pm: - fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4] ([i915#2291]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html * igt@runner@aborted: - fi-bsw-nick: NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#1436]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/fi-bsw-nick/igt@runner@aborted.html #### Possible fixes #### * igt@i915_module_load@reload: - fi-kbl-soraka: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/fi-kbl-soraka/igt@i915_module_load@reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/fi-kbl-soraka/igt@i915_module_load@reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 Participating hosts (43 -> 35) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus fi-tgl-y bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10415 -> Patchwork_20730 CI-20190529: 20190529 CI_DRM_10415: 457209baa84d04e17ce648a12733a32809717494 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6155: 4b51398dcd7559012b85776e7353d516ff1e6ce6 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20730: 014439ad9703e6ec926c6c565ccdb17018afdb4f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 014439ad9703 drm/i915/gt: remove GRAPHICS_VER == 10 3bc9dcd882d0 drm/i915/gt: rename CNL references in intel_engine.h b9487c245786 drm/i915/gt: remove explicit CNL handling from intel_sseu.c 53e1ddaa5930 drm/i915/gt: remove explicit CNL handling from intel_mocs.c == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/index.html [-- Attachment #1.2: Type: text/html, Size: 3870 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Remove CNL - for drm-intel-gt-next 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi ` (6 preceding siblings ...) (?) @ 2021-07-29 5:09 ` Patchwork -1 siblings, 0 replies; 15+ messages in thread From: Patchwork @ 2021-07-29 5:09 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx [-- Attachment #1.1: Type: text/plain, Size: 30257 bytes --] == Series Details == Series: Remove CNL - for drm-intel-gt-next URL : https://patchwork.freedesktop.org/series/93143/ State : success == Summary == CI Bug Log - changes from CI_DRM_10415_full -> Patchwork_20730_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_20730_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@runner@aborted: - {shard-rkl}: ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5]) ([i915#2029] / [i915#3002] / [i915#3621] / [i915#3810]) -> ([FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10]) ([i915#3002] / [i915#3621] / [i915#3810]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-1/igt@runner@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-6/igt@runner@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-6/igt@runner@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@runner@aborted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-1/igt@runner@aborted.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-1/igt@runner@aborted.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-5/igt@runner@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-5/igt@runner@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-2/igt@runner@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_20730_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@display-3x: - shard-glk: NOTRUN -> [SKIP][11] ([fdo#109271]) +39 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@feature_discovery@display-3x.html * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][12] ([i915#3002]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl2/igt@gem_create@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html - shard-apl: NOTRUN -> [DMESG-WARN][15] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html * igt@gem_ctx_persistence@engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1099]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-snb7/igt@gem_ctx_persistence@engines-hostile-preempt.html * igt@gem_ctx_persistence@smoketest: - shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2896]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb1/igt@gem_ctx_persistence@smoketest.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb1/igt@gem_ctx_persistence@smoketest.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb1/igt@gem_exec_fair@basic-none@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb1/igt@gem_exec_fair@basic-none@rcs0.html - shard-glk: [PASS][23] -> [FAIL][24] ([i915#2842]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk7/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][25] ([i915#2842]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][26] -> [FAIL][27] ([i915#2842]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][28] -> [FAIL][29] ([i915#2849]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-iclb: NOTRUN -> [SKIP][30] ([i915#2190]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@gem_huc_copy@huc-copy.html * igt@gem_mmap_gtt@cpuset-medium-copy: - shard-glk: [PASS][31] -> [FAIL][32] ([i915#1888] / [i915#307]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk8/igt@gem_mmap_gtt@cpuset-medium-copy.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk1/igt@gem_mmap_gtt@cpuset-medium-copy.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][33] ([i915#2658]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl8/igt@gem_pread@exhaustion.html - shard-snb: NOTRUN -> [WARN][34] ([i915#2658]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-snb7/igt@gem_pread@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][35] ([i915#2658]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl6/igt@gem_pwrite@basic-exhaustion.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-iclb: NOTRUN -> [SKIP][36] ([i915#768]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-iclb: NOTRUN -> [SKIP][37] ([i915#3297]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][38] -> [DMESG-WARN][39] ([i915#1436] / [i915#716]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-skl9/igt@gen9_exec_parse@allowed-single.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl10/igt@gen9_exec_parse@allowed-single.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#1937]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_rpm@basic-rte: - shard-glk: NOTRUN -> [FAIL][41] ([i915#579]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@i915_pm_rpm@basic-rte.html * igt@i915_pm_rpm@gem-execbuf: - shard-iclb: NOTRUN -> [SKIP][42] ([i915#579]) +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@i915_pm_rpm@gem-execbuf.html * igt@i915_suspend@forcewake: - shard-apl: [PASS][43] -> [DMESG-WARN][44] ([i915#180]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-apl3/igt@i915_suspend@forcewake.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl6/igt@i915_suspend@forcewake.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: NOTRUN -> [DMESG-WARN][45] ([i915#118] / [i915#95]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_big_fb@x-tiled-32bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][46] ([fdo#110725] / [fdo#111614]) +1 similar issue [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3777]) +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-iclb: [PASS][48] -> [DMESG-WARN][49] ([i915#3621]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111615]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278]) +12 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@dp-audio-edid: - shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_chamelium@dp-audio-edid.html * igt@kms_chamelium@dp-crc-multiple: - shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_chamelium@dp-crc-multiple.html * igt@kms_chamelium@hdmi-crc-nonplanar-formats: - shard-glk: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +3 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +26 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl8/igt@kms_chamelium@hdmi-edid-change-during-suspend.html * igt@kms_chamelium@hdmi-hpd-storm-disable: - shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl6/igt@kms_chamelium@hdmi-hpd-storm-disable.html * igt@kms_color_chamelium@pipe-b-ctm-negative: - shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +8 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-snb6/igt@kms_color_chamelium@pipe-b-ctm-negative.html * igt@kms_content_protection@dp-mst-type-1: - shard-tglb: NOTRUN -> [SKIP][59] ([i915#3116]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_content_protection@uevent: - shard-apl: NOTRUN -> [FAIL][60] ([i915#2105]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl8/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen: - shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271]) +65 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html * igt@kms_cursor_crc@pipe-c-cursor-512x170-random: - shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109278] / [fdo#109279]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-c-cursor-max-size-sliding: - shard-tglb: NOTRUN -> [SKIP][63] ([i915#3359]) +4 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-max-size-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen: - shard-tglb: NOTRUN -> [SKIP][64] ([fdo#109279] / [i915#3359]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][65] -> [FAIL][66] ([i915#2346]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_dp_tiled_display@basic-test-pattern: - shard-tglb: NOTRUN -> [SKIP][67] ([i915#426]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_dp_tiled_display@basic-test-pattern.html * igt@kms_flip@2x-dpms-vs-vblank-race: - shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109274]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb8/igt@kms_flip@2x-dpms-vs-vblank-race.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][69] -> [FAIL][70] ([i915#2122]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-suspend@a-edp1: - shard-skl: [PASS][71] -> [DMESG-WARN][72] ([i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-skl5/igt@kms_flip@flip-vs-suspend@a-edp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][73] -> [FAIL][74] ([i915#2122]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-tglb: NOTRUN -> [SKIP][75] ([fdo#111825]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render: - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109280]) +7 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite: - shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +5 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#533]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265]) +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-glk: NOTRUN -> [FAIL][80] ([i915#265]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][81] -> [FAIL][82] ([fdo#108145] / [i915#265]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-x: - shard-iclb: NOTRUN -> [SKIP][83] ([i915#3536]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3: - shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5: - shard-iclb: NOTRUN -> [SKIP][86] ([i915#658]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +6 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2: - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-skl9/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109441]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html - shard-tglb: NOTRUN -> [FAIL][90] ([i915#132] / [i915#3467]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@kms_psr@psr2_cursor_blt.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][91] -> [SKIP][92] ([fdo#109441]) +1 similar issue [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_psr@suspend: - shard-snb: NOTRUN -> [SKIP][93] ([fdo#109271]) +146 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-snb6/igt@kms_psr@suspend.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271]) +318 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl6/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_vblank@pipe-d-wait-idle: - shard-apl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#533]) +3 similar issues [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html * igt@kms_writeback@writeback-fb-id: - shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2437]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl2/igt@kms_writeback@writeback-fb-id.html * igt@perf@polling-parameterized: - shard-glk: [PASS][97] -> [FAIL][98] ([i915#1542]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk6/igt@perf@polling-parameterized.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk4/igt@perf@polling-parameterized.html * igt@perf_pmu@rc6-suspend: - shard-kbl: [PASS][99] -> [INCOMPLETE][100] ([i915#155] / [i915#794]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-kbl7/igt@perf_pmu@rc6-suspend.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-kbl3/igt@perf_pmu@rc6-suspend.html * igt@prime_nv_api@i915_nv_double_export: - shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109291]) +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@prime_nv_api@i915_nv_double_export.html * igt@prime_nv_pcopy@test3_3: - shard-tglb: NOTRUN -> [SKIP][102] ([fdo#109291]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@prime_nv_pcopy@test3_3.html * igt@sysfs_clients@fair-1: - shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2994]) +7 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-apl7/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@sema-25: - shard-glk: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#2994]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk5/igt@sysfs_clients@sema-25.html * igt@sysfs_clients@sema-50: - shard-iclb: NOTRUN -> [SKIP][105] ([i915#2994]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@sysfs_clients@sema-50.html #### Possible fixes #### * igt@fbdev@info: - {shard-rkl}: [SKIP][106] ([i915#2582]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@fbdev@info.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@fbdev@info.html * igt@feature_discovery@psr2: - shard-iclb: [SKIP][108] ([i915#658]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb6/igt@feature_discovery@psr2.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb2/igt@feature_discovery@psr2.html * igt@gem_ctx_persistence@many-contexts: - shard-tglb: [FAIL][110] ([i915#2410]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][112] ([i915#2842]) -> [PASS][113] +1 similar issue [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - {shard-rkl}: [FAIL][114] ([i915#2842]) -> [PASS][115] +5 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-tglb: [FAIL][116] ([i915#2842]) -> [PASS][117] +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-tglb8/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_whisper@basic-fds: - shard-glk: [DMESG-WARN][118] ([i915#118] / [i915#95]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk8/igt@gem_exec_whisper@basic-fds.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk1/igt@gem_exec_whisper@basic-fds.html * igt@gem_mmap_gtt@basic-wc: - {shard-rkl}: [FAIL][120] ([i915#3830]) -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@gem_mmap_gtt@basic-wc.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-1/igt@gem_mmap_gtt@basic-wc.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-glk: [FAIL][122] ([i915#1888] / [i915#307]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-glk2/igt@gem_mmap_gtt@cpuset-big-copy.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-glk4/igt@gem_mmap_gtt@cpuset-big-copy.html * igt@gem_workarounds@suspend-resume-context: - {shard-rkl}: [FAIL][124] ([fdo#103375]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-6/igt@gem_workarounds@suspend-resume-context.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-5/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_backlight@fade: - {shard-rkl}: [SKIP][126] ([i915#3012]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@i915_pm_backlight@fade.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@i915_pm_backlight@fade.html * igt@i915_suspend@debugfs-reader: - shard-iclb: [INCOMPLETE][128] ([i915#1185]) -> [PASS][129] [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-iclb3/igt@i915_suspend@debugfs-reader.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-iclb7/igt@i915_suspend@debugfs-reader.html * igt@kms_big_fb@x-tiled-16bpp-rotate-0: - {shard-rkl}: [SKIP][130] ([i915#3638]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-0.html * igt@kms_big_fb@y-tiled-32bpp-rotate-90: - {shard-rkl}: [SKIP][132] ([fdo#111614]) -> [PASS][133] [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - {shard-rkl}: [SKIP][134] ([i915#3721]) -> [PASS][135] [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - {shard-rkl}: [FAIL][136] ([i915#3678]) -> [PASS][137] +3 similar issues [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_color@pipe-c-ctm-red-to-blue: - {shard-rkl}: [SKIP][138] ([i915#1149] / [i915#1849]) -> [PASS][139] +1 similar issue [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_color@pipe-c-ctm-red-to-blue.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_color@pipe-c-ctm-red-to-blue.html * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque: - {shard-rkl}: [SKIP][140] ([fdo#112022]) -> [PASS][141] +4 similar issues [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - {shard-rkl}: [SKIP][142] ([fdo#111825]) -> [PASS][143] [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/shard-rkl-6/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled: - {shard-rkl}: [SKIP][144] ([fdo#111314]) -> [PASS][145] +3 similar issues [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10415/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-blt-xtiled.html [145]: https:/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20730/index.html [-- Attachment #1.2: Type: text/html, Size: 34094 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/4] Remove CNL - for drm-intel-gt-next 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi @ 2021-07-29 11:14 ` Rodrigo Vivi -1 siblings, 0 replies; 15+ messages in thread From: Rodrigo Vivi @ 2021-07-29 11:14 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, dri-devel On Wed, Jul 28, 2021 at 03:03:22PM -0700, Lucas De Marchi wrote: > This the part of https://patchwork.freedesktop.org/series/93056/ > that should go through drm-intel-gt-next branch. Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Lucas De Marchi (4): > drm/i915/gt: remove explicit CNL handling from intel_mocs.c > drm/i915/gt: remove explicit CNL handling from intel_sseu.c > drm/i915/gt: rename CNL references in intel_engine.h > drm/i915/gt: remove GRAPHICS_VER == 10 > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 +-- > drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 - > drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 +-- > drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--------- > drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- > drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ------------------- > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- > drivers/gpu/drm/i915/i915_drv.h | 4 +- > 14 files changed, 27 insertions(+), 149 deletions(-) > > -- > 2.31.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 0/4] Remove CNL - for drm-intel-gt-next @ 2021-07-29 11:14 ` Rodrigo Vivi 0 siblings, 0 replies; 15+ messages in thread From: Rodrigo Vivi @ 2021-07-29 11:14 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, dri-devel On Wed, Jul 28, 2021 at 03:03:22PM -0700, Lucas De Marchi wrote: > This the part of https://patchwork.freedesktop.org/series/93056/ > that should go through drm-intel-gt-next branch. Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Lucas De Marchi (4): > drm/i915/gt: remove explicit CNL handling from intel_mocs.c > drm/i915/gt: remove explicit CNL handling from intel_sseu.c > drm/i915/gt: rename CNL references in intel_engine.h > drm/i915/gt: remove GRAPHICS_VER == 10 > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 +-- > drivers/gpu/drm/i915/gt/intel_engine.h | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 - > drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +- > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 10 +-- > drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--------- > drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- > drivers/gpu/drm/i915/gt/intel_sseu.c | 79 ------------------- > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +- > drivers/gpu/drm/i915/i915_drv.h | 4 +- > 14 files changed, 27 insertions(+), 149 deletions(-) > > -- > 2.31.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-07-29 11:14 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-07-28 22:03 [PATCH 0/4] Remove CNL - for drm-intel-gt-next Lucas De Marchi 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi 2021-07-28 22:03 ` [PATCH 1/4] drm/i915/gt: remove explicit CNL handling from intel_mocs.c Lucas De Marchi 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi 2021-07-28 22:03 ` [PATCH 2/4] drm/i915/gt: remove explicit CNL handling from intel_sseu.c Lucas De Marchi 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi 2021-07-28 22:03 ` [PATCH 3/4] drm/i915/gt: rename CNL references in intel_engine.h Lucas De Marchi 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi 2021-07-28 22:03 ` [PATCH 4/4] drm/i915/gt: remove GRAPHICS_VER == 10 Lucas De Marchi 2021-07-28 22:03 ` [Intel-gfx] " Lucas De Marchi 2021-07-28 23:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remove CNL - for drm-intel-gt-next Patchwork 2021-07-28 23:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-07-29 5:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-07-29 11:14 ` [PATCH 0/4] " Rodrigo Vivi 2021-07-29 11:14 ` [Intel-gfx] " Rodrigo Vivi
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