[PATCH] board: ti: k2g: Program PadConfig_202 before locking RSTMUX8

* [PATCH] board: ti: k2g: Program PadConfig_202 before locking RSTMUX8
@ 2021-07-26 23:22 Suman Anna
  2021-07-29  5:14 ` Lokesh Vutla
  0 siblings, 1 reply; 2+ messages in thread
From: Suman Anna @ 2021-07-26 23:22 UTC (permalink / raw)
  To: Lokesh Vutla
  Cc: Praneeth Bajjuri, Kishon Vijay Abraham I, Grygorii Strashko,
	Vignesh Raghavendra, u-boot, Suman Anna

The PADCONFIG_202 register (0x02621328) is affected by the locking
of the RSTMUX8 register (0x02620328), and so cannot be configured
in kernel. This has been confirmed as a hardware bug and affects
all K2G SoCs.

Setup the pinmux for this pin before locking the RSTMUX8 register
to allow the ICSS1 PRU1 Ethernet PHY port to work properly. The
workaround was added only for the K2G-ICE board to configure the
pins needed for the PRUSS Ethernet usecase.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 board/ti/ks2_evm/mux-k2g.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index fa6c92cbdf1e..f24e62850b8b 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -368,6 +368,9 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = {
 	{ 98,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_DATA */
 	{ 99,	BUFFER_CLASS_B | PIN_PDIS | MODE(0) },	/* MDIO_CLK */
 
+	/* ICSS1 Padconf Workaround */
+	{ 202, MODE(1) | PIN_PDIS },    /* PR1_PRU1_GPO1.PR1_PRU1_GPI1 (PR1_MII1_RXD1) */
+
 	{ MAX_PIN_N, }
 };
 
-- 
2.32.0


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