* [PATCH v2 01/19] drm/dp: add DP 2.0 UHBR link rate and bw code conversions
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] " Jani Nikula
` (21 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d0f2c447f3b..9b2a2961fca8 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
u8 drm_dp_link_rate_to_bw_code(int link_rate)
{
- /* Spec says link_bw = link_rate / 0.27Gbps */
- return link_rate / 27000;
+ switch (link_rate) {
+ case 1000000:
+ return DP_LINK_BW_10;
+ case 1350000:
+ return DP_LINK_BW_13_5;
+ case 2000000:
+ return DP_LINK_BW_20;
+ default:
+ /* Spec says link_bw = link_rate / 0.27Gbps */
+ return link_rate / 27000;
+ }
}
EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
int drm_dp_bw_code_to_link_rate(u8 link_bw)
{
- /* Spec says link_rate = link_bw * 0.27Gbps */
- return link_bw * 27000;
+ switch (link_bw) {
+ case DP_LINK_BW_10:
+ return 1000000;
+ case DP_LINK_BW_13_5:
+ return 1350000;
+ case DP_LINK_BW_20:
+ return 2000000;
+ default:
+ /* Spec says link_rate = link_bw * 0.27Gbps */
+ return link_bw * 27000;
+ }
}
EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 01/19] drm/dp: add DP 2.0 UHBR link rate and bw code conversions
@ 2021-08-23 16:18 ` Jani Nikula
0 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 6d0f2c447f3b..9b2a2961fca8 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
u8 drm_dp_link_rate_to_bw_code(int link_rate)
{
- /* Spec says link_bw = link_rate / 0.27Gbps */
- return link_rate / 27000;
+ switch (link_rate) {
+ case 1000000:
+ return DP_LINK_BW_10;
+ case 1350000:
+ return DP_LINK_BW_13_5;
+ case 2000000:
+ return DP_LINK_BW_20;
+ default:
+ /* Spec says link_bw = link_rate / 0.27Gbps */
+ return link_rate / 27000;
+ }
}
EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
int drm_dp_bw_code_to_link_rate(u8 link_bw)
{
- /* Spec says link_rate = link_bw * 0.27Gbps */
- return link_bw * 27000;
+ switch (link_bw) {
+ case DP_LINK_BW_10:
+ return 1000000;
+ case DP_LINK_BW_13_5:
+ return 1350000;
+ case DP_LINK_BW_20:
+ return 2000000;
+ default:
+ /* Spec says link_rate = link_bw * 0.27Gbps */
+ return link_bw * 27000;
+ }
}
EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 02/19] drm/dp: use more of the extended receiver cap
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] " Jani Nikula
` (21 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9b2a2961fca8..9389f92cb944 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
- u8 dpcd_ext[6];
+ u8 dpcd_ext[DP_MAIN_LINK_CHANNEL_CODING + 1];
int ret;
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 02/19] drm/dp: use more of the extended receiver cap
@ 2021-08-23 16:18 ` Jani Nikula
0 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9b2a2961fca8..9389f92cb944 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
- u8 dpcd_ext[6];
+ u8 dpcd_ext[DP_MAIN_LINK_CHANNEL_CODING + 1];
int ret;
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 03/19] drm/dp: add LTTPR DP 2.0 DPCD addresses
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] " Jani Nikula
` (21 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..f3a61341011d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1319,6 +1319,10 @@ struct drm_panel;
#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
+#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
+# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
+/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
+#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy {
DP_PHY_DPRX,
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 03/19] drm/dp: add LTTPR DP 2.0 DPCD addresses
@ 2021-08-23 16:18 ` Jani Nikula
0 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..f3a61341011d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1319,6 +1319,10 @@ struct drm_panel;
#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
+#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
+# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
+/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
+#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
enum drm_dp_phy {
DP_PHY_DPRX,
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 04/19] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] " Jani Nikula
` (21 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9389f92cb944..2843238a78e6 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+/* DP 2.0 128b/132b */
+u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+{
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+ DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
+ DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
+ u8 l = dp_link_status(link_status, i);
+
+ return (l >> s) & 0xf;
+}
+EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
+
u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
unsigned int lane)
{
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f3a61341011d..3ee0b3ffb8a5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
+u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane);
u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
unsigned int lane);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 04/19] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
@ 2021-08-23 16:18 ` Jani Nikula
0 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare, dri-devel
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 9389f92cb944..2843238a78e6 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
}
EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
+/* DP 2.0 128b/132b */
+u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+{
+ int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
+ int s = ((lane & 1) ?
+ DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
+ DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
+ u8 l = dp_link_status(link_status, i);
+
+ return (l >> s) & 0xf;
+}
+EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
+
u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
unsigned int lane)
{
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f3a61341011d..3ee0b3ffb8a5 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane);
+u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane);
u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
unsigned int lane);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH v2 05/19] drm/i915/dp: use actual link rate values in struct link_config_limits
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (3 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] " Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 06/19] drm/i915/dp: read sink UHBR rates Jani Nikula
` (17 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
The MST code uses actual link rates in the limits struct, while the DP
code in general uses indexes to the ->common_rates[] array. Fix the
confusion by using actual link rate values everywhere. This is a better
abstraction than some obscure index.
Rename the struct members while at it to ensure all the places are
covered.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 ++++++++++++---------
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++---
3 files changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0dbd35ae7bc..b21dac19ae76 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1044,7 +1044,8 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
intel_dp->num_common_rates,
intel_dp->compliance.test_link_rate);
if (index >= 0)
- limits->min_clock = limits->max_clock = index;
+ limits->min_rate = limits->max_rate =
+ intel_dp->compliance.test_link_rate;
limits->min_lane_count = limits->max_lane_count =
intel_dp->compliance.test_lane_count;
}
@@ -1058,8 +1059,8 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
const struct link_config_limits *limits)
{
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- int bpp, clock, lane_count;
- int mode_rate, link_clock, link_avail;
+ int bpp, i, lane_count;
+ int mode_rate, link_rate, link_avail;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
@@ -1067,18 +1068,22 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
output_bpp);
- for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
+ for (i = 0; i < intel_dp->num_common_rates; i++) {
+ link_rate = intel_dp->common_rates[i];
+ if (link_rate < limits->min_rate ||
+ link_rate > limits->max_rate)
+ continue;
+
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- link_clock = intel_dp->common_rates[clock];
- link_avail = intel_dp_max_data_rate(link_clock,
+ link_avail = intel_dp_max_data_rate(link_rate,
lane_count);
if (mode_rate <= link_avail) {
pipe_config->lane_count = lane_count;
pipe_config->pipe_bpp = bpp;
- pipe_config->port_clock = link_clock;
+ pipe_config->port_clock = link_rate;
return 0;
}
@@ -1212,7 +1217,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* with DSC enabled for the requested mode.
*/
pipe_config->pipe_bpp = pipe_bpp;
- pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
+ pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
if (intel_dp_is_edp(intel_dp)) {
@@ -1321,8 +1326,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
/* No common link rates between source and sink */
drm_WARN_ON(encoder->base.dev, common_len <= 0);
- limits.min_clock = 0;
- limits.max_clock = common_len - 1;
+ limits.min_rate = intel_dp->common_rates[0];
+ limits.max_rate = intel_dp->common_rates[common_len - 1];
limits.min_lane_count = 1;
limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
@@ -1340,15 +1345,14 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
* values correspond to the native resolution of the panel.
*/
limits.min_lane_count = limits.max_lane_count;
- limits.min_clock = limits.max_clock;
+ limits.min_rate = limits.max_rate;
}
intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
- limits.max_lane_count,
- intel_dp->common_rates[limits.max_clock],
+ limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 680631b5b437..1345d588fc6d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,7 +26,7 @@ struct intel_dp;
struct intel_encoder;
struct link_config_limits {
- int min_clock, max_clock;
+ int min_rate, max_rate;
int min_lane_count, max_lane_count;
int min_bpp, max_bpp;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9859c0334ebc..d104441344c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -61,7 +61,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
int bpp, slots = -EINVAL;
crtc_state->lane_count = limits->max_lane_count;
- crtc_state->port_clock = limits->max_clock;
+ crtc_state->port_clock = limits->max_rate;
for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
crtc_state->pipe_bpp = bpp;
@@ -131,8 +131,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
*/
- limits.min_clock =
- limits.max_clock = intel_dp_max_link_rate(intel_dp);
+ limits.min_rate =
+ limits.max_rate = intel_dp_max_link_rate(intel_dp);
limits.min_lane_count =
limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 06/19] drm/i915/dp: read sink UHBR rates
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (4 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 05/19] drm/i915/dp: use actual link rate values in struct link_config_limits Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 07/19] drm/i915/dg2: add TRANS_DP2_CTL register definition Jani Nikula
` (16 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
See if sink supports DP 2.0 128b/132b channel encoding, and update sink
rates accordingly.
FIXME: Also take LTTPR 128b/132b into account.
v2: Add build-time check for ->sink_rates size (Ville)
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b21dac19ae76..3a701728e47e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -141,6 +141,26 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
intel_dp->sink_rates[i] = dp_rates[i];
}
+ /*
+ * Sink rates for 128b/132b. If set, sink should support all 8b/10b
+ * rates and 10 Gbps.
+ */
+ if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
+ u8 uhbr_rates = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
+
+ drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
+
+ if (uhbr_rates & DP_UHBR10)
+ intel_dp->sink_rates[i++] = 1000000;
+ if (uhbr_rates & DP_UHBR13_5)
+ intel_dp->sink_rates[i++] = 1350000;
+ if (uhbr_rates & DP_UHBR20)
+ intel_dp->sink_rates[i++] = 2000000;
+ }
+
intel_dp->num_sink_rates = i;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 07/19] drm/i915/dg2: add TRANS_DP2_CTL register definition
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (5 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 06/19] drm/i915/dp: read sink UHBR rates Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 08/19] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
` (15 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
This register controls the DP 2.0 datapath.
Bspec: 69967
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4b7c69c70b66..bd400553f9ea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9101,6 +9101,15 @@ enum {
#define TRANS_DP_HSYNC_ACTIVE_LOW 0
#define TRANS_DP_SYNC_MASK (3 << 3)
+#define _TRANS_DP2_CTL_A 0x600a0
+#define _TRANS_DP2_CTL_B 0x610a0
+#define _TRANS_DP2_CTL_C 0x620a0
+#define _TRANS_DP2_CTL_D 0x630a0
+#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
+#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
+#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
+#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
+
/* SNB eDP training params */
/* SNB A-stepping */
#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 08/19] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (6 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 07/19] drm/i915/dg2: add TRANS_DP2_CTL register definition Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 09/19] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Jani Nikula
` (14 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register
conflicts with FDI. Since we have to deal with both meanings in the same
code, for different platforms, clarify the macro name so we don't
forget.
Bspec: 50493
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1ef7a65feb66..203a54f905f6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -488,7 +488,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
- temp |= TRANS_DDI_MODE_SELECT_FDI;
+ temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
@@ -678,7 +678,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
ret = false;
break;
- case TRANS_DDI_MODE_SELECT_FDI:
+ case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
ret = type == DRM_MODE_CONNECTOR_VGA;
break;
@@ -3557,7 +3557,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
pipe_config->lane_count = 4;
break;
- case TRANS_DDI_MODE_SELECT_FDI:
+ case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
break;
case TRANS_DDI_MODE_SELECT_DP_SST:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bd400553f9ea..93b51ba2da87 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10169,7 +10169,7 @@ enum skl_power_gate {
#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
-#define TRANS_DDI_MODE_SELECT_FDI (4 << 24)
+#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
#define TRANS_DDI_BPC_MASK (7 << 20)
#define TRANS_DDI_BPC_8 (0 << 20)
#define TRANS_DDI_BPC_10 (1 << 20)
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 09/19] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (7 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 08/19] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 10/19] drm/i915/dg2: add DG2 UHBR source rates Jani Nikula
` (13 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
Add the registers for specifying the lower and higher 24 bits of the DP
2.0 pixel clock frequency in Hz.
Bspec: 53326
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93b51ba2da87..d0c507a98699 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9110,6 +9110,20 @@ enum {
#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
+#define _TRANS_DP2_VFREQHIGH_A 0x600a4
+#define _TRANS_DP2_VFREQHIGH_B 0x610a4
+#define _TRANS_DP2_VFREQHIGH_C 0x620a4
+#define _TRANS_DP2_VFREQHIGH_D 0x630a4
+#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
+
+#define _TRANS_DP2_VFREQLOW_A 0x600a8
+#define _TRANS_DP2_VFREQLOW_B 0x610a8
+#define _TRANS_DP2_VFREQLOW_C 0x620a8
+#define _TRANS_DP2_VFREQLOW_D 0x630a8
+#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
+
/* SNB eDP training params */
/* SNB A-stepping */
#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 10/19] drm/i915/dg2: add DG2 UHBR source rates
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (8 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 09/19] drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 11/19] drm/i915/dp: add max data rate calculation for UHBR rates Jani Nikula
` (12 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
DG2 supports DP 2.0 UHBR and 128b/132b channel encoding.
Bspec: 53657, 54034
Acked-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3a701728e47e..1a0eb4c4d666 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -242,6 +242,11 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
encoder->port != PORT_A);
}
+static int dg2_max_source_rate(struct intel_dp *intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
+}
+
static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -268,7 +273,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
static const int icl_rates[] = {
- 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
+ 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
+ 1000000, 1350000,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 270000, 324000, 432000, 540000
@@ -295,6 +301,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
+ if (IS_DG2(dev_priv))
+ max_rate = dg2_max_source_rate(intel_dp);
if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 11/19] drm/i915/dp: add max data rate calculation for UHBR rates
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (9 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 10/19] drm/i915/dg2: add DG2 UHBR source rates Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 12/19] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula
` (11 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
DP 2.0 UHBR link rates always use 128b/132b channel encoding, which has
a different data bandwidth efficiency from 8b/10b. The computation is
slightly convoluted due to the units we use; this is all explained in
the added comment.
v2: Clarified comment (Manasi)
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++++++++---
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
2 files changed, 47 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1a0eb4c4d666..7e5d9b959c1d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -212,6 +212,10 @@ int intel_dp_max_lane_count(struct intel_dp *intel_dp)
return intel_dp->max_link_lane_count;
}
+/*
+ * The required data bandwidth for a mode with given pixel clock and bpp. This
+ * is the required net bandwidth independent of the data bandwidth efficiency.
+ */
int
intel_dp_link_required(int pixel_clock, int bpp)
{
@@ -219,16 +223,52 @@ intel_dp_link_required(int pixel_clock, int bpp)
return DIV_ROUND_UP(pixel_clock * bpp, 8);
}
+/*
+ * Given a link rate and lanes, get the data bandwidth.
+ *
+ * Data bandwidth is the actual payload rate, which depends on the data
+ * bandwidth efficiency and the link rate.
+ *
+ * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
+ * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
+ * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
+ * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
+ * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
+ * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
+ *
+ * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
+ * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
+ * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
+ * does not match the symbol clock, the port clock (not even if you think in
+ * terms of a byte clock), nor the data bandwidth. It only matches the link bit
+ * rate in units of 10000 bps.
+ */
int
-intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+intel_dp_max_data_rate(int max_link_rate, int max_lanes)
{
- /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
- * link rate that is generally expressed in Gbps. Since, 8 bits of data
- * is transmitted every LS_Clk per lane, there is no need to account for
- * the channel encoding that is done in the PHY layer here.
+ if (max_link_rate >= 1000000) {
+ /*
+ * UHBR rates always use 128b/132b channel encoding, and have
+ * 97.71% data bandwidth efficiency. Consider max_link_rate the
+ * link bit rate in units of 10000 bps.
+ */
+ int max_link_rate_kbps = max_link_rate * 10;
+
+ max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 9671, 10000);
+ max_link_rate = max_link_rate_kbps / 8;
+ }
+
+ /*
+ * Lower than UHBR rates always use 8b/10b channel encoding, and have
+ * 80% data bandwidth efficiency for SST non-FEC. However, this turns
+ * out to be a nop by coincidence, and can be skipped:
+ *
+ * int max_link_rate_kbps = max_link_rate * 10;
+ * max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
+ * max_link_rate = max_link_rate_kbps / 8;
*/
- return max_link_clock * max_lanes;
+ return max_link_rate * max_lanes;
}
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 1345d588fc6d..ae0f776bffab 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -88,7 +88,7 @@ bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
-int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
+int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 12/19] drm/i915/dp: add helper for checking for UHBR link rate
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (10 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 11/19] drm/i915/dp: add max data rate calculation for UHBR rates Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 13/19] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
` (10 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
Helpful abstraction to avoid duplication.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e5d9b959c1d..907c10a0cdef 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -111,6 +111,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+/* Is link rate UHBR and thus 128b/132b? */
+bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->port_clock >= 1000000;
+}
+
/* update sink rates from dpcd */
static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index ae0f776bffab..443a8628bfcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state);
bool intel_dp_is_edp(struct intel_dp *intel_dp);
+bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
bool long_hpd);
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 13/19] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (11 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 12/19] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 14/19] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
` (9 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.
v2: Use intel_dp_is_uhbr
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 508a514c5e37..36b35239da83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
}
/*
- * Pick training pattern for channel equalization. Training pattern 4 for HBR3
- * or for 1.4 devices that support it, training Pattern 3 for HBR2
- * or 1.2 devices that support it, Training Pattern 2 otherwise.
+ * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
+ * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
+ * 1.2 devices that support it, TPS2 otherwise.
*/
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
@@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
{
bool source_tps3, sink_tps3, source_tps4, sink_tps4;
+ /* UHBR+ use separate 128b/132b TPS2 */
+ if (intel_dp_is_uhbr(crtc_state))
+ return DP_TRAINING_PATTERN_2;
+
/*
* Intel platforms that support HBR3 also support TPS4. It is mandatory
* for all downstream devices that support HBR3. There are no known eDP
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 14/19] drm/i915/dp: select 128b/132b channel encoding for UHBR rates
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (12 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 13/19] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 15/19] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
` (8 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
UHBR rates and 128b/132b channel encoding go hand in hand.
v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville)
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 36b35239da83..4f116cd32846 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -495,7 +495,8 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
&rate_select, 1);
link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
- link_config[1] = DP_SET_ANSI_8B10B;
+ link_config[1] = intel_dp_is_uhbr(crtc_state) ?
+ DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
intel_dp->DP |= DP_PORT_EN;
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 15/19] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (13 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 14/19] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 16/19] drm/i915/dp: add HAS_DP20 macro Jani Nikula
` (7 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
Set the DP 2.0 128b/132b channel encoding for UHBR rates.
v2: Fix UHBR port clock check, use intel_dp_is_uhbr()
Bspec: 54128
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 203a54f905f6..d885a4c0fb39 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -407,6 +407,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
return master_transcoder + 1;
}
+static void
+intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val = 0;
+
+ if (intel_dp_is_uhbr(crtc_state))
+ val = TRANS_DP2_128B132B_CHANNEL_CODING;
+
+ intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
+}
+
/*
* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
*
@@ -2375,7 +2389,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
*/
intel_ddi_enable_pipe_clock(encoder, crtc_state);
- /* 5.b Not relevant to i915 for now */
+ /* 5.b Configure transcoder for DP 2.0 128b/132b */
+ intel_ddi_config_transcoder_dp2(encoder, crtc_state);
/*
* 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 16/19] drm/i915/dp: add HAS_DP20 macro
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (14 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 15/19] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 17/19] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
` (6 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
Let's abstract the DP 2.0 feature. Initially just DG2.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a2b63072ff5..fc89cf618b44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1665,6 +1665,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
+#define HAS_DP20(dev_priv) (IS_DG2(dev_priv))
#define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 17/19] drm/i915/dg2: use 128b/132b transcoder DDI mode
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (15 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 16/19] drm/i915/dp: add HAS_DP20 macro Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 18/19] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
` (5 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
128b/132b has a separate transcoder DDI mode, which also requires the
MST transport select to be set. Note that we'll use DP MST also for
single-stream 128b/132b.
Having the FDI and 128b/132b modes share the register mode value
complicates things a bit.
v2:
- Use HAS_DP20 abstraction for 128b/132b mode (Ville)
- Use intel_dp_is_uhbr() helper
Bspec: 50493
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d885a4c0fb39..bbc2e052075d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -505,7 +505,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
- temp |= TRANS_DDI_MODE_SELECT_DP_MST;
+ if (intel_dp_is_uhbr(crtc_state))
+ temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
+ else
+ temp |= TRANS_DDI_MODE_SELECT_DP_MST;
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
if (DISPLAY_VER(dev_priv) >= 12) {
@@ -693,7 +696,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
break;
case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
- ret = type == DRM_MODE_CONNECTOR_VGA;
+ if (HAS_DP20(dev_priv))
+ /* 128b/132b */
+ ret = false;
+ else
+ /* FDI */
+ ret = type == DRM_MODE_CONNECTOR_VGA;
break;
default:
@@ -780,8 +788,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
if ((tmp & port_mask) != ddi_select)
continue;
- if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
- TRANS_DDI_MODE_SELECT_DP_MST)
+ if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
+ (HAS_DP20(dev_priv) &&
+ (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
mst_pipe_mask |= BIT(p);
*pipe_mask |= BIT(p);
@@ -3572,9 +3581,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
pipe_config->lane_count = 4;
break;
- case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
- pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
- break;
case TRANS_DDI_MODE_SELECT_DP_SST:
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
@@ -3603,6 +3609,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
pipe_config->infoframes.enable |=
intel_hdmi_infoframes_enabled(encoder, pipe_config);
break;
+ case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
+ if (!HAS_DP20(dev_priv)) {
+ /* FDI */
+ pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
+ break;
+ }
+ fallthrough; /* 128b/132b */
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 18/19] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (16 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 17/19] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 19/19] drm/i915/dg2: update link training " Jani Nikula
` (4 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.
v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper
Bspec: 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d104441344c0..97af19fd9780 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
clear_act_sent(encoder, pipe_config);
+ if (intel_dp_is_uhbr(pipe_config)) {
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
+
+ intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
+ TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
+ intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
+ TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
+ }
+
intel_ddi_enable_transcoder_func(encoder, pipe_config);
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] [PATCH v2 19/19] drm/i915/dg2: update link training for 128b/132b
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (17 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 18/19] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
@ 2021-08-23 16:18 ` Jani Nikula
2021-08-23 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev2) Patchwork
` (3 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Jani Nikula @ 2021-08-23 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, ville.syrjala, manasi.d.navare
The 128b/132b channel coding link training uses more straightforward TX
FFE preset values.
v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++-
.../drm/i915/display/intel_dp_link_training.c | 86 +++++++++++++------
2 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bbc2e052075d..3cbe56e2a473 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1397,11 +1397,16 @@ static int translate_signal_level(struct intel_dp *intel_dp,
static int intel_ddi_dp_level(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- u8 train_set = intel_dp->train_set[0];
- u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
- DP_TRAIN_PRE_EMPHASIS_MASK);
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /* FIXME: We'll want independent presets for each lane. */
+ return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK;
+ } else {
+ u8 train_set = intel_dp->train_set[0];
+ u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
+ DP_TRAIN_PRE_EMPHASIS_MASK);
- return translate_signal_level(intel_dp, signal_levels);
+ return translate_signal_level(intel_dp, signal_levels);
+ }
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 4f116cd32846..c10f165d1aa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -301,6 +301,24 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
return preemph_max;
}
+static void intel_dp_128b132b_adjust_train(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ int lane;
+ u8 tx_ffe = 0;
+
+ /*
+ * FIXME: We'll want independent presets for each lane. See also
+ * intel_ddi_dp_level() and intel_snps_phy_ddi_vswing_sequence().
+ */
+ for (lane = 0; lane < crtc_state->lane_count; lane++)
+ tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
+
+ for (lane = 0; lane < crtc_state->lane_count; lane++)
+ intel_dp->train_set[lane] = tx_ffe;
+}
+
void
intel_dp_get_adjust_train(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
@@ -313,6 +331,11 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
u8 voltage_max;
u8 preemph_max;
+ if (intel_dp_is_uhbr(crtc_state)) {
+ intel_dp_128b132b_adjust_train(intel_dp, crtc_state, link_status);
+ return;
+ }
+
for (lane = 0; lane < crtc_state->lane_count; lane++) {
v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
@@ -402,14 +425,21 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
u8 train_set = intel_dp->train_set[0];
char phy_name[10];
- drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
- train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
- train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
- (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
- DP_TRAIN_PRE_EMPHASIS_SHIFT,
- train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
- " (max)" : "",
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
+ if (intel_dp_is_uhbr(crtc_state)) {
+ /* FIXME: We'll want independent presets for each lane. */
+ drm_dbg_kms(&dev_priv->drm, "%s: Using 128b/132b TX FFE preset %u\n",
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ train_set & DP_TX_FFE_PRESET_VALUE_MASK);
+ } else {
+ drm_dbg_kms(&dev_priv->drm, "%s: Using 8b/10b vswing level %d%s, pre-emphasis level %d%s\n",
+ intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
+ train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
+ (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT,
+ train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
+ " (max)" : "");
+ }
if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
intel_dp->set_signal_levels(intel_dp, crtc_state);
@@ -565,18 +595,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
return true;
}
- if (voltage_tries == 5) {
- drm_dbg_kms(&i915->drm,
- "Same voltage tried 5 times\n");
- return false;
- }
+ /* FIXME: 128b/132b needs better abstractions here. */
+ if (!intel_dp_is_uhbr(crtc_state)) {
+ if (voltage_tries == 5) {
+ drm_dbg_kms(&i915->drm,
+ "Same voltage tried 5 times\n");
+ return false;
+ }
- if (max_vswing_reached) {
- drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
- return false;
- }
+ if (max_vswing_reached) {
+ drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
+ return false;
+ }
- voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+ voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+ }
/* Update training set as requested by target */
intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
@@ -587,14 +620,17 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
return false;
}
- if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
- voltage)
- ++voltage_tries;
- else
- voltage_tries = 1;
+ /* FIXME: 128b/132b needs better abstractions here. */
+ if (!intel_dp_is_uhbr(crtc_state)) {
+ if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
+ voltage)
+ ++voltage_tries;
+ else
+ voltage_tries = 1;
- if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
- max_vswing_reached = true;
+ if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
+ max_vswing_reached = true;
+ }
}
drm_err(&i915->drm,
--
2.20.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev2)
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (18 preceding siblings ...)
2021-08-23 16:18 ` [Intel-gfx] [PATCH v2 19/19] drm/i915/dg2: update link training " Jani Nikula
@ 2021-08-23 16:58 ` Patchwork
2021-08-23 17:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-08-23 16:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev2)
URL : https://patchwork.freedesktop.org/series/93800/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8759d8bfe020 drm/dp: add DP 2.0 UHBR link rate and bw code conversions
9397aee48cfd drm/dp: use more of the extended receiver cap
a23d8a2c3bff drm/dp: add LTTPR DP 2.0 DPCD addresses
98f3670ed782 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
042b65b439ac drm/i915/dp: use actual link rate values in struct link_config_limits
-:30: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#30: FILE: drivers/gpu/drm/i915/display/intel_dp.c:1047:
+ limits->min_rate = limits->max_rate =
total: 0 errors, 0 warnings, 1 checks, 106 lines checked
34e2c14f2850 drm/i915/dp: read sink UHBR rates
9daeb845ce59 drm/i915/dg2: add TRANS_DP2_CTL register definition
-:24: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:9108:
+#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
total: 0 errors, 1 warnings, 0 checks, 15 lines checked
7d6c5525e2aa drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
aed810a8337a drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
-:25: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/i915_reg.h:9117:
+#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
-:27: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:9119:
+#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
-:33: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:9125:
+#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
total: 0 errors, 3 warnings, 0 checks, 20 lines checked
c7f5afac00ac drm/i915/dg2: add DG2 UHBR source rates
d8ac1ff0bbbe drm/i915/dp: add max data rate calculation for UHBR rates
e5482f012b51 drm/i915/dp: add helper for checking for UHBR link rate
38655af915e1 drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
bbded83b9092 drm/i915/dp: select 128b/132b channel encoding for UHBR rates
32f8f2e8c94f drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
4406550f6936 drm/i915/dp: add HAS_DP20 macro
67152b2848ba drm/i915/dg2: use 128b/132b transcoder DDI mode
5fda70736e96 drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b
87410f9fe830 drm/i915/dg2: update link training for 128b/132b
-:27: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#27: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1403:
+ return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 139 lines checked
^ permalink raw reply [flat|nested] 28+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dp: dp 2.0 enabling prep work (rev2)
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (19 preceding siblings ...)
2021-08-23 16:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev2) Patchwork
@ 2021-08-23 17:00 ` Patchwork
2021-08-23 17:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-23 19:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
22 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-08-23 17:00 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev2)
URL : https://patchwork.freedesktop.org/series/93800/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:123:51: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv
^ permalink raw reply [flat|nested] 28+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: dp 2.0 enabling prep work (rev2)
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (20 preceding siblings ...)
2021-08-23 17:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-08-23 17:29 ` Patchwork
2021-08-23 19:32 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
22 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-08-23 17:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8735 bytes --]
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev2)
URL : https://patchwork.freedesktop.org/series/93800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10508 -> Patchwork_20875
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/index.html
Known issues
------------
Here are the changes found in Patchwork_20875 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: NOTRUN -> [FAIL][1] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_module_load@reload:
- fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][3] ([i915#1385] / [i915#4002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#1155])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
- fi-rkl-guc: NOTRUN -> [SKIP][5] ([i915#3012])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][6] ([i915#4006])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: NOTRUN -> [DMESG-FAIL][7] ([i915#3928])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@too-wide:
- fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][8] ([i915#4002]) +87 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@kms_addfb_basic@too-wide.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-edid-read:
- fi-rkl-guc: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@kms_chamelium@dp-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#109285])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-guc: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-guc: NOTRUN -> [SKIP][13] ([i915#533])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#1072]) +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@primary_page_flip:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#1072] / [i915#1385])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-guc: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
- fi-rkl-guc: NOTRUN -> [SKIP][18] ([i915#3301])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- fi-rkl-guc: NOTRUN -> [SKIP][19] ([i915#3291]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@prime_vgem@basic-write.html
* igt@runner@aborted:
- fi-tgl-1115g4: NOTRUN -> [FAIL][20] ([i915#2722] / [i915#3834])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_wait@busy@all:
- fi-rkl-guc: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/fi-rkl-guc/igt@gem_wait@busy@all.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@gem_wait@busy@all.html
#### Warnings ####
* igt@runner@aborted:
- fi-rkl-guc: [FAIL][23] ([i915#2426]) -> [FAIL][24] ([i915#3928])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/fi-rkl-guc/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/fi-rkl-guc/igt@runner@aborted.html
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3834]: https://gitlab.freedesktop.org/drm/intel/issues/3834
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (39 -> 34)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (6): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10508 -> Patchwork_20875
CI-20190529: 20190529
CI_DRM_10508: 00400e0b1213556376e556de6561f117909dcab9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6183: c75ffa39b2f8b3b991deba834a3828e102c909e5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20875: 87410f9fe8309d0f6cf6de46e12f5083b7512271 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
87410f9fe830 drm/i915/dg2: update link training for 128b/132b
5fda70736e96 drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b
67152b2848ba drm/i915/dg2: use 128b/132b transcoder DDI mode
4406550f6936 drm/i915/dp: add HAS_DP20 macro
32f8f2e8c94f drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
bbded83b9092 drm/i915/dp: select 128b/132b channel encoding for UHBR rates
38655af915e1 drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
e5482f012b51 drm/i915/dp: add helper for checking for UHBR link rate
d8ac1ff0bbbe drm/i915/dp: add max data rate calculation for UHBR rates
c7f5afac00ac drm/i915/dg2: add DG2 UHBR source rates
aed810a8337a drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW
7d6c5525e2aa drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
9daeb845ce59 drm/i915/dg2: add TRANS_DP2_CTL register definition
34e2c14f2850 drm/i915/dp: read sink UHBR rates
042b65b439ac drm/i915/dp: use actual link rate values in struct link_config_limits
98f3670ed782 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
a23d8a2c3bff drm/dp: add LTTPR DP 2.0 DPCD addresses
9397aee48cfd drm/dp: use more of the extended receiver cap
8759d8bfe020 drm/dp: add DP 2.0 UHBR link rate and bw code conversions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/index.html
[-- Attachment #2: Type: text/html, Size: 10517 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: dp 2.0 enabling prep work (rev2)
2021-08-23 16:18 [Intel-gfx] [PATCH v2 00/19] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
` (21 preceding siblings ...)
2021-08-23 17:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-08-23 19:32 ` Patchwork
22 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-08-23 19:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]
== Series Details ==
Series: drm/i915/dp: dp 2.0 enabling prep work (rev2)
URL : https://patchwork.freedesktop.org/series/93800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10508_full -> Patchwork_20875_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20875_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl5/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +6 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-snb5/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2849])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#307])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb2/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@gem_pread@exhaustion.html
- shard-snb: NOTRUN -> [WARN][14] ([i915#2658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-snb5/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@huge-split:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#3376])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl1/igt@gem_userptr_blits@huge-split.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl7/igt@gem_userptr_blits@huge-split.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +209 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl2/igt@gen7_exec_parse@basic-offset.html
* igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109289])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb8/igt@gen7_exec_parse@basic-rejected.html
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109289])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@gen7_exec_parse@basic-rejected.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][21] ([i915#454])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl4/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#404])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] / [i915#95])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-iclb: [PASS][26] -> [DMESG-WARN][27] ([i915#3621])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +9 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +18 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb5/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl8/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109284] / [fdo#111827])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +24 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-snb2/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-iclb: NOTRUN -> [SKIP][36] ([i915#3116])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_content_protection@dp-mst-type-1.html
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3116])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-max-size-sliding.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271]) +15 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl7/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109274] / [fdo#109278])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2346]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#533]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109274])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_flip@2x-flip-vs-dpms.html
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111825]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb5/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [PASS][47] -> [DMESG-WARN][48] ([i915#180]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2122]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271]) +532 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-snb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2672])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109280])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-skl: [PASS][54] -> [DMESG-WARN][55] ([i915#1982]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#1188])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][61] -> [FAIL][62] ([fdo#108145] / [i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][63] ([i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2733])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][67] -> [SKIP][68] ([fdo#109441]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_tv_load_detect@load-detect:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#109309])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb5/igt@kms_tv_load_detect@load-detect.html
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109309])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [PASS][71] -> [INCOMPLETE][72] ([i915#155] / [i915#2828] / [i915#794])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl8/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][75] -> [FAIL][76] ([i915#1542])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl5/igt@perf@polling-parameterized.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl3/igt@perf@polling-parameterized.html
* igt@prime_nv_pcopy@test2:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271]) +43 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@prime_nv_pcopy@test2.html
* igt@prime_vgem@coherency-blt:
- shard-glk: [PASS][78] -> [INCOMPLETE][79] ([i915#2944])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk1/igt@prime_vgem@coherency-blt.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk3/igt@prime_vgem@coherency-blt.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl8/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-3:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#2994])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_ctx_persistence@legacy-engines-hang@blt:
- {shard-rkl}: [FAIL][82] ([i915#2410]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-rkl-2/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-rkl-1/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-skl: [TIMEOUT][84] ([i915#3063]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl2/igt@gem_eio@in-flight-contexts-1us.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl7/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][86] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-tglb6/igt@gem_eio@unwedge-stress.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb3/igt@gem_eio@unwedge-stress.html
- shard-iclb: [TIMEOUT][88] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb5/igt@gem_eio@unwedge-stress.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: [FAIL][90] ([i915#2842]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-tglb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-tglb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- {shard-rkl}: [FAIL][92] ([i915#2842]) -> [PASS][93] +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-rkl-5/igt@gem_exec_fair@basic-pace@vecs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-rkl-2/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-kbl: [SKIP][94] ([fdo#109271]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk: [DMESG-WARN][98] ([i915#118] / [i915#95]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk8/igt@gem_exec_whisper@basic-contexts-forked-all.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk1/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- {shard-rkl}: [FAIL][100] ([i915#2428]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-rkl-5/igt@gem_mmap_gtt@cpuset-big-copy.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-rkl-2/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_mmap_offset@clear:
- {shard-rkl}: [INCOMPLETE][102] -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-rkl-1/igt@gem_mmap_offset@clear.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-rkl-1/igt@gem_mmap_offset@clear.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-iclb: [SKIP][104] ([i915#3788]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb4/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [DMESG-WARN][106] ([i915#180]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@nonexisting-fb-interruptible@a-edp1:
- shard-skl: [DMESG-WARN][108] ([i915#1982]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl6/igt@kms_flip@nonexisting-fb-interruptible@a-edp1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl10/igt@kms_flip@nonexisting-fb-interruptible@a-edp1.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][110] ([fdo#108145] / [i915#265]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][112] ([fdo#109441]) -> [PASS][113] +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: [DMESG-WARN][114] ([i915#180]) -> [PASS][115] +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl4/igt@perf_pmu@rc6-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl1/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [SKIP][116] ([fdo#109271]) -> [FAIL][117] ([i915#2842])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][118] ([i915#2684]) -> [WARN][119] ([i915#1804] / [i915#2684])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-iclb: [SKIP][120] ([i915#2920]) -> [SKIP][121] ([i915#658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][122] ([i915#658]) -> [SKIP][123] ([i915#2920]) +2 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl4/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl6/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-kbl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl4/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl4/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl4/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-kbl6/igt@runner@aborted.html
- shard-iclb: ([FAIL][135], [FAIL][136]) ([i915#3002]) -> ([FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1814] / [i915#3002])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb1/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-iclb8/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb5/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-iclb1/igt@runner@aborted.html
- shard-apl: ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([fdo#109271] / [i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl3/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl8/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl3/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-apl2/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl6/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl7/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl3/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl3/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl1/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl1/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-apl3/igt@runner@aborted.html
- shard-glk: ([FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#3363] / [k.org#202321]) -> ([FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161]) ([i915#1814] / [i915#2426] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#409] / [k.org#202321])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk8/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk8/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk1/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10508/shard-glk3/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk3/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk3/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk1/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/shard-glk5/igt@runner@aborted.html
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20875/index.html
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