[PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Jani Nikula]

v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
check and an OUI helper patch added.

Jani Nikula (6):
  drm/displayid: re-align data block macros
  drm/displayid: add DisplayID v2.0 data blocks and primary use cases
  drm/edid: abstract OUI conversion to 24-bit int
  drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
  drm/i915/edp: postpone MSO init until after EDID read
  drm/i915/edp: use MSO pixel overlap from DisplayID data

 drivers/gpu/drm/drm_edid.c              |  89 ++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dp.c |  14 ++--
 include/drm/drm_connector.h             |  12 +++
 include/drm/drm_displayid.h             | 101 +++++++++++++++++-------
 4 files changed, 172 insertions(+), 44 deletions(-)

-- 
2.30.2

[Intel-gfx] [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Jani Nikula]

v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
check and an OUI helper patch added.

Jani Nikula (6):
  drm/displayid: re-align data block macros
  drm/displayid: add DisplayID v2.0 data blocks and primary use cases
  drm/edid: abstract OUI conversion to 24-bit int
  drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
  drm/i915/edp: postpone MSO init until after EDID read
  drm/i915/edp: use MSO pixel overlap from DisplayID data

 drivers/gpu/drm/drm_edid.c              |  89 ++++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dp.c |  14 ++--
 include/drm/drm_connector.h             |  12 +++
 include/drm/drm_displayid.h             | 101 +++++++++++++++++-------
 4 files changed, 172 insertions(+), 44 deletions(-)

-- 
2.30.2

[PATCH v2 1/6] drm/displayid: re-align data block macros

[Jani Nikula]

Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
 1 file changed, 29 insertions(+), 28 deletions(-)

diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index ec64d141f578..0ed9445b5482 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,35 +26,36 @@
 
 struct edid;
 
-#define DATA_BLOCK_PRODUCT_ID 0x00
-#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
-#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
-#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
-#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
-#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
-#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
-#define DATA_BLOCK_VESA_TIMING 0x07
-#define DATA_BLOCK_CEA_TIMING 0x08
-#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
-#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
-#define DATA_BLOCK_GP_ASCII_STRING 0x0b
-#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
-#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
-#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
-#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
-#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
-#define DATA_BLOCK_TILED_DISPLAY 0x12
-#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v1r2 Data Blocks */
+#define DATA_BLOCK_PRODUCT_ID			0x00
+#define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
+#define DATA_BLOCK_COLOR_CHARACTERISTICS	0x02
+#define DATA_BLOCK_TYPE_1_DETAILED_TIMING	0x03
+#define DATA_BLOCK_TYPE_2_DETAILED_TIMING	0x04
+#define DATA_BLOCK_TYPE_3_SHORT_TIMING		0x05
+#define DATA_BLOCK_TYPE_4_DMT_TIMING		0x06
+#define DATA_BLOCK_VESA_TIMING			0x07
+#define DATA_BLOCK_CEA_TIMING			0x08
+#define DATA_BLOCK_VIDEO_TIMING_RANGE		0x09
+#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER	0x0a
+#define DATA_BLOCK_GP_ASCII_STRING		0x0b
+#define DATA_BLOCK_DISPLAY_DEVICE_DATA		0x0c
+#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING	0x0d
+#define DATA_BLOCK_TRANSFER_CHARACTERISTICS	0x0e
+#define DATA_BLOCK_DISPLAY_INTERFACE		0x0f
+#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE	0x10
+#define DATA_BLOCK_TILED_DISPLAY		0x12
+#define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
+#define DATA_BLOCK_CTA				0x81
 
-#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
-
-#define PRODUCT_TYPE_EXTENSION 0
-#define PRODUCT_TYPE_TEST 1
-#define PRODUCT_TYPE_PANEL 2
-#define PRODUCT_TYPE_MONITOR 3
-#define PRODUCT_TYPE_TV 4
-#define PRODUCT_TYPE_REPEATER 5
-#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v1r2 Product Type */
+#define PRODUCT_TYPE_EXTENSION			0
+#define PRODUCT_TYPE_TEST			1
+#define PRODUCT_TYPE_PANEL			2
+#define PRODUCT_TYPE_MONITOR			3
+#define PRODUCT_TYPE_TV				4
+#define PRODUCT_TYPE_REPEATER			5
+#define PRODUCT_TYPE_DIRECT_DRIVE		6
 
 struct displayid_header {
 	u8 rev;
-- 
2.30.2

[Intel-gfx] [PATCH v2 1/6] drm/displayid: re-align data block macros

[Jani Nikula]

Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
 1 file changed, 29 insertions(+), 28 deletions(-)

diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index ec64d141f578..0ed9445b5482 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,35 +26,36 @@
 
 struct edid;
 
-#define DATA_BLOCK_PRODUCT_ID 0x00
-#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
-#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
-#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
-#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
-#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
-#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
-#define DATA_BLOCK_VESA_TIMING 0x07
-#define DATA_BLOCK_CEA_TIMING 0x08
-#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
-#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
-#define DATA_BLOCK_GP_ASCII_STRING 0x0b
-#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
-#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
-#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
-#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
-#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
-#define DATA_BLOCK_TILED_DISPLAY 0x12
-#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v1r2 Data Blocks */
+#define DATA_BLOCK_PRODUCT_ID			0x00
+#define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
+#define DATA_BLOCK_COLOR_CHARACTERISTICS	0x02
+#define DATA_BLOCK_TYPE_1_DETAILED_TIMING	0x03
+#define DATA_BLOCK_TYPE_2_DETAILED_TIMING	0x04
+#define DATA_BLOCK_TYPE_3_SHORT_TIMING		0x05
+#define DATA_BLOCK_TYPE_4_DMT_TIMING		0x06
+#define DATA_BLOCK_VESA_TIMING			0x07
+#define DATA_BLOCK_CEA_TIMING			0x08
+#define DATA_BLOCK_VIDEO_TIMING_RANGE		0x09
+#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER	0x0a
+#define DATA_BLOCK_GP_ASCII_STRING		0x0b
+#define DATA_BLOCK_DISPLAY_DEVICE_DATA		0x0c
+#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING	0x0d
+#define DATA_BLOCK_TRANSFER_CHARACTERISTICS	0x0e
+#define DATA_BLOCK_DISPLAY_INTERFACE		0x0f
+#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE	0x10
+#define DATA_BLOCK_TILED_DISPLAY		0x12
+#define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
+#define DATA_BLOCK_CTA				0x81
 
-#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
-
-#define PRODUCT_TYPE_EXTENSION 0
-#define PRODUCT_TYPE_TEST 1
-#define PRODUCT_TYPE_PANEL 2
-#define PRODUCT_TYPE_MONITOR 3
-#define PRODUCT_TYPE_TV 4
-#define PRODUCT_TYPE_REPEATER 5
-#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v1r2 Product Type */
+#define PRODUCT_TYPE_EXTENSION			0
+#define PRODUCT_TYPE_TEST			1
+#define PRODUCT_TYPE_PANEL			2
+#define PRODUCT_TYPE_MONITOR			3
+#define PRODUCT_TYPE_TV				4
+#define PRODUCT_TYPE_REPEATER			5
+#define PRODUCT_TYPE_DIRECT_DRIVE		6
 
 struct displayid_header {
 	u8 rev;
-- 
2.30.2

RE: [PATCH v2 1/6] drm/displayid: re-align data block macros

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 1/6] drm/displayid: re-align data block macros
> 
> Make the values easier to read. Also add DisplayID Structure version and revision
> information (this is different from the spec version).

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
>  1 file changed, 29 insertions(+), 28 deletions(-)
> 
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> ec64d141f578..0ed9445b5482 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -26,35 +26,36 @@
> 
>  struct edid;
> 
> -#define DATA_BLOCK_PRODUCT_ID 0x00
> -#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 -#define
> DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 -#define
> DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 -#define
> DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 -#define
> DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 -#define
> DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 -#define DATA_BLOCK_VESA_TIMING
> 0x07 -#define DATA_BLOCK_CEA_TIMING 0x08 -#define
> DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 -#define
> DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a -#define
> DATA_BLOCK_GP_ASCII_STRING 0x0b -#define
> DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c -#define
> DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d -#define
> DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e -#define
> DATA_BLOCK_DISPLAY_INTERFACE 0x0f -#define
> DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 -#define
> DATA_BLOCK_TILED_DISPLAY 0x12 -#define DATA_BLOCK_CTA 0x81
> +/* DisplayID Structure v1r2 Data Blocks */
> +#define DATA_BLOCK_PRODUCT_ID			0x00
> +#define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
> +#define DATA_BLOCK_COLOR_CHARACTERISTICS	0x02
> +#define DATA_BLOCK_TYPE_1_DETAILED_TIMING	0x03
> +#define DATA_BLOCK_TYPE_2_DETAILED_TIMING	0x04
> +#define DATA_BLOCK_TYPE_3_SHORT_TIMING		0x05
> +#define DATA_BLOCK_TYPE_4_DMT_TIMING		0x06
> +#define DATA_BLOCK_VESA_TIMING			0x07
> +#define DATA_BLOCK_CEA_TIMING			0x08
> +#define DATA_BLOCK_VIDEO_TIMING_RANGE		0x09
> +#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER	0x0a
> +#define DATA_BLOCK_GP_ASCII_STRING		0x0b
> +#define DATA_BLOCK_DISPLAY_DEVICE_DATA		0x0c
> +#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING	0x0d
> +#define DATA_BLOCK_TRANSFER_CHARACTERISTICS	0x0e
> +#define DATA_BLOCK_DISPLAY_INTERFACE		0x0f
> +#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE	0x10
> +#define DATA_BLOCK_TILED_DISPLAY		0x12
> +#define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
> +#define DATA_BLOCK_CTA				0x81
> 
> -#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
> -
> -#define PRODUCT_TYPE_EXTENSION 0
> -#define PRODUCT_TYPE_TEST 1
> -#define PRODUCT_TYPE_PANEL 2
> -#define PRODUCT_TYPE_MONITOR 3
> -#define PRODUCT_TYPE_TV 4
> -#define PRODUCT_TYPE_REPEATER 5
> -#define PRODUCT_TYPE_DIRECT_DRIVE 6
> +/* DisplayID Structure v1r2 Product Type */
> +#define PRODUCT_TYPE_EXTENSION			0
> +#define PRODUCT_TYPE_TEST			1
> +#define PRODUCT_TYPE_PANEL			2
> +#define PRODUCT_TYPE_MONITOR			3
> +#define PRODUCT_TYPE_TV				4
> +#define PRODUCT_TYPE_REPEATER			5
> +#define PRODUCT_TYPE_DIRECT_DRIVE		6
> 
>  struct displayid_header {
>  	u8 rev;
> --
> 2.30.2

Re: [Intel-gfx] [PATCH v2 1/6] drm/displayid: re-align data block macros

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 1/6] drm/displayid: re-align data block macros
> 
> Make the values easier to read. Also add DisplayID Structure version and revision
> information (this is different from the spec version).

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
>  1 file changed, 29 insertions(+), 28 deletions(-)
> 
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> ec64d141f578..0ed9445b5482 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -26,35 +26,36 @@
> 
>  struct edid;
> 
> -#define DATA_BLOCK_PRODUCT_ID 0x00
> -#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01 -#define
> DATA_BLOCK_COLOR_CHARACTERISTICS 0x02 -#define
> DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03 -#define
> DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04 -#define
> DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05 -#define
> DATA_BLOCK_TYPE_4_DMT_TIMING 0x06 -#define DATA_BLOCK_VESA_TIMING
> 0x07 -#define DATA_BLOCK_CEA_TIMING 0x08 -#define
> DATA_BLOCK_VIDEO_TIMING_RANGE 0x09 -#define
> DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a -#define
> DATA_BLOCK_GP_ASCII_STRING 0x0b -#define
> DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c -#define
> DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d -#define
> DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e -#define
> DATA_BLOCK_DISPLAY_INTERFACE 0x0f -#define
> DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10 -#define
> DATA_BLOCK_TILED_DISPLAY 0x12 -#define DATA_BLOCK_CTA 0x81
> +/* DisplayID Structure v1r2 Data Blocks */
> +#define DATA_BLOCK_PRODUCT_ID			0x00
> +#define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
> +#define DATA_BLOCK_COLOR_CHARACTERISTICS	0x02
> +#define DATA_BLOCK_TYPE_1_DETAILED_TIMING	0x03
> +#define DATA_BLOCK_TYPE_2_DETAILED_TIMING	0x04
> +#define DATA_BLOCK_TYPE_3_SHORT_TIMING		0x05
> +#define DATA_BLOCK_TYPE_4_DMT_TIMING		0x06
> +#define DATA_BLOCK_VESA_TIMING			0x07
> +#define DATA_BLOCK_CEA_TIMING			0x08
> +#define DATA_BLOCK_VIDEO_TIMING_RANGE		0x09
> +#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER	0x0a
> +#define DATA_BLOCK_GP_ASCII_STRING		0x0b
> +#define DATA_BLOCK_DISPLAY_DEVICE_DATA		0x0c
> +#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING	0x0d
> +#define DATA_BLOCK_TRANSFER_CHARACTERISTICS	0x0e
> +#define DATA_BLOCK_DISPLAY_INTERFACE		0x0f
> +#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE	0x10
> +#define DATA_BLOCK_TILED_DISPLAY		0x12
> +#define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
> +#define DATA_BLOCK_CTA				0x81
> 
> -#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
> -
> -#define PRODUCT_TYPE_EXTENSION 0
> -#define PRODUCT_TYPE_TEST 1
> -#define PRODUCT_TYPE_PANEL 2
> -#define PRODUCT_TYPE_MONITOR 3
> -#define PRODUCT_TYPE_TV 4
> -#define PRODUCT_TYPE_REPEATER 5
> -#define PRODUCT_TYPE_DIRECT_DRIVE 6
> +/* DisplayID Structure v1r2 Product Type */
> +#define PRODUCT_TYPE_EXTENSION			0
> +#define PRODUCT_TYPE_TEST			1
> +#define PRODUCT_TYPE_PANEL			2
> +#define PRODUCT_TYPE_MONITOR			3
> +#define PRODUCT_TYPE_TV				4
> +#define PRODUCT_TYPE_REPEATER			5
> +#define PRODUCT_TYPE_DIRECT_DRIVE		6
> 
>  struct displayid_header {
>  	u8 rev;
> --
> 2.30.2

[PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and primary use cases

[Jani Nikula]

DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 0ed9445b5482..79771091771a 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,6 +26,10 @@
 
 struct edid;
 
+/* DisplayID Structure versions */
+#define DISPLAY_ID_STRUCTURE_VER_12		0x12
+#define DISPLAY_ID_STRUCTURE_VER_20		0x20
+
 /* DisplayID Structure v1r2 Data Blocks */
 #define DATA_BLOCK_PRODUCT_ID			0x00
 #define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
@@ -48,6 +52,20 @@ struct edid;
 #define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
 #define DATA_BLOCK_CTA				0x81
 
+/* DisplayID Structure v2r0 Data Blocks */
+#define DATA_BLOCK_2_PRODUCT_ID			0x20
+#define DATA_BLOCK_2_DISPLAY_PARAMETERS		0x21
+#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING	0x22
+#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING	0x23
+#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING	0x24
+#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING	0x25
+#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES	0x26
+#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE	0x27
+#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY	0x28
+#define DATA_BLOCK_2_CONTAINER_ID		0x29
+#define DATA_BLOCK_2_VENDOR_SPECIFIC		0x7e
+#define DATA_BLOCK_2_CTA_DISPLAY_ID		0x81
+
 /* DisplayID Structure v1r2 Product Type */
 #define PRODUCT_TYPE_EXTENSION			0
 #define PRODUCT_TYPE_TEST			1
@@ -57,6 +75,17 @@ struct edid;
 #define PRODUCT_TYPE_REPEATER			5
 #define PRODUCT_TYPE_DIRECT_DRIVE		6
 
+/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
+#define PRIMARY_USE_EXTENSION			0
+#define PRIMARY_USE_TEST			1
+#define PRIMARY_USE_GENERIC			2
+#define PRIMARY_USE_TV				3
+#define PRIMARY_USE_DESKTOP_PRODUCTIVITY	4
+#define PRIMARY_USE_DESKTOP_GAMING		5
+#define PRIMARY_USE_PRESENTATION		6
+#define PRIMARY_USE_HEAD_MOUNTED_VR		7
+#define PRIMARY_USE_HEAD_MOUNTED_AR		8
+
 struct displayid_header {
 	u8 rev;
 	u8 bytes;
-- 
2.30.2

[Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and primary use cases

[Jani Nikula]

DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 0ed9445b5482..79771091771a 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,6 +26,10 @@
 
 struct edid;
 
+/* DisplayID Structure versions */
+#define DISPLAY_ID_STRUCTURE_VER_12		0x12
+#define DISPLAY_ID_STRUCTURE_VER_20		0x20
+
 /* DisplayID Structure v1r2 Data Blocks */
 #define DATA_BLOCK_PRODUCT_ID			0x00
 #define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
@@ -48,6 +52,20 @@ struct edid;
 #define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
 #define DATA_BLOCK_CTA				0x81
 
+/* DisplayID Structure v2r0 Data Blocks */
+#define DATA_BLOCK_2_PRODUCT_ID			0x20
+#define DATA_BLOCK_2_DISPLAY_PARAMETERS		0x21
+#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING	0x22
+#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING	0x23
+#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING	0x24
+#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING	0x25
+#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES	0x26
+#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE	0x27
+#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY	0x28
+#define DATA_BLOCK_2_CONTAINER_ID		0x29
+#define DATA_BLOCK_2_VENDOR_SPECIFIC		0x7e
+#define DATA_BLOCK_2_CTA_DISPLAY_ID		0x81
+
 /* DisplayID Structure v1r2 Product Type */
 #define PRODUCT_TYPE_EXTENSION			0
 #define PRODUCT_TYPE_TEST			1
@@ -57,6 +75,17 @@ struct edid;
 #define PRODUCT_TYPE_REPEATER			5
 #define PRODUCT_TYPE_DIRECT_DRIVE		6
 
+/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
+#define PRIMARY_USE_EXTENSION			0
+#define PRIMARY_USE_TEST			1
+#define PRIMARY_USE_GENERIC			2
+#define PRIMARY_USE_TV				3
+#define PRIMARY_USE_DESKTOP_PRODUCTIVITY	4
+#define PRIMARY_USE_DESKTOP_GAMING		5
+#define PRIMARY_USE_PRESENTATION		6
+#define PRIMARY_USE_HEAD_MOUNTED_VR		7
+#define PRIMARY_USE_HEAD_MOUNTED_AR		8
+
 struct displayid_header {
 	u8 rev;
 	u8 bytes;
-- 
2.30.2

RE: [Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and primary use cases

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and
> primary use cases
> 
> DisplayID v2.0 changes the data block identifiers and product types (now called
> primary use cases).

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> 0ed9445b5482..79771091771a 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -26,6 +26,10 @@
> 
>  struct edid;
> 
> +/* DisplayID Structure versions */
> +#define DISPLAY_ID_STRUCTURE_VER_12		0x12
> +#define DISPLAY_ID_STRUCTURE_VER_20		0x20
> +
>  /* DisplayID Structure v1r2 Data Blocks */
>  #define DATA_BLOCK_PRODUCT_ID			0x00
>  #define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
> @@ -48,6 +52,20 @@ struct edid;
>  #define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
>  #define DATA_BLOCK_CTA				0x81
> 
> +/* DisplayID Structure v2r0 Data Blocks */
> +#define DATA_BLOCK_2_PRODUCT_ID			0x20
> +#define DATA_BLOCK_2_DISPLAY_PARAMETERS		0x21
> +#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING	0x22
> +#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING	0x23
> +#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING	0x24
> +#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING	0x25
> +#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES	0x26
> +#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE	0x27
> +#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY	0x28
> +#define DATA_BLOCK_2_CONTAINER_ID		0x29
> +#define DATA_BLOCK_2_VENDOR_SPECIFIC		0x7e
> +#define DATA_BLOCK_2_CTA_DISPLAY_ID		0x81
> +
>  /* DisplayID Structure v1r2 Product Type */
>  #define PRODUCT_TYPE_EXTENSION			0
>  #define PRODUCT_TYPE_TEST			1
> @@ -57,6 +75,17 @@ struct edid;
>  #define PRODUCT_TYPE_REPEATER			5
>  #define PRODUCT_TYPE_DIRECT_DRIVE		6
> 
> +/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
> +#define PRIMARY_USE_EXTENSION			0
> +#define PRIMARY_USE_TEST			1
> +#define PRIMARY_USE_GENERIC			2
> +#define PRIMARY_USE_TV				3
> +#define PRIMARY_USE_DESKTOP_PRODUCTIVITY	4
> +#define PRIMARY_USE_DESKTOP_GAMING		5
> +#define PRIMARY_USE_PRESENTATION		6
> +#define PRIMARY_USE_HEAD_MOUNTED_VR		7
> +#define PRIMARY_USE_HEAD_MOUNTED_AR		8
> +
>  struct displayid_header {
>  	u8 rev;
>  	u8 bytes;
> --
> 2.30.2

Re: [Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and primary use cases

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 2/6] drm/displayid: add DisplayID v2.0 data blocks and
> primary use cases
> 
> DisplayID v2.0 changes the data block identifiers and product types (now called
> primary use cases).

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> 0ed9445b5482..79771091771a 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -26,6 +26,10 @@
> 
>  struct edid;
> 
> +/* DisplayID Structure versions */
> +#define DISPLAY_ID_STRUCTURE_VER_12		0x12
> +#define DISPLAY_ID_STRUCTURE_VER_20		0x20
> +
>  /* DisplayID Structure v1r2 Data Blocks */
>  #define DATA_BLOCK_PRODUCT_ID			0x00
>  #define DATA_BLOCK_DISPLAY_PARAMETERS		0x01
> @@ -48,6 +52,20 @@ struct edid;
>  #define DATA_BLOCK_VENDOR_SPECIFIC		0x7f
>  #define DATA_BLOCK_CTA				0x81
> 
> +/* DisplayID Structure v2r0 Data Blocks */
> +#define DATA_BLOCK_2_PRODUCT_ID			0x20
> +#define DATA_BLOCK_2_DISPLAY_PARAMETERS		0x21
> +#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING	0x22
> +#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING	0x23
> +#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING	0x24
> +#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING	0x25
> +#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES	0x26
> +#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE	0x27
> +#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY	0x28
> +#define DATA_BLOCK_2_CONTAINER_ID		0x29
> +#define DATA_BLOCK_2_VENDOR_SPECIFIC		0x7e
> +#define DATA_BLOCK_2_CTA_DISPLAY_ID		0x81
> +
>  /* DisplayID Structure v1r2 Product Type */
>  #define PRODUCT_TYPE_EXTENSION			0
>  #define PRODUCT_TYPE_TEST			1
> @@ -57,6 +75,17 @@ struct edid;
>  #define PRODUCT_TYPE_REPEATER			5
>  #define PRODUCT_TYPE_DIRECT_DRIVE		6
> 
> +/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
> +#define PRIMARY_USE_EXTENSION			0
> +#define PRIMARY_USE_TEST			1
> +#define PRIMARY_USE_GENERIC			2
> +#define PRIMARY_USE_TV				3
> +#define PRIMARY_USE_DESKTOP_PRODUCTIVITY	4
> +#define PRIMARY_USE_DESKTOP_GAMING		5
> +#define PRIMARY_USE_PRESENTATION		6
> +#define PRIMARY_USE_HEAD_MOUNTED_VR		7
> +#define PRIMARY_USE_HEAD_MOUNTED_AR		8
> +
>  struct displayid_header {
>  	u8 rev;
>  	u8 bytes;
> --
> 2.30.2

[PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int

[Jani Nikula]

Replace the open coded OUI conversion from three bytes to a 24-bit int,
as we'll be adding one more user shortly. No functional changes.

Side note: CTA-861 format has the OUI bytes in reverse order.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_edid.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..92974b1478bc 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -49,6 +49,11 @@
 	(((edid)->version > (maj)) || \
 	 ((edid)->version == (maj) && (edid)->revision > (min)))
 
+static int oui(u8 first, u8 second, u8 third)
+{
+	return (first << 16) | (second << 8) | third;
+}
+
 #define EDID_EST_TIMINGS 16
 #define EDID_STD_TIMINGS 8
 #define EDID_DETAILED_TIMINGS 4
@@ -4113,32 +4118,24 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
 
 static bool cea_db_is_hdmi_vsdb(const u8 *db)
 {
-	int hdmi_id;
-
 	if (cea_db_tag(db) != VENDOR_BLOCK)
 		return false;
 
 	if (cea_db_payload_len(db) < 5)
 		return false;
 
-	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
-
-	return hdmi_id == HDMI_IEEE_OUI;
+	return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
 }
 
 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
 {
-	unsigned int oui;
-
 	if (cea_db_tag(db) != VENDOR_BLOCK)
 		return false;
 
 	if (cea_db_payload_len(db) < 7)
 		return false;
 
-	oui = db[3] << 16 | db[2] << 8 | db[1];
-
-	return oui == HDMI_FORUM_IEEE_OUI;
+	return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
 }
 
 static bool cea_db_is_vcdb(const u8 *db)
-- 
2.30.2

[Intel-gfx] [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int

[Jani Nikula]

Replace the open coded OUI conversion from three bytes to a 24-bit int,
as we'll be adding one more user shortly. No functional changes.

Side note: CTA-861 format has the OUI bytes in reverse order.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_edid.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..92974b1478bc 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -49,6 +49,11 @@
 	(((edid)->version > (maj)) || \
 	 ((edid)->version == (maj) && (edid)->revision > (min)))
 
+static int oui(u8 first, u8 second, u8 third)
+{
+	return (first << 16) | (second << 8) | third;
+}
+
 #define EDID_EST_TIMINGS 16
 #define EDID_STD_TIMINGS 8
 #define EDID_DETAILED_TIMINGS 4
@@ -4113,32 +4118,24 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
 
 static bool cea_db_is_hdmi_vsdb(const u8 *db)
 {
-	int hdmi_id;
-
 	if (cea_db_tag(db) != VENDOR_BLOCK)
 		return false;
 
 	if (cea_db_payload_len(db) < 5)
 		return false;
 
-	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
-
-	return hdmi_id == HDMI_IEEE_OUI;
+	return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
 }
 
 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
 {
-	unsigned int oui;
-
 	if (cea_db_tag(db) != VENDOR_BLOCK)
 		return false;
 
 	if (cea_db_payload_len(db) < 7)
 		return false;
 
-	oui = db[3] << 16 | db[2] << 8 | db[1];
-
-	return oui == HDMI_FORUM_IEEE_OUI;
+	return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
 }
 
 static bool cea_db_is_vcdb(const u8 *db)
-- 
2.30.2

RE: [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int
> 
> Replace the open coded OUI conversion from three bytes to a 24-bit int, as we'll be
> adding one more user shortly. No functional changes.
> 
> Side note: CTA-861 format has the OUI bytes in reverse order.

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 6325877c5fd6..92974b1478bc 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -49,6 +49,11 @@
>  	(((edid)->version > (maj)) || \
>  	 ((edid)->version == (maj) && (edid)->revision > (min)))
> 
> +static int oui(u8 first, u8 second, u8 third) {
> +	return (first << 16) | (second << 8) | third; }
> +
>  #define EDID_EST_TIMINGS 16
>  #define EDID_STD_TIMINGS 8
>  #define EDID_DETAILED_TIMINGS 4
> @@ -4113,32 +4118,24 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> 
>  static bool cea_db_is_hdmi_vsdb(const u8 *db)  {
> -	int hdmi_id;
> -
>  	if (cea_db_tag(db) != VENDOR_BLOCK)
>  		return false;
> 
>  	if (cea_db_payload_len(db) < 5)
>  		return false;
> 
> -	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
> -
> -	return hdmi_id == HDMI_IEEE_OUI;
> +	return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
>  }
> 
>  static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)  {
> -	unsigned int oui;
> -
>  	if (cea_db_tag(db) != VENDOR_BLOCK)
>  		return false;
> 
>  	if (cea_db_payload_len(db) < 7)
>  		return false;
> 
> -	oui = db[3] << 16 | db[2] << 8 | db[1];
> -
> -	return oui == HDMI_FORUM_IEEE_OUI;
> +	return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
>  }
> 
>  static bool cea_db_is_vcdb(const u8 *db)
> --
> 2.30.2

Re: [Intel-gfx] [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 3/6] drm/edid: abstract OUI conversion to 24-bit int
> 
> Replace the open coded OUI conversion from three bytes to a 24-bit int, as we'll be
> adding one more user shortly. No functional changes.
> 
> Side note: CTA-861 format has the OUI bytes in reverse order.

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c | 17 +++++++----------
>  1 file changed, 7 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 6325877c5fd6..92974b1478bc 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -49,6 +49,11 @@
>  	(((edid)->version > (maj)) || \
>  	 ((edid)->version == (maj) && (edid)->revision > (min)))
> 
> +static int oui(u8 first, u8 second, u8 third) {
> +	return (first << 16) | (second << 8) | third; }
> +
>  #define EDID_EST_TIMINGS 16
>  #define EDID_STD_TIMINGS 8
>  #define EDID_DETAILED_TIMINGS 4
> @@ -4113,32 +4118,24 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> 
>  static bool cea_db_is_hdmi_vsdb(const u8 *db)  {
> -	int hdmi_id;
> -
>  	if (cea_db_tag(db) != VENDOR_BLOCK)
>  		return false;
> 
>  	if (cea_db_payload_len(db) < 5)
>  		return false;
> 
> -	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
> -
> -	return hdmi_id == HDMI_IEEE_OUI;
> +	return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;
>  }
> 
>  static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)  {
> -	unsigned int oui;
> -
>  	if (cea_db_tag(db) != VENDOR_BLOCK)
>  		return false;
> 
>  	if (cea_db_payload_len(db) < 7)
>  		return false;
> 
> -	oui = db[3] << 16 | db[2] << 8 | db[1];
> -
> -	return oui == HDMI_FORUM_IEEE_OUI;
> +	return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;
>  }
> 
>  static bool cea_db_is_vcdb(const u8 *db)
> --
> 2.30.2

[PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Jani Nikula]

The VESA Organization Vendor-Specific Data Block, defined in VESA
DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
stream count and segment pixel overlap.

DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
describing how DisplayID sections may be embedded in EDID extension
blocks. DisplayID v2.0 does not have such a section, perhaps implying
that DisplayID v2.0 data should not be included in EDID extensions, but
rather in a "pure" DisplayID structure at its own DDC address pair
A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.

However, in practice, displays out in the field have embedded DisplayID
v2.0 data blocks in EDID extensions, including, in particular, some eDP
MSO displays, where a pure DisplayID structure is not available at all.

Parse the MSO data from the DisplayID data block. Do it as part of
drm_add_display_info(), extending it to parse also DisplayID data to
avoid requiring extra calls to update the information.

v2: Check for VESA OUI (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h | 12 +++++++
 include/drm/drm_displayid.h | 13 +++++++
 3 files changed, 97 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 92974b1478bc..c45c225267ca 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -28,6 +28,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <linux/bitfield.h>
 #include <linux/hdmi.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
@@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector *connector,
 		      info->monitor_range.max_vfreq);
 }
 
+static void drm_parse_vesa_mso_data(struct drm_connector *connector,
+				    const struct displayid_block *block)
+{
+	struct displayid_vesa_vendor_specific_block *vesa =
+		(struct displayid_vesa_vendor_specific_block *)block;
+	struct drm_display_info *info = &connector->display_info;
+
+	if (block->num_bytes < 3) {
+		drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
+			    block->num_bytes);
+		return;
+	}
+
+	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
+		return;
+
+	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
+		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
+		return;
+	}
+
+	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+	default:
+		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
+		fallthrough;
+	case 0:
+		info->mso_stream_count = 0;
+		break;
+	case 1:
+		info->mso_stream_count = 2; /* 2 or 4 links */
+		break;
+	case 2:
+		info->mso_stream_count = 4; /* 4 links */
+		break;
+	}
+
+	if (!info->mso_stream_count) {
+		info->mso_pixel_overlap = 0;
+		return;
+	}
+
+	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
+	if (info->mso_pixel_overlap > 8) {
+		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
+			    info->mso_pixel_overlap);
+		info->mso_pixel_overlap = 8;
+	}
+
+	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
+		    info->mso_stream_count, info->mso_pixel_overlap);
+}
+
+static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
+{
+	const struct displayid_block *block;
+	struct displayid_iter iter;
+
+	displayid_iter_edid_begin(edid, &iter);
+	displayid_iter_for_each(block, &iter) {
+		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
+			drm_parse_vesa_mso_data(connector, block);
+	}
+	displayid_iter_end(&iter);
+}
+
 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
  * all of the values which would have been set from EDID
  */
@@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector *connector)
 
 	info->non_desktop = 0;
 	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
+
+	info->mso_stream_count = 0;
+	info->mso_pixel_overlap = 0;
 }
 
 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
@@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
 		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
 	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
 		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
+
+	drm_update_mso(connector, edid);
+
 	return quirks;
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 79fa34e5ccdb..379746d3266f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -590,6 +590,18 @@ struct drm_display_info {
 	 * @monitor_range: Frequency range supported by monitor range descriptor
 	 */
 	struct drm_monitor_range_info monitor_range;
+
+	/**
+	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
+	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
+	 * Transport (SST), or 2 or 4 MSO streams.
+	 */
+	u8 mso_stream_count;
+
+	/**
+	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
+	 */
+	u8 mso_pixel_overlap;
 };
 
 int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 79771091771a..7ffbd9f7bfc7 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -23,9 +23,12 @@
 #define DRM_DISPLAYID_H
 
 #include <linux/types.h>
+#include <linux/bits.h>
 
 struct edid;
 
+#define VESA_IEEE_OUI				0x3a0292
+
 /* DisplayID Structure versions */
 #define DISPLAY_ID_STRUCTURE_VER_12		0x12
 #define DISPLAY_ID_STRUCTURE_VER_20		0x20
@@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
 	struct displayid_detailed_timings_1 timings[];
 };
 
+#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
+#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
+
+struct displayid_vesa_vendor_specific_block {
+	struct displayid_block base;
+	u8 oui[3];
+	u8 data_structure_type;
+	u8 mso;
+} __packed;
+
 /* DisplayID iteration */
 struct displayid_iter {
 	const struct edid *edid;
-- 
2.30.2

[Intel-gfx] [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Jani Nikula]

The VESA Organization Vendor-Specific Data Block, defined in VESA
DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
stream count and segment pixel overlap.

DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
describing how DisplayID sections may be embedded in EDID extension
blocks. DisplayID v2.0 does not have such a section, perhaps implying
that DisplayID v2.0 data should not be included in EDID extensions, but
rather in a "pure" DisplayID structure at its own DDC address pair
A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.

However, in practice, displays out in the field have embedded DisplayID
v2.0 data blocks in EDID extensions, including, in particular, some eDP
MSO displays, where a pure DisplayID structure is not available at all.

Parse the MSO data from the DisplayID data block. Do it as part of
drm_add_display_info(), extending it to parse also DisplayID data to
avoid requiring extra calls to update the information.

v2: Check for VESA OUI (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
 include/drm/drm_connector.h | 12 +++++++
 include/drm/drm_displayid.h | 13 +++++++
 3 files changed, 97 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 92974b1478bc..c45c225267ca 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -28,6 +28,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <linux/bitfield.h>
 #include <linux/hdmi.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
@@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector *connector,
 		      info->monitor_range.max_vfreq);
 }
 
+static void drm_parse_vesa_mso_data(struct drm_connector *connector,
+				    const struct displayid_block *block)
+{
+	struct displayid_vesa_vendor_specific_block *vesa =
+		(struct displayid_vesa_vendor_specific_block *)block;
+	struct drm_display_info *info = &connector->display_info;
+
+	if (block->num_bytes < 3) {
+		drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
+			    block->num_bytes);
+		return;
+	}
+
+	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
+		return;
+
+	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
+		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
+		return;
+	}
+
+	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+	default:
+		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
+		fallthrough;
+	case 0:
+		info->mso_stream_count = 0;
+		break;
+	case 1:
+		info->mso_stream_count = 2; /* 2 or 4 links */
+		break;
+	case 2:
+		info->mso_stream_count = 4; /* 4 links */
+		break;
+	}
+
+	if (!info->mso_stream_count) {
+		info->mso_pixel_overlap = 0;
+		return;
+	}
+
+	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
+	if (info->mso_pixel_overlap > 8) {
+		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
+			    info->mso_pixel_overlap);
+		info->mso_pixel_overlap = 8;
+	}
+
+	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
+		    info->mso_stream_count, info->mso_pixel_overlap);
+}
+
+static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
+{
+	const struct displayid_block *block;
+	struct displayid_iter iter;
+
+	displayid_iter_edid_begin(edid, &iter);
+	displayid_iter_for_each(block, &iter) {
+		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
+			drm_parse_vesa_mso_data(connector, block);
+	}
+	displayid_iter_end(&iter);
+}
+
 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
  * all of the values which would have been set from EDID
  */
@@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector *connector)
 
 	info->non_desktop = 0;
 	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
+
+	info->mso_stream_count = 0;
+	info->mso_pixel_overlap = 0;
 }
 
 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
@@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
 		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
 	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
 		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
+
+	drm_update_mso(connector, edid);
+
 	return quirks;
 }
 
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 79fa34e5ccdb..379746d3266f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -590,6 +590,18 @@ struct drm_display_info {
 	 * @monitor_range: Frequency range supported by monitor range descriptor
 	 */
 	struct drm_monitor_range_info monitor_range;
+
+	/**
+	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
+	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
+	 * Transport (SST), or 2 or 4 MSO streams.
+	 */
+	u8 mso_stream_count;
+
+	/**
+	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
+	 */
+	u8 mso_pixel_overlap;
 };
 
 int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 79771091771a..7ffbd9f7bfc7 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -23,9 +23,12 @@
 #define DRM_DISPLAYID_H
 
 #include <linux/types.h>
+#include <linux/bits.h>
 
 struct edid;
 
+#define VESA_IEEE_OUI				0x3a0292
+
 /* DisplayID Structure versions */
 #define DISPLAY_ID_STRUCTURE_VER_12		0x12
 #define DISPLAY_ID_STRUCTURE_VER_20		0x20
@@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
 	struct displayid_detailed_timings_1 timings[];
 };
 
+#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
+#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
+
+struct displayid_vesa_vendor_specific_block {
+	struct displayid_block base;
+	u8 oui[3];
+	u8 data_structure_type;
+	u8 mso;
+} __packed;
+
 /* DisplayID iteration */
 struct displayid_iter {
 	const struct edid *edid;
-- 
2.30.2

RE: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for
> MSO
> 
> The VESA Organization Vendor-Specific Data Block, defined in VESA DisplayID
> Standard v2.0, specifies the eDP Multi-SST Operation (MSO) stream count and
> segment pixel overlap.
> 
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, describing how
> DisplayID sections may be embedded in EDID extension blocks. DisplayID v2.0 does
> not have such a section, perhaps implying that DisplayID v2.0 data should not be
> included in EDID extensions, but rather in a "pure" DisplayID structure at its own DDC
> address pair A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
> 
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP MSO displays,
> where a pure DisplayID structure is not available at all.
> 
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to avoid requiring
> extra calls to update the information.
> 
> v2: Check for VESA OUI (Ville)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h | 12 +++++++  include/drm/drm_displayid.h | 13
> +++++++
>  3 files changed, 97 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 92974b1478bc..c45c225267ca 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -28,6 +28,7 @@
>   * DEALINGS IN THE SOFTWARE.
>   */
> 
> +#include <linux/bitfield.h>
>  #include <linux/hdmi.h>
>  #include <linux/i2c.h>
>  #include <linux/kernel.h>
> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector
> *connector,
>  		      info->monitor_range.max_vfreq);  }
> 
> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> +				    const struct displayid_block *block) {
> +	struct displayid_vesa_vendor_specific_block *vesa =
> +		(struct displayid_vesa_vendor_specific_block *)block;
> +	struct drm_display_info *info = &connector->display_info;
> +
> +	if (block->num_bytes < 3) {
> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
> %u\n",
> +			    block->num_bytes);
> +		return;
> +	}
> +
> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
> +		return;
> +
> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
> size\n");
> +		return;
> +	}
> +
> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> +	default:
> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> +		fallthrough;
> +	case 0:
> +		info->mso_stream_count = 0;
> +		break;
> +	case 1:
> +		info->mso_stream_count = 2; /* 2 or 4 links */
> +		break;
> +	case 2:
> +		info->mso_stream_count = 4; /* 4 links */
> +		break;
> +	}
> +
> +	if (!info->mso_stream_count) {
> +		info->mso_pixel_overlap = 0;
> +		return;
> +	}
> +
> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
> vesa->mso);
> +	if (info->mso_pixel_overlap > 8) {
> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
> %u\n",
> +			    info->mso_pixel_overlap);
> +		info->mso_pixel_overlap = 8;

Going beyond 8 is not right from a vendor perspective as it goes into reserved region.
Should we not just set to 0 or how we decide that we fixed overlap at 8. It seems an
undefined operation and it may vary from sink to sink.

Regards,
Uma Shankar

> +	}
> +
> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> +		    info->mso_stream_count, info->mso_pixel_overlap); }
> +
> +static void drm_update_mso(struct drm_connector *connector, const
> +struct edid *edid) {
> +	const struct displayid_block *block;
> +	struct displayid_iter iter;
> +
> +	displayid_iter_edid_begin(edid, &iter);
> +	displayid_iter_for_each(block, &iter) {
> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> +			drm_parse_vesa_mso_data(connector, block);
> +	}
> +	displayid_iter_end(&iter);
> +}
> +
>  /* A connector has no EDID information, so we've got no EDID to compute quirks
> from. Reset
>   * all of the values which would have been set from EDID
>   */
> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
> *connector)
> 
>  	info->non_desktop = 0;
>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> +
> +	info->mso_stream_count = 0;
> +	info->mso_pixel_overlap = 0;
>  }
> 
>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid
> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector
> *connector, const struct edid *edi
>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> +
> +	drm_update_mso(connector, edid);
> +
>  	return quirks;
>  }
> 
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
> 79fa34e5ccdb..379746d3266f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -590,6 +590,18 @@ struct drm_display_info {
>  	 * @monitor_range: Frequency range supported by monitor range descriptor
>  	 */
>  	struct drm_monitor_range_info monitor_range;
> +
> +	/**
> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> +	 * Transport (SST), or 2 or 4 MSO streams.
> +	 */
> +	u8 mso_stream_count;
> +
> +	/**
> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> +	 */
> +	u8 mso_pixel_overlap;
>  };
> 
>  int drm_display_info_set_bus_formats(struct drm_display_info *info, diff --git
> a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> 79771091771a..7ffbd9f7bfc7 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -23,9 +23,12 @@
>  #define DRM_DISPLAYID_H
> 
>  #include <linux/types.h>
> +#include <linux/bits.h>
> 
>  struct edid;
> 
> +#define VESA_IEEE_OUI				0x3a0292
> +
>  /* DisplayID Structure versions */
>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
>  	struct displayid_detailed_timings_1 timings[];  };
> 
> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
> +
> +struct displayid_vesa_vendor_specific_block {
> +	struct displayid_block base;
> +	u8 oui[3];
> +	u8 data_structure_type;
> +	u8 mso;
> +} __packed;
> +
>  /* DisplayID iteration */
>  struct displayid_iter {
>  	const struct edid *edid;
> --
> 2.30.2

Re: [Intel-gfx] [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Shankar, Uma]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for
> MSO
> 
> The VESA Organization Vendor-Specific Data Block, defined in VESA DisplayID
> Standard v2.0, specifies the eDP Multi-SST Operation (MSO) stream count and
> segment pixel overlap.
> 
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, describing how
> DisplayID sections may be embedded in EDID extension blocks. DisplayID v2.0 does
> not have such a section, perhaps implying that DisplayID v2.0 data should not be
> included in EDID extensions, but rather in a "pure" DisplayID structure at its own DDC
> address pair A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
> 
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP MSO displays,
> where a pure DisplayID structure is not available at all.
> 
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to avoid requiring
> extra calls to update the information.
> 
> v2: Check for VESA OUI (Ville)
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
>  include/drm/drm_connector.h | 12 +++++++  include/drm/drm_displayid.h | 13
> +++++++
>  3 files changed, 97 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
> 92974b1478bc..c45c225267ca 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -28,6 +28,7 @@
>   * DEALINGS IN THE SOFTWARE.
>   */
> 
> +#include <linux/bitfield.h>
>  #include <linux/hdmi.h>
>  #include <linux/i2c.h>
>  #include <linux/kernel.h>
> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector
> *connector,
>  		      info->monitor_range.max_vfreq);  }
> 
> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> +				    const struct displayid_block *block) {
> +	struct displayid_vesa_vendor_specific_block *vesa =
> +		(struct displayid_vesa_vendor_specific_block *)block;
> +	struct drm_display_info *info = &connector->display_info;
> +
> +	if (block->num_bytes < 3) {
> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
> %u\n",
> +			    block->num_bytes);
> +		return;
> +	}
> +
> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
> +		return;
> +
> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
> size\n");
> +		return;
> +	}
> +
> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> +	default:
> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> +		fallthrough;
> +	case 0:
> +		info->mso_stream_count = 0;
> +		break;
> +	case 1:
> +		info->mso_stream_count = 2; /* 2 or 4 links */
> +		break;
> +	case 2:
> +		info->mso_stream_count = 4; /* 4 links */
> +		break;
> +	}
> +
> +	if (!info->mso_stream_count) {
> +		info->mso_pixel_overlap = 0;
> +		return;
> +	}
> +
> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
> vesa->mso);
> +	if (info->mso_pixel_overlap > 8) {
> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
> %u\n",
> +			    info->mso_pixel_overlap);
> +		info->mso_pixel_overlap = 8;

Going beyond 8 is not right from a vendor perspective as it goes into reserved region.
Should we not just set to 0 or how we decide that we fixed overlap at 8. It seems an
undefined operation and it may vary from sink to sink.

Regards,
Uma Shankar

> +	}
> +
> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> +		    info->mso_stream_count, info->mso_pixel_overlap); }
> +
> +static void drm_update_mso(struct drm_connector *connector, const
> +struct edid *edid) {
> +	const struct displayid_block *block;
> +	struct displayid_iter iter;
> +
> +	displayid_iter_edid_begin(edid, &iter);
> +	displayid_iter_for_each(block, &iter) {
> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> +			drm_parse_vesa_mso_data(connector, block);
> +	}
> +	displayid_iter_end(&iter);
> +}
> +
>  /* A connector has no EDID information, so we've got no EDID to compute quirks
> from. Reset
>   * all of the values which would have been set from EDID
>   */
> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
> *connector)
> 
>  	info->non_desktop = 0;
>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> +
> +	info->mso_stream_count = 0;
> +	info->mso_pixel_overlap = 0;
>  }
> 
>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid
> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector
> *connector, const struct edid *edi
>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> +
> +	drm_update_mso(connector, edid);
> +
>  	return quirks;
>  }
> 
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
> 79fa34e5ccdb..379746d3266f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -590,6 +590,18 @@ struct drm_display_info {
>  	 * @monitor_range: Frequency range supported by monitor range descriptor
>  	 */
>  	struct drm_monitor_range_info monitor_range;
> +
> +	/**
> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> +	 * Transport (SST), or 2 or 4 MSO streams.
> +	 */
> +	u8 mso_stream_count;
> +
> +	/**
> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> +	 */
> +	u8 mso_pixel_overlap;
>  };
> 
>  int drm_display_info_set_bus_formats(struct drm_display_info *info, diff --git
> a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
> 79771091771a..7ffbd9f7bfc7 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -23,9 +23,12 @@
>  #define DRM_DISPLAYID_H
> 
>  #include <linux/types.h>
> +#include <linux/bits.h>
> 
>  struct edid;
> 
> +#define VESA_IEEE_OUI				0x3a0292
> +
>  /* DisplayID Structure versions */
>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
>  	struct displayid_detailed_timings_1 timings[];  };
> 
> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
> +
> +struct displayid_vesa_vendor_specific_block {
> +	struct displayid_block base;
> +	u8 oui[3];
> +	u8 data_structure_type;
> +	u8 mso;
> +} __packed;
> +
>  /* DisplayID iteration */
>  struct displayid_iter {
>  	const struct edid *edid;
> --
> 2.30.2

RE: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Jani Nikula]

On Mon, 13 Sep 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
>> Sent: Tuesday, August 31, 2021 7:48 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
>> <jani.nikula@intel.com>
>> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for
>> MSO
>> 
>> The VESA Organization Vendor-Specific Data Block, defined in VESA DisplayID
>> Standard v2.0, specifies the eDP Multi-SST Operation (MSO) stream count and
>> segment pixel overlap.
>> 
>> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, describing how
>> DisplayID sections may be embedded in EDID extension blocks. DisplayID v2.0 does
>> not have such a section, perhaps implying that DisplayID v2.0 data should not be
>> included in EDID extensions, but rather in a "pure" DisplayID structure at its own DDC
>> address pair A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>> 
>> However, in practice, displays out in the field have embedded DisplayID
>> v2.0 data blocks in EDID extensions, including, in particular, some eDP MSO displays,
>> where a pure DisplayID structure is not available at all.
>> 
>> Parse the MSO data from the DisplayID data block. Do it as part of
>> drm_add_display_info(), extending it to parse also DisplayID data to avoid requiring
>> extra calls to update the information.
>> 
>> v2: Check for VESA OUI (Ville)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
>>  include/drm/drm_connector.h | 12 +++++++  include/drm/drm_displayid.h | 13
>> +++++++
>>  3 files changed, 97 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
>> 92974b1478bc..c45c225267ca 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -28,6 +28,7 @@
>>   * DEALINGS IN THE SOFTWARE.
>>   */
>> 
>> +#include <linux/bitfield.h>
>>  #include <linux/hdmi.h>
>>  #include <linux/i2c.h>
>>  #include <linux/kernel.h>
>> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector
>> *connector,
>>  		      info->monitor_range.max_vfreq);  }
>> 
>> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
>> +				    const struct displayid_block *block) {
>> +	struct displayid_vesa_vendor_specific_block *vesa =
>> +		(struct displayid_vesa_vendor_specific_block *)block;
>> +	struct drm_display_info *info = &connector->display_info;
>> +
>> +	if (block->num_bytes < 3) {
>> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
>> %u\n",
>> +			    block->num_bytes);
>> +		return;
>> +	}
>> +
>> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>> +		return;
>> +
>> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
>> size\n");
>> +		return;
>> +	}
>> +
>> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> +	default:
>> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
>> +		fallthrough;
>> +	case 0:
>> +		info->mso_stream_count = 0;
>> +		break;
>> +	case 1:
>> +		info->mso_stream_count = 2; /* 2 or 4 links */
>> +		break;
>> +	case 2:
>> +		info->mso_stream_count = 4; /* 4 links */
>> +		break;
>> +	}
>> +
>> +	if (!info->mso_stream_count) {
>> +		info->mso_pixel_overlap = 0;
>> +		return;
>> +	}
>> +
>> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
>> vesa->mso);
>> +	if (info->mso_pixel_overlap > 8) {
>> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
>> %u\n",
>> +			    info->mso_pixel_overlap);
>> +		info->mso_pixel_overlap = 8;
>
> Going beyond 8 is not right from a vendor perspective as it goes into reserved region.
> Should we not just set to 0 or how we decide that we fixed overlap at 8. It seems an
> undefined operation and it may vary from sink to sink.

I don't know if there's a right choice here. I don't mind setting it to
0 if you prefer that.

BR,
Jani.


>
> Regards,
> Uma Shankar
>
>> +	}
>> +
>> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
>> +		    info->mso_stream_count, info->mso_pixel_overlap); }
>> +
>> +static void drm_update_mso(struct drm_connector *connector, const
>> +struct edid *edid) {
>> +	const struct displayid_block *block;
>> +	struct displayid_iter iter;
>> +
>> +	displayid_iter_edid_begin(edid, &iter);
>> +	displayid_iter_for_each(block, &iter) {
>> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
>> +			drm_parse_vesa_mso_data(connector, block);
>> +	}
>> +	displayid_iter_end(&iter);
>> +}
>> +
>>  /* A connector has no EDID information, so we've got no EDID to compute quirks
>> from. Reset
>>   * all of the values which would have been set from EDID
>>   */
>> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
>> *connector)
>> 
>>  	info->non_desktop = 0;
>>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
>> +
>> +	info->mso_stream_count = 0;
>> +	info->mso_pixel_overlap = 0;
>>  }
>> 
>>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid
>> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector
>> *connector, const struct edid *edi
>>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
>> +
>> +	drm_update_mso(connector, edid);
>> +
>>  	return quirks;
>>  }
>> 
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
>> 79fa34e5ccdb..379746d3266f 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -590,6 +590,18 @@ struct drm_display_info {
>>  	 * @monitor_range: Frequency range supported by monitor range descriptor
>>  	 */
>>  	struct drm_monitor_range_info monitor_range;
>> +
>> +	/**
>> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
>> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
>> +	 * Transport (SST), or 2 or 4 MSO streams.
>> +	 */
>> +	u8 mso_stream_count;
>> +
>> +	/**
>> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
>> +	 */
>> +	u8 mso_pixel_overlap;
>>  };
>> 
>>  int drm_display_info_set_bus_formats(struct drm_display_info *info, diff --git
>> a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
>> 79771091771a..7ffbd9f7bfc7 100644
>> --- a/include/drm/drm_displayid.h
>> +++ b/include/drm/drm_displayid.h
>> @@ -23,9 +23,12 @@
>>  #define DRM_DISPLAYID_H
>> 
>>  #include <linux/types.h>
>> +#include <linux/bits.h>
>> 
>>  struct edid;
>> 
>> +#define VESA_IEEE_OUI				0x3a0292
>> +
>>  /* DisplayID Structure versions */
>>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
>>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
>> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
>>  	struct displayid_detailed_timings_1 timings[];  };
>> 
>> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
>> +
>> +struct displayid_vesa_vendor_specific_block {
>> +	struct displayid_block base;
>> +	u8 oui[3];
>> +	u8 data_structure_type;
>> +	u8 mso;
>> +} __packed;
>> +
>>  /* DisplayID iteration */
>>  struct displayid_iter {
>>  	const struct edid *edid;
>> --
>> 2.30.2
>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Jani Nikula]

On Mon, 13 Sep 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
>> Sent: Tuesday, August 31, 2021 7:48 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
>> <jani.nikula@intel.com>
>> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for
>> MSO
>> 
>> The VESA Organization Vendor-Specific Data Block, defined in VESA DisplayID
>> Standard v2.0, specifies the eDP Multi-SST Operation (MSO) stream count and
>> segment pixel overlap.
>> 
>> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension, describing how
>> DisplayID sections may be embedded in EDID extension blocks. DisplayID v2.0 does
>> not have such a section, perhaps implying that DisplayID v2.0 data should not be
>> included in EDID extensions, but rather in a "pure" DisplayID structure at its own DDC
>> address pair A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>> 
>> However, in practice, displays out in the field have embedded DisplayID
>> v2.0 data blocks in EDID extensions, including, in particular, some eDP MSO displays,
>> where a pure DisplayID structure is not available at all.
>> 
>> Parse the MSO data from the DisplayID data block. Do it as part of
>> drm_add_display_info(), extending it to parse also DisplayID data to avoid requiring
>> extra calls to update the information.
>> 
>> v2: Check for VESA OUI (Ville)
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/drm_edid.c  | 72 +++++++++++++++++++++++++++++++++++++
>>  include/drm/drm_connector.h | 12 +++++++  include/drm/drm_displayid.h | 13
>> +++++++
>>  3 files changed, 97 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index
>> 92974b1478bc..c45c225267ca 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -28,6 +28,7 @@
>>   * DEALINGS IN THE SOFTWARE.
>>   */
>> 
>> +#include <linux/bitfield.h>
>>  #include <linux/hdmi.h>
>>  #include <linux/i2c.h>
>>  #include <linux/kernel.h>
>> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct drm_connector
>> *connector,
>>  		      info->monitor_range.max_vfreq);  }
>> 
>> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
>> +				    const struct displayid_block *block) {
>> +	struct displayid_vesa_vendor_specific_block *vesa =
>> +		(struct displayid_vesa_vendor_specific_block *)block;
>> +	struct drm_display_info *info = &connector->display_info;
>> +
>> +	if (block->num_bytes < 3) {
>> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
>> %u\n",
>> +			    block->num_bytes);
>> +		return;
>> +	}
>> +
>> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>> +		return;
>> +
>> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
>> size\n");
>> +		return;
>> +	}
>> +
>> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> +	default:
>> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
>> +		fallthrough;
>> +	case 0:
>> +		info->mso_stream_count = 0;
>> +		break;
>> +	case 1:
>> +		info->mso_stream_count = 2; /* 2 or 4 links */
>> +		break;
>> +	case 2:
>> +		info->mso_stream_count = 4; /* 4 links */
>> +		break;
>> +	}
>> +
>> +	if (!info->mso_stream_count) {
>> +		info->mso_pixel_overlap = 0;
>> +		return;
>> +	}
>> +
>> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
>> vesa->mso);
>> +	if (info->mso_pixel_overlap > 8) {
>> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
>> %u\n",
>> +			    info->mso_pixel_overlap);
>> +		info->mso_pixel_overlap = 8;
>
> Going beyond 8 is not right from a vendor perspective as it goes into reserved region.
> Should we not just set to 0 or how we decide that we fixed overlap at 8. It seems an
> undefined operation and it may vary from sink to sink.

I don't know if there's a right choice here. I don't mind setting it to
0 if you prefer that.

BR,
Jani.


>
> Regards,
> Uma Shankar
>
>> +	}
>> +
>> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
>> +		    info->mso_stream_count, info->mso_pixel_overlap); }
>> +
>> +static void drm_update_mso(struct drm_connector *connector, const
>> +struct edid *edid) {
>> +	const struct displayid_block *block;
>> +	struct displayid_iter iter;
>> +
>> +	displayid_iter_edid_begin(edid, &iter);
>> +	displayid_iter_for_each(block, &iter) {
>> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
>> +			drm_parse_vesa_mso_data(connector, block);
>> +	}
>> +	displayid_iter_end(&iter);
>> +}
>> +
>>  /* A connector has no EDID information, so we've got no EDID to compute quirks
>> from. Reset
>>   * all of the values which would have been set from EDID
>>   */
>> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
>> *connector)
>> 
>>  	info->non_desktop = 0;
>>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
>> +
>> +	info->mso_stream_count = 0;
>> +	info->mso_pixel_overlap = 0;
>>  }
>> 
>>  u32 drm_add_display_info(struct drm_connector *connector, const struct edid
>> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct drm_connector
>> *connector, const struct edid *edi
>>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
>> +
>> +	drm_update_mso(connector, edid);
>> +
>>  	return quirks;
>>  }
>> 
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index
>> 79fa34e5ccdb..379746d3266f 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -590,6 +590,18 @@ struct drm_display_info {
>>  	 * @monitor_range: Frequency range supported by monitor range descriptor
>>  	 */
>>  	struct drm_monitor_range_info monitor_range;
>> +
>> +	/**
>> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
>> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
>> +	 * Transport (SST), or 2 or 4 MSO streams.
>> +	 */
>> +	u8 mso_stream_count;
>> +
>> +	/**
>> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
>> +	 */
>> +	u8 mso_pixel_overlap;
>>  };
>> 
>>  int drm_display_info_set_bus_formats(struct drm_display_info *info, diff --git
>> a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h index
>> 79771091771a..7ffbd9f7bfc7 100644
>> --- a/include/drm/drm_displayid.h
>> +++ b/include/drm/drm_displayid.h
>> @@ -23,9 +23,12 @@
>>  #define DRM_DISPLAYID_H
>> 
>>  #include <linux/types.h>
>> +#include <linux/bits.h>
>> 
>>  struct edid;
>> 
>> +#define VESA_IEEE_OUI				0x3a0292
>> +
>>  /* DisplayID Structure versions */
>>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
>>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
>> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
>>  	struct displayid_detailed_timings_1 timings[];  };
>> 
>> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
>> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
>> +
>> +struct displayid_vesa_vendor_specific_block {
>> +	struct displayid_block base;
>> +	u8 oui[3];
>> +	u8 data_structure_type;
>> +	u8 mso;
>> +} __packed;
>> +
>>  /* DisplayID iteration */
>>  struct displayid_iter {
>>  	const struct edid *edid;
>> --
>> 2.30.2
>

-- 
Jani Nikula, Intel Open Source Graphics Center

RE: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, September 13, 2021 3:00 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com
> Subject: RE: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block
> for MSO
> 
> On Mon, 13 Sep 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> -----Original Message-----
> >> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Tuesday, August 31, 2021 7:48 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com;
> >> Nikula, Jani <jani.nikula@intel.com>
> >> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA
> >> vendor block for MSO
> >>
> >> The VESA Organization Vendor-Specific Data Block, defined in VESA
> >> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> >> stream count and segment pixel overlap.
> >>
> >> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> >> describing how DisplayID sections may be embedded in EDID extension
> >> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> >> that DisplayID v2.0 data should not be included in EDID extensions,
> >> but rather in a "pure" DisplayID structure at its own DDC address pair A4h/A5h, as
> described in VESA E-DDC Standard v1.3 chapter 3.
> >>
> >> However, in practice, displays out in the field have embedded
> >> DisplayID
> >> v2.0 data blocks in EDID extensions, including, in particular, some
> >> eDP MSO displays, where a pure DisplayID structure is not available at all.
> >>
> >> Parse the MSO data from the DisplayID data block. Do it as part of
> >> drm_add_display_info(), extending it to parse also DisplayID data to
> >> avoid requiring extra calls to update the information.
> >>
> >> v2: Check for VESA OUI (Ville)
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/drm_edid.c  | 72
> >> +++++++++++++++++++++++++++++++++++++
> >>  include/drm/drm_connector.h | 12 +++++++
> >> include/drm/drm_displayid.h | 13
> >> +++++++
> >>  3 files changed, 97 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> index 92974b1478bc..c45c225267ca 100644
> >> --- a/drivers/gpu/drm/drm_edid.c
> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> @@ -28,6 +28,7 @@
> >>   * DEALINGS IN THE SOFTWARE.
> >>   */
> >>
> >> +#include <linux/bitfield.h>
> >>  #include <linux/hdmi.h>
> >>  #include <linux/i2c.h>
> >>  #include <linux/kernel.h>
> >> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct
> >> drm_connector *connector,
> >>  		      info->monitor_range.max_vfreq);  }
> >>
> >> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> >> +				    const struct displayid_block *block) {
> >> +	struct displayid_vesa_vendor_specific_block *vesa =
> >> +		(struct displayid_vesa_vendor_specific_block *)block;
> >> +	struct drm_display_info *info = &connector->display_info;
> >> +
> >> +	if (block->num_bytes < 3) {
> >> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
> >> %u\n",
> >> +			    block->num_bytes);
> >> +		return;
> >> +	}
> >> +
> >> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
> >> +		return;
> >> +
> >> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> >> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
> >> size\n");
> >> +		return;
> >> +	}
> >> +
> >> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> >> +	default:
> >> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> >> +		fallthrough;
> >> +	case 0:
> >> +		info->mso_stream_count = 0;
> >> +		break;
> >> +	case 1:
> >> +		info->mso_stream_count = 2; /* 2 or 4 links */
> >> +		break;
> >> +	case 2:
> >> +		info->mso_stream_count = 4; /* 4 links */
> >> +		break;
> >> +	}
> >> +
> >> +	if (!info->mso_stream_count) {
> >> +		info->mso_pixel_overlap = 0;
> >> +		return;
> >> +	}
> >> +
> >> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
> >> vesa->mso);
> >> +	if (info->mso_pixel_overlap > 8) {
> >> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
> >> %u\n",
> >> +			    info->mso_pixel_overlap);
> >> +		info->mso_pixel_overlap = 8;
> >
> > Going beyond 8 is not right from a vendor perspective as it goes into reserved
> region.
> > Should we not just set to 0 or how we decide that we fixed overlap at
> > 8. It seems an undefined operation and it may vary from sink to sink.
> 
> I don't know if there's a right choice here. I don't mind setting it to
> 0 if you prefer that.

I feel it will be wrong on a vendor's behalf if he programs anything above 8. But not sure what
should driver do in such case, it's an undefined behavior. If he intentionally programs it as say 20,
fixing at 8 will still lead to some artifacts. 0 only helps in case where this field is corrupted and has
garbage data.

No strong objection, I will leave to your discretion Jani.

With this, all else looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> >
> > Regards,
> > Uma Shankar
> >
> >> +	}
> >> +
> >> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> >> +		    info->mso_stream_count, info->mso_pixel_overlap); }
> >> +
> >> +static void drm_update_mso(struct drm_connector *connector, const
> >> +struct edid *edid) {
> >> +	const struct displayid_block *block;
> >> +	struct displayid_iter iter;
> >> +
> >> +	displayid_iter_edid_begin(edid, &iter);
> >> +	displayid_iter_for_each(block, &iter) {
> >> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> >> +			drm_parse_vesa_mso_data(connector, block);
> >> +	}
> >> +	displayid_iter_end(&iter);
> >> +}
> >> +
> >>  /* A connector has no EDID information, so we've got no EDID to
> >> compute quirks from. Reset
> >>   * all of the values which would have been set from EDID
> >>   */
> >> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
> >> *connector)
> >>
> >>  	info->non_desktop = 0;
> >>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> >> +
> >> +	info->mso_stream_count = 0;
> >> +	info->mso_pixel_overlap = 0;
> >>  }
> >>
> >>  u32 drm_add_display_info(struct drm_connector *connector, const
> >> struct edid
> >> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct
> >> drm_connector *connector, const struct edid *edi
> >>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
> >>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
> >>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> >> +
> >> +	drm_update_mso(connector, edid);
> >> +
> >>  	return quirks;
> >>  }
> >>
> >> diff --git a/include/drm/drm_connector.h
> >> b/include/drm/drm_connector.h index 79fa34e5ccdb..379746d3266f 100644
> >> --- a/include/drm/drm_connector.h
> >> +++ b/include/drm/drm_connector.h
> >> @@ -590,6 +590,18 @@ struct drm_display_info {
> >>  	 * @monitor_range: Frequency range supported by monitor range descriptor
> >>  	 */
> >>  	struct drm_monitor_range_info monitor_range;
> >> +
> >> +	/**
> >> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> >> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> >> +	 * Transport (SST), or 2 or 4 MSO streams.
> >> +	 */
> >> +	u8 mso_stream_count;
> >> +
> >> +	/**
> >> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> >> +	 */
> >> +	u8 mso_pixel_overlap;
> >>  };
> >>
> >>  int drm_display_info_set_bus_formats(struct drm_display_info *info,
> >> diff --git a/include/drm/drm_displayid.h
> >> b/include/drm/drm_displayid.h index
> >> 79771091771a..7ffbd9f7bfc7 100644
> >> --- a/include/drm/drm_displayid.h
> >> +++ b/include/drm/drm_displayid.h
> >> @@ -23,9 +23,12 @@
> >>  #define DRM_DISPLAYID_H
> >>
> >>  #include <linux/types.h>
> >> +#include <linux/bits.h>
> >>
> >>  struct edid;
> >>
> >> +#define VESA_IEEE_OUI				0x3a0292
> >> +
> >>  /* DisplayID Structure versions */
> >>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
> >>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
> >> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
> >>  	struct displayid_detailed_timings_1 timings[];  };
> >>
> >> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
> >> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
> >> +
> >> +struct displayid_vesa_vendor_specific_block {
> >> +	struct displayid_block base;
> >> +	u8 oui[3];
> >> +	u8 data_structure_type;
> >> +	u8 mso;
> >> +} __packed;
> >> +
> >>  /* DisplayID iteration */
> >>  struct displayid_iter {
> >>  	const struct edid *edid;
> >> --
> >> 2.30.2
> >
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Monday, September 13, 2021 3:00 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com
> Subject: RE: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA vendor block
> for MSO
> 
> On Mon, 13 Sep 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> -----Original Message-----
> >> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Tuesday, August 31, 2021 7:48 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com;
> >> Nikula, Jani <jani.nikula@intel.com>
> >> Subject: [PATCH v2 4/6] drm/edid: parse the DisplayID v2.0 VESA
> >> vendor block for MSO
> >>
> >> The VESA Organization Vendor-Specific Data Block, defined in VESA
> >> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> >> stream count and segment pixel overlap.
> >>
> >> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> >> describing how DisplayID sections may be embedded in EDID extension
> >> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> >> that DisplayID v2.0 data should not be included in EDID extensions,
> >> but rather in a "pure" DisplayID structure at its own DDC address pair A4h/A5h, as
> described in VESA E-DDC Standard v1.3 chapter 3.
> >>
> >> However, in practice, displays out in the field have embedded
> >> DisplayID
> >> v2.0 data blocks in EDID extensions, including, in particular, some
> >> eDP MSO displays, where a pure DisplayID structure is not available at all.
> >>
> >> Parse the MSO data from the DisplayID data block. Do it as part of
> >> drm_add_display_info(), extending it to parse also DisplayID data to
> >> avoid requiring extra calls to update the information.
> >>
> >> v2: Check for VESA OUI (Ville)
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/drm_edid.c  | 72
> >> +++++++++++++++++++++++++++++++++++++
> >>  include/drm/drm_connector.h | 12 +++++++
> >> include/drm/drm_displayid.h | 13
> >> +++++++
> >>  3 files changed, 97 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> index 92974b1478bc..c45c225267ca 100644
> >> --- a/drivers/gpu/drm/drm_edid.c
> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> @@ -28,6 +28,7 @@
> >>   * DEALINGS IN THE SOFTWARE.
> >>   */
> >>
> >> +#include <linux/bitfield.h>
> >>  #include <linux/hdmi.h>
> >>  #include <linux/i2c.h>
> >>  #include <linux/kernel.h>
> >> @@ -5145,6 +5146,71 @@ void drm_get_monitor_range(struct
> >> drm_connector *connector,
> >>  		      info->monitor_range.max_vfreq);  }
> >>
> >> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> >> +				    const struct displayid_block *block) {
> >> +	struct displayid_vesa_vendor_specific_block *vesa =
> >> +		(struct displayid_vesa_vendor_specific_block *)block;
> >> +	struct drm_display_info *info = &connector->display_info;
> >> +
> >> +	if (block->num_bytes < 3) {
> >> +		drm_dbg_kms(connector->dev, "Unexpected vendor block size
> >> %u\n",
> >> +			    block->num_bytes);
> >> +		return;
> >> +	}
> >> +
> >> +	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
> >> +		return;
> >> +
> >> +	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> >> +		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block
> >> size\n");
> >> +		return;
> >> +	}
> >> +
> >> +	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> >> +	default:
> >> +		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> >> +		fallthrough;
> >> +	case 0:
> >> +		info->mso_stream_count = 0;
> >> +		break;
> >> +	case 1:
> >> +		info->mso_stream_count = 2; /* 2 or 4 links */
> >> +		break;
> >> +	case 2:
> >> +		info->mso_stream_count = 4; /* 4 links */
> >> +		break;
> >> +	}
> >> +
> >> +	if (!info->mso_stream_count) {
> >> +		info->mso_pixel_overlap = 0;
> >> +		return;
> >> +	}
> >> +
> >> +	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP,
> >> vesa->mso);
> >> +	if (info->mso_pixel_overlap > 8) {
> >> +		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value
> >> %u\n",
> >> +			    info->mso_pixel_overlap);
> >> +		info->mso_pixel_overlap = 8;
> >
> > Going beyond 8 is not right from a vendor perspective as it goes into reserved
> region.
> > Should we not just set to 0 or how we decide that we fixed overlap at
> > 8. It seems an undefined operation and it may vary from sink to sink.
> 
> I don't know if there's a right choice here. I don't mind setting it to
> 0 if you prefer that.

I feel it will be wrong on a vendor's behalf if he programs anything above 8. But not sure what
should driver do in such case, it's an undefined behavior. If he intentionally programs it as say 20,
fixing at 8 will still lead to some artifacts. 0 only helps in case where this field is corrupted and has
garbage data.

No strong objection, I will leave to your discretion Jani.

With this, all else looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> >
> > Regards,
> > Uma Shankar
> >
> >> +	}
> >> +
> >> +	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> >> +		    info->mso_stream_count, info->mso_pixel_overlap); }
> >> +
> >> +static void drm_update_mso(struct drm_connector *connector, const
> >> +struct edid *edid) {
> >> +	const struct displayid_block *block;
> >> +	struct displayid_iter iter;
> >> +
> >> +	displayid_iter_edid_begin(edid, &iter);
> >> +	displayid_iter_for_each(block, &iter) {
> >> +		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
> >> +			drm_parse_vesa_mso_data(connector, block);
> >> +	}
> >> +	displayid_iter_end(&iter);
> >> +}
> >> +
> >>  /* A connector has no EDID information, so we've got no EDID to
> >> compute quirks from. Reset
> >>   * all of the values which would have been set from EDID
> >>   */
> >> @@ -5168,6 +5234,9 @@ drm_reset_display_info(struct drm_connector
> >> *connector)
> >>
> >>  	info->non_desktop = 0;
> >>  	memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> >> +
> >> +	info->mso_stream_count = 0;
> >> +	info->mso_pixel_overlap = 0;
> >>  }
> >>
> >>  u32 drm_add_display_info(struct drm_connector *connector, const
> >> struct edid
> >> *edid) @@ -5246,6 +5315,9 @@ u32 drm_add_display_info(struct
> >> drm_connector *connector, const struct edid *edi
> >>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
> >>  	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
> >>  		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> >> +
> >> +	drm_update_mso(connector, edid);
> >> +
> >>  	return quirks;
> >>  }
> >>
> >> diff --git a/include/drm/drm_connector.h
> >> b/include/drm/drm_connector.h index 79fa34e5ccdb..379746d3266f 100644
> >> --- a/include/drm/drm_connector.h
> >> +++ b/include/drm/drm_connector.h
> >> @@ -590,6 +590,18 @@ struct drm_display_info {
> >>  	 * @monitor_range: Frequency range supported by monitor range descriptor
> >>  	 */
> >>  	struct drm_monitor_range_info monitor_range;
> >> +
> >> +	/**
> >> +	 * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> >> +	 * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> >> +	 * Transport (SST), or 2 or 4 MSO streams.
> >> +	 */
> >> +	u8 mso_stream_count;
> >> +
> >> +	/**
> >> +	 * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> >> +	 */
> >> +	u8 mso_pixel_overlap;
> >>  };
> >>
> >>  int drm_display_info_set_bus_formats(struct drm_display_info *info,
> >> diff --git a/include/drm/drm_displayid.h
> >> b/include/drm/drm_displayid.h index
> >> 79771091771a..7ffbd9f7bfc7 100644
> >> --- a/include/drm/drm_displayid.h
> >> +++ b/include/drm/drm_displayid.h
> >> @@ -23,9 +23,12 @@
> >>  #define DRM_DISPLAYID_H
> >>
> >>  #include <linux/types.h>
> >> +#include <linux/bits.h>
> >>
> >>  struct edid;
> >>
> >> +#define VESA_IEEE_OUI				0x3a0292
> >> +
> >>  /* DisplayID Structure versions */
> >>  #define DISPLAY_ID_STRUCTURE_VER_12		0x12
> >>  #define DISPLAY_ID_STRUCTURE_VER_20		0x20
> >> @@ -126,6 +129,16 @@ struct displayid_detailed_timing_block {
> >>  	struct displayid_detailed_timings_1 timings[];  };
> >>
> >> +#define DISPLAYID_VESA_MSO_OVERLAP	GENMASK(3, 0)
> >> +#define DISPLAYID_VESA_MSO_MODE		GENMASK(6, 5)
> >> +
> >> +struct displayid_vesa_vendor_specific_block {
> >> +	struct displayid_block base;
> >> +	u8 oui[3];
> >> +	u8 data_structure_type;
> >> +	u8 mso;
> >> +} __packed;
> >> +
> >>  /* DisplayID iteration */
> >>  struct displayid_iter {
> >>  	const struct edid *edid;
> >> --
> >> 2.30.2
> >
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

[PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read

[Jani Nikula]

MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 64e8151d13a4..df402f63b741 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2536,8 +2536,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 	 */
 	intel_edp_init_source_oui(intel_dp, true);
 
-	intel_edp_mso_init(intel_dp);
-
 	return true;
 }
 
@@ -4804,6 +4802,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	if (fixed_mode)
 		downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
 
+	/* MSO requires information from the EDID */
+	intel_edp_mso_init(intel_dp);
+
 	/* multiply the mode clock and horizontal timings for MSO */
 	intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
 	intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
-- 
2.30.2

[Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read

[Jani Nikula]

MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 64e8151d13a4..df402f63b741 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2536,8 +2536,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
 	 */
 	intel_edp_init_source_oui(intel_dp, true);
 
-	intel_edp_mso_init(intel_dp);
-
 	return true;
 }
 
@@ -4804,6 +4802,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	if (fixed_mode)
 		downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
 
+	/* MSO requires information from the EDID */
+	intel_edp_mso_init(intel_dp);
+
 	/* multiply the mode clock and horizontal timings for MSO */
 	intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
 	intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
-- 
2.30.2

RE: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID
> read
> 
> MSO will require segment pixel overlap information from the EDID. Postpone MSO
> init until after we've read and cached the EDID.
> 

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 64e8151d13a4..df402f63b741 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2536,8 +2536,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>  	 */
>  	intel_edp_init_source_oui(intel_dp, true);
> 
> -	intel_edp_mso_init(intel_dp);
> -
>  	return true;
>  }
> 
> @@ -4804,6 +4802,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
>  	if (fixed_mode)
>  		downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
> 
> +	/* MSO requires information from the EDID */
> +	intel_edp_mso_init(intel_dp);
> +
>  	/* multiply the mode clock and horizontal timings for MSO */
>  	intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
>  	intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
> --
> 2.30.2

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID
> read
> 
> MSO will require segment pixel overlap information from the EDID. Postpone MSO
> init until after we've read and cached the EDID.
> 

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 64e8151d13a4..df402f63b741 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2536,8 +2536,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>  	 */
>  	intel_edp_init_source_oui(intel_dp, true);
> 
> -	intel_edp_mso_init(intel_dp);
> -
>  	return true;
>  }
> 
> @@ -4804,6 +4802,9 @@ static bool intel_edp_init_connector(struct intel_dp
> *intel_dp,
>  	if (fixed_mode)
>  		downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
> 
> +	/* MSO requires information from the EDID */
> +	intel_edp_mso_init(intel_dp);
> +
>  	/* multiply the mode clock and horizontal timings for MSO */
>  	intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
>  	intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
> --
> 2.30.2

[PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data

[Jani Nikula]

Now that we have MSO pixel overlap in display info, use it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index df402f63b741..baf21f9aa40e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
 static void intel_edp_mso_init(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct intel_connector *connector = intel_dp->attached_connector;
+	struct drm_display_info *info = &connector->base.display_info;
 	u8 mso;
 
 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
@@ -2438,8 +2440,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
 	}
 
 	if (mso) {
-		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
-			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
+		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
+			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
+			    info->mso_pixel_overlap);
 		if (!HAS_MSO(i915)) {
 			drm_err(&i915->drm, "No source MSO support, disabling\n");
 			mso = 0;
@@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
 	}
 
 	intel_dp->mso_link_count = mso;
-	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
+	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
 }
 
 static bool
-- 
2.30.2

[Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data

[Jani Nikula]

Now that we have MSO pixel overlap in display info, use it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index df402f63b741..baf21f9aa40e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
 static void intel_edp_mso_init(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	struct intel_connector *connector = intel_dp->attached_connector;
+	struct drm_display_info *info = &connector->base.display_info;
 	u8 mso;
 
 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
@@ -2438,8 +2440,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
 	}
 
 	if (mso) {
-		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
-			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
+		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
+			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
+			    info->mso_pixel_overlap);
 		if (!HAS_MSO(i915)) {
 			drm_err(&i915->drm, "No source MSO support, disabling\n");
 			mso = 0;
@@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
 	}
 
 	intel_dp->mso_link_count = mso;
-	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
+	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
 }
 
 static bool
-- 
2.30.2

Re: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from
> DisplayID data
> 
> Now that we have MSO pixel overlap in display info, use it.
> 

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df402f63b741..baf21f9aa40e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct
> intel_connector *connector,  static void intel_edp_mso_init(struct intel_dp
> *intel_dp)  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +	struct drm_display_info *info = &connector->base.display_info;
>  	u8 mso;
> 
>  	if (intel_dp->edp_dpcd[0] < DP_EDP_14) @@ -2438,8 +2440,9 @@ static
> void intel_edp_mso_init(struct intel_dp *intel_dp)
>  	}
> 
>  	if (mso) {
> -		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
> -			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
> +		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel
> overlap %u\n",
> +			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
> +			    info->mso_pixel_overlap);
>  		if (!HAS_MSO(i915)) {
>  			drm_err(&i915->drm, "No source MSO support,
> disabling\n");
>  			mso = 0;
> @@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
>  	}
> 
>  	intel_dp->mso_link_count = mso;
> -	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
> +	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
>  }
> 
>  static bool
> --
> 2.30.2

RE: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from DisplayID data

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
> Sent: Tuesday, August 31, 2021 7:48 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from
> DisplayID data
> 
> Now that we have MSO pixel overlap in display info, use it.
> 

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df402f63b741..baf21f9aa40e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct
> intel_connector *connector,  static void intel_edp_mso_init(struct intel_dp
> *intel_dp)  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +	struct drm_display_info *info = &connector->base.display_info;
>  	u8 mso;
> 
>  	if (intel_dp->edp_dpcd[0] < DP_EDP_14) @@ -2438,8 +2440,9 @@ static
> void intel_edp_mso_init(struct intel_dp *intel_dp)
>  	}
> 
>  	if (mso) {
> -		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
> -			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
> +		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel
> overlap %u\n",
> +			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
> +			    info->mso_pixel_overlap);
>  		if (!HAS_MSO(i915)) {
>  			drm_err(&i915->drm, "No source MSO support,
> disabling\n");
>  			mso = 0;
> @@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
>  	}
> 
>  	intel_dp->mso_link_count = mso;
> -	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
> +	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
>  }
> 
>  static bool
> --
> 2.30.2

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)

[Patchwork]

== Series Details ==

Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)
URL   : https://patchwork.freedesktop.org/series/94161/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16:    unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16:    unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:117:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:123:51: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2p

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4640 bytes --]

== Series Details ==

Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)
URL   : https://patchwork.freedesktop.org/series/94161/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10540 -> Patchwork_20930
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/index.html

Known issues
------------

  Here are the changes found in Patchwork_20930 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-rkl-guc:         NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bsw-nick:        NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-kefka:       [PASS][3] -> [INCOMPLETE][4] ([i915#2940])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-bsw-kefka/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_lrc:
    - fi-rkl-guc:         NOTRUN -> [DMESG-WARN][5] ([i915#3958])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@runner@aborted:
    - fi-bsw-kefka:       NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#3428])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-bsw-kefka/igt@runner@aborted.html
    - fi-icl-y:           NOTRUN -> [FAIL][7] ([i915#3690])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-icl-y/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][8] ([i915#2940]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@workarounds:
    - fi-rkl-guc:         [DMESG-FAIL][10] ([i915#3928]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/fi-rkl-guc/igt@i915_selftest@live@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958


Participating hosts (43 -> 35)
------------------------------

  Missing    (8): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-skl-guc fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10540 -> Patchwork_20930

  CI-20190529: 20190529
  CI_DRM_10540: 8eff208fe95db1015e8fe0e4026065e6f0fa7d30 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20930: db849e26e74799e360e55ec39bc240e4f1b2d95c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

db849e26e747 drm/i915/edp: use MSO pixel overlap from DisplayID data
fd20bedfadd9 drm/i915/edp: postpone MSO init until after EDID read
9570941e69a9 drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
c30e221ed86a drm/edid: abstract OUI conversion to 24-bit int
f4d0b48dd388 drm/displayid: add DisplayID v2.0 data blocks and primary use cases
c1b9800976a8 drm/displayid: re-align data block macros

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/index.html

[-- Attachment #2: Type: text/html, Size: 5531 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30289 bytes --]

== Series Details ==

Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it (rev2)
URL   : https://patchwork.freedesktop.org/series/94161/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10540_full -> Patchwork_20930_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20930_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs:
    - {shard-rkl}:        [SKIP][1] ([i915#1845]) -> [SKIP][2] +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - {shard-rkl}:        NOTRUN -> [SKIP][3] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  
Known issues
------------

  Here are the changes found in Patchwork_20930_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-snb5/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@smoketest:
    - shard-snb:          NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-snb5/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb5/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-tglb:         NOTRUN -> [SKIP][10] ([fdo#109313])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb7/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][11] ([i915#180])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl6/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-iclb:         [PASS][12] -> [FAIL][13] ([i915#307])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][14] ([i915#2658])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-iclb:         NOTRUN -> [SKIP][16] ([fdo#109289])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][17] ([i915#2856])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@gen9_exec_parse@bb-start-far.html
    - shard-tglb:         NOTRUN -> [SKIP][18] ([i915#2856])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb7/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_rpm@gem-mmap-type@fixed:
    - shard-kbl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3976])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@i915_pm_rpm@gem-mmap-type@fixed.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][20] ([i915#3921])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-snb6/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-iclb:         [PASS][22] -> [DMESG-WARN][23] ([i915#3621])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][24] ([fdo#110723])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +5 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#3689] / [i915#3886])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb7/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +14 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl10/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
    - shard-snb:          NOTRUN -> [SKIP][30] ([fdo#109271]) +391 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-snb7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-kbl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_color_chamelium@pipe-a-ctm-limited-range:
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +23 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
    - shard-snb:          NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +16 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][34] ([i915#1319])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#109278] / [fdo#109279])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-size-change:
    - shard-apl:          NOTRUN -> [FAIL][36] ([i915#3444])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-size-change.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109274] / [fdo#109278])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-skl:          [PASS][38] -> [FAIL][39] ([i915#2346]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][40] -> [FAIL][41] ([i915#79])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-wf_vblank:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#109274]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_flip@2x-flip-vs-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [PASS][43] -> [FAIL][44] ([i915#79]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][45] -> [DMESG-WARN][46] ([i915#180]) +4 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [PASS][47] -> [FAIL][48] ([i915#2122])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][49] ([fdo#109280]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271]) +3 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
    - shard-tglb:         NOTRUN -> [SKIP][51] ([fdo#111825]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-apl:          NOTRUN -> [DMESG-WARN][54] ([i915#180])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265]) +5 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [PASS][57] -> [FAIL][58] ([fdo#108145] / [i915#265])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
    - shard-kbl:          NOTRUN -> [SKIP][59] ([fdo#109271]) +71 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +6 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
    - shard-kbl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-skl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][63] -> [SKIP][64] ([fdo#109441]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][65] ([IGT#2])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl2/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][66] -> [DMESG-WARN][67] ([i915#180] / [i915#295])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-wait-forked:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([fdo#109278]) +5 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_vblank@pipe-d-wait-forked.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271]) +298 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl6/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl2/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([i915#2437])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2437])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@kms_writeback@writeback-fb-id.html

  * igt@nouveau_crc@pipe-c-source-outp-complete:
    - shard-iclb:         NOTRUN -> [SKIP][73] ([i915#2530])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@nouveau_crc@pipe-c-source-outp-complete.html

  * igt@perf_pmu@module-unload:
    - shard-skl:          [PASS][74] -> [DMESG-WARN][75] ([i915#1982] / [i915#262])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl2/igt@perf_pmu@module-unload.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl2/igt@perf_pmu@module-unload.html

  * igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109291])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html

  * igt@prime_vgem@fence-write-hang:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([fdo#109295])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@prime_vgem@fence-write-hang.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994]) +3 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl6/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@recycle-many:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([i915#2994]) +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@sema-50:
    - shard-kbl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl1/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-close-race:
    - shard-iclb:         [INCOMPLETE][81] ([i915#1895]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb8/igt@gem_ctx_exec@basic-close-race.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb4/igt@gem_ctx_exec@basic-close-race.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-tglb:         [TIMEOUT][83] ([i915#3063]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-tglb3/igt@gem_eio@in-flight-contexts-10ms.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [TIMEOUT][85] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-tglb2/igt@gem_eio@unwedge-stress.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb5/igt@gem_eio@unwedge-stress.html
    - {shard-rkl}:        [TIMEOUT][87] ([i915#3063]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-6/igt@gem_eio@unwedge-stress.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][89] ([i915#2846]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl7/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-tglb:         [FAIL][91] ([i915#2842]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - {shard-rkl}:        [INCOMPLETE][93] ([i915#3189] / [i915#3810]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_pm_backlight@bad-brightness:
    - {shard-rkl}:        [SKIP][95] ([i915#3012]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@i915_pm_backlight@bad-brightness.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@i915_pm_backlight@bad-brightness.html

  * igt@i915_pm_dc@dc5-psr:
    - {shard-rkl}:        [SKIP][97] ([i915#658]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@i915_pm_dc@dc5-psr.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][99] ([i915#118] / [i915#95]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_big_fb@linear-8bpp-rotate-0:
    - {shard-rkl}:        [SKIP][101] ([i915#3638]) -> [PASS][102] +3 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-0.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_big_fb@linear-8bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][103] ([i915#3721]) -> [PASS][104] +3 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-270:
    - {shard-rkl}:        [SKIP][105] ([fdo#111614]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html

  * igt@kms_color@pipe-c-ctm-0-5:
    - shard-skl:          [DMESG-WARN][107] ([i915#1982]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl6/igt@kms_color@pipe-c-ctm-0-5.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl1/igt@kms_color@pipe-c-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
    - {shard-rkl}:        [SKIP][109] ([fdo#112022]) -> [PASS][110] +8 similar issues
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html

  * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
    - {shard-rkl}:        [SKIP][111] ([fdo#111825]) -> [PASS][112] +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled:
    - {shard-rkl}:        [SKIP][113] ([fdo#111314]) -> [PASS][114] +6 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [FAIL][115] ([i915#79]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][117] ([i915#180]) -> [PASS][118] +7 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][121] ([i915#1188]) -> [PASS][122] +2 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - {shard-rkl}:        [SKIP][123] ([i915#1849]) -> [PASS][124] +29 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - {shard-rkl}:        [SKIP][125] ([i915#3558]) -> [PASS][126] +1 similar issue
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][127] ([fdo#108145] / [i915#265]) -> [PASS][128] +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_plane_cursor@pipe-a-overlay-size-64:
    - {shard-rkl}:        [SKIP][129] ([i915#1845]) -> [PASS][130] +22 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_plane_cursor@pipe-a-overlay-size-64.html

  * igt@kms_psr@primary_page_flip:
    - {shard-rkl}:        [SKIP][131] ([i915#1072]) -> [PASS][132] +2 similar issues
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-rkl-5/igt@kms_psr@primary_page_flip.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-rkl-6/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][133] ([fdo#109441]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][135] ([i915#155] / [i915#2828]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [FAIL][137] ([i915#2842]) -> [SKIP][138] ([fdo#109271])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][139] ([i915#2684]) -> [WARN][140] ([i915#1804] / [i915#2684])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10540/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/shard-i

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20930/index.html

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Re: [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Jani Nikula]

On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
> check and an OUI helper patch added.

Maarten, Maxime, Thomas - may I have an ack for merging this via
drm-intel? I think at this time we can get the merge to drm-next and
backmerge to drm-misc fairly quickly, and a topic branch would be
overkill.

Alternative, I think it's also fine to merge all of this via drm-misc if
you prefer.

BR,
Jani.


>
> Jani Nikula (6):
>   drm/displayid: re-align data block macros
>   drm/displayid: add DisplayID v2.0 data blocks and primary use cases
>   drm/edid: abstract OUI conversion to 24-bit int
>   drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
>   drm/i915/edp: postpone MSO init until after EDID read
>   drm/i915/edp: use MSO pixel overlap from DisplayID data
>
>  drivers/gpu/drm/drm_edid.c              |  89 ++++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_dp.c |  14 ++--
>  include/drm/drm_connector.h             |  12 +++
>  include/drm/drm_displayid.h             | 101 +++++++++++++++++-------
>  4 files changed, 172 insertions(+), 44 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Jani Nikula]

On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
> check and an OUI helper patch added.

Maarten, Maxime, Thomas - may I have an ack for merging this via
drm-intel? I think at this time we can get the merge to drm-next and
backmerge to drm-misc fairly quickly, and a topic branch would be
overkill.

Alternative, I think it's also fine to merge all of this via drm-misc if
you prefer.

BR,
Jani.


>
> Jani Nikula (6):
>   drm/displayid: re-align data block macros
>   drm/displayid: add DisplayID v2.0 data blocks and primary use cases
>   drm/edid: abstract OUI conversion to 24-bit int
>   drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
>   drm/i915/edp: postpone MSO init until after EDID read
>   drm/i915/edp: use MSO pixel overlap from DisplayID data
>
>  drivers/gpu/drm/drm_edid.c              |  89 ++++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_dp.c |  14 ++--
>  include/drm/drm_connector.h             |  12 +++
>  include/drm/drm_displayid.h             | 101 +++++++++++++++++-------
>  4 files changed, 172 insertions(+), 44 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Maxime Ripard]

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Hi,

On Mon, Sep 13, 2021 at 07:45:03PM +0300, Jani Nikula wrote:
> On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> > v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
> > check and an OUI helper patch added.
> 
> Maarten, Maxime, Thomas - may I have an ack for merging this via
> drm-intel? I think at this time we can get the merge to drm-next and
> backmerge to drm-misc fairly quickly, and a topic branch would be
> overkill.

Yep, that works for me

Acked-by: Maxime Ripard <maxime@cerno.tech>

Maxime

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Re: [Intel-gfx] [PATCH v2 0/6] drm/displayid: VESA vendor block and drm/i915 MSO use of it

[Maxime Ripard]

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Hi,

On Mon, Sep 13, 2021 at 07:45:03PM +0300, Jani Nikula wrote:
> On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> > v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
> > check and an OUI helper patch added.
> 
> Maarten, Maxime, Thomas - may I have an ack for merging this via
> drm-intel? I think at this time we can get the merge to drm-next and
> backmerge to drm-misc fairly quickly, and a topic branch would be
> overkill.

Yep, that works for me

Acked-by: Maxime Ripard <maxime@cerno.tech>

Maxime

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