* [igt-dev] [i-g-t] i915_drm.h sync
@ 2021-09-02 5:40 Tejas Upadhyay
2021-09-02 6:20 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Tejas Upadhyay @ 2021-09-02 5:40 UTC (permalink / raw)
To: igt-dev
Sync to get I915_MMAP_OFFSET_FIXED define value.
Taken from kernel commit:
commit 7961c5b60f23 ("drm/i915: Add TTM offset argument to mmap.")
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
include/drm-uapi/i915_drm.h | 450 +++++++++++++++++++++++++++++-------
lib/i915/i915_drm_local.h | 2 -
2 files changed, 369 insertions(+), 83 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index a1c0030c..b9632bb2 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -849,45 +849,94 @@ struct drm_i915_gem_mmap_gtt {
__u64 offset;
};
+/**
+ * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
+ *
+ * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
+ * and is used to retrieve the fake offset to mmap an object specified by &handle.
+ *
+ * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
+ * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
+ * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
+ */
struct drm_i915_gem_mmap_offset {
- /** Handle for the object being mapped. */
+ /** @handle: Handle for the object being mapped. */
__u32 handle;
+ /** @pad: Must be zero */
__u32 pad;
/**
- * Fake offset to use for subsequent mmap call
+ * @offset: The fake offset to use for subsequent mmap call
*
* This is a fixed-size type for 32/64 compatibility.
*/
__u64 offset;
/**
- * Flags for extended behaviour.
+ * @flags: Flags for extended behaviour.
*
- * It is mandatory that one of the MMAP_OFFSET types
- * (GTT, WC, WB, UC, etc) should be included.
+ * It is mandatory that one of the `MMAP_OFFSET` types
+ * should be included:
+ *
+ * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
+ * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
+ * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
+ * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
+ *
+ * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
+ * type. On devices without local memory, this caching mode is invalid.
+ *
+ * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
+ * be used, depending on the object placement on creation. WB will be used
+ * when the object can only exist in system memory, WC otherwise.
*/
__u64 flags;
-#define I915_MMAP_OFFSET_GTT 0
-#define I915_MMAP_OFFSET_WC 1
-#define I915_MMAP_OFFSET_WB 2
-#define I915_MMAP_OFFSET_UC 3
- /*
- * Zero-terminated chain of extensions.
+#define I915_MMAP_OFFSET_GTT 0
+#define I915_MMAP_OFFSET_WC 1
+#define I915_MMAP_OFFSET_WB 2
+#define I915_MMAP_OFFSET_UC 3
+#define I915_MMAP_OFFSET_FIXED 4
+
+ /**
+ * @extensions: Zero-terminated chain of extensions.
*
* No current extensions defined; mbz.
*/
__u64 extensions;
};
+/**
+ * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
+ * preparation for accessing the pages via some CPU domain.
+ *
+ * Specifying a new write or read domain will flush the object out of the
+ * previous domain(if required), before then updating the objects domain
+ * tracking with the new domain.
+ *
+ * Note this might involve waiting for the object first if it is still active on
+ * the GPU.
+ *
+ * Supported values for @read_domains and @write_domain:
+ *
+ * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
+ * - I915_GEM_DOMAIN_CPU: CPU cache domain
+ * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
+ *
+ * All other domains are rejected.
+ */
struct drm_i915_gem_set_domain {
- /** Handle for the object */
+ /** @handle: Handle for the object. */
__u32 handle;
- /** New read domains */
+ /** @read_domains: New read domains. */
__u32 read_domains;
- /** New write domain */
+ /**
+ * @write_domain: New write domain.
+ *
+ * Note that having something in the write domain implies it's in the
+ * read domain, and only that read domain.
+ */
__u32 write_domain;
};
@@ -1348,12 +1397,11 @@ struct drm_i915_gem_busy {
* reading from the object simultaneously.
*
* The value of each engine class is the same as specified in the
- * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+ * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
- * reported as active itself. Some hardware may have parallel
- * execution engines, e.g. multiple media engines, which are
- * mapped to the same class identifier and so are not separately
- * reported for busyness.
+ * Some hardware may have parallel execution engines, e.g. multiple
+ * media engines, which are mapped to the same class identifier and so
+ * are not separately reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@@ -1364,43 +1412,79 @@ struct drm_i915_gem_busy {
};
/**
- * I915_CACHING_NONE
- *
- * GPU access is not coherent with cpu caches. Default for machines without an
- * LLC.
- */
-#define I915_CACHING_NONE 0
-/**
- * I915_CACHING_CACHED
- *
- * GPU access is coherent with cpu caches and furthermore the data is cached in
- * last-level caches shared between cpu cores and the gpu GT. Default on
- * machines with HAS_LLC.
+ * struct drm_i915_gem_caching - Set or get the caching for given object
+ * handle.
+ *
+ * Allow userspace to control the GTT caching bits for a given object when the
+ * object is later mapped through the ppGTT(or GGTT on older platforms lacking
+ * ppGTT support, or if the object is used for scanout). Note that this might
+ * require unbinding the object from the GTT first, if its current caching value
+ * doesn't match.
+ *
+ * Note that this all changes on discrete platforms, starting from DG1, the
+ * set/get caching is no longer supported, and is now rejected. Instead the CPU
+ * caching attributes(WB vs WC) will become an immutable creation time property
+ * for the object, along with the GTT caching level. For now we don't expose any
+ * new uAPI for this, instead on DG1 this is all implicit, although this largely
+ * shouldn't matter since DG1 is coherent by default(without any way of
+ * controlling it).
+ *
+ * Implicit caching rules, starting from DG1:
+ *
+ * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
+ * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
+ * mapped as write-combined only.
+ *
+ * - Everything else is always allocated and mapped as write-back, with the
+ * guarantee that everything is also coherent with the GPU.
+ *
+ * Note that this is likely to change in the future again, where we might need
+ * more flexibility on future devices, so making this all explicit as part of a
+ * new &drm_i915_gem_create_ext extension is probable.
+ *
+ * Side note: Part of the reason for this is that changing the at-allocation-time CPU
+ * caching attributes for the pages might be required(and is expensive) if we
+ * need to then CPU map the pages later with different caching attributes. This
+ * inconsistent caching behaviour, while supported on x86, is not universally
+ * supported on other architectures. So for simplicity we opt for setting
+ * everything at creation time, whilst also making it immutable, on discrete
+ * platforms.
*/
-#define I915_CACHING_CACHED 1
-/**
- * I915_CACHING_DISPLAY
- *
- * Special GPU caching mode which is coherent with the scanout engines.
- * Transparently falls back to I915_CACHING_NONE on platforms where no special
- * cache mode (like write-through or gfdt flushing) is available. The kernel
- * automatically sets this mode when using a buffer as a scanout target.
- * Userspace can manually set this mode to avoid a costly stall and clflush in
- * the hotpath of drawing the first frame.
- */
-#define I915_CACHING_DISPLAY 2
-
struct drm_i915_gem_caching {
/**
- * Handle of the buffer to set/get the caching level of. */
+ * @handle: Handle of the buffer to set/get the caching level.
+ */
__u32 handle;
/**
- * Cacheing level to apply or return value
+ * @caching: The GTT caching level to apply or possible return value.
+ *
+ * The supported @caching values:
+ *
+ * I915_CACHING_NONE:
+ *
+ * GPU access is not coherent with CPU caches. Default for machines
+ * without an LLC. This means manual flushing might be needed, if we
+ * want GPU access to be coherent.
+ *
+ * I915_CACHING_CACHED:
+ *
+ * GPU access is coherent with CPU caches and furthermore the data is
+ * cached in last-level caches shared between CPU cores and the GPU GT.
*
- * bits0-15 are for generic caching control (i.e. the above defined
- * values). bits16-31 are reserved for platform-specific variations
- * (e.g. l3$ caching on gen7). */
+ * I915_CACHING_DISPLAY:
+ *
+ * Special GPU caching mode which is coherent with the scanout engines.
+ * Transparently falls back to I915_CACHING_NONE on platforms where no
+ * special cache mode (like write-through or gfdt flushing) is
+ * available. The kernel automatically sets this mode when using a
+ * buffer as a scanout target. Userspace can manually set this mode to
+ * avoid a costly stall and clflush in the hotpath of drawing the first
+ * frame.
+ */
+#define I915_CACHING_NONE 0
+#define I915_CACHING_CACHED 1
+#define I915_CACHING_DISPLAY 2
__u32 caching;
};
@@ -1639,6 +1723,10 @@ struct drm_i915_gem_context_param {
__u32 size;
__u64 param;
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
+/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
+ * someone somewhere has attempted to use it, never re-use this context
+ * param number.
+ */
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
@@ -1723,24 +1811,8 @@ struct drm_i915_gem_context_param {
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
-/*
- * I915_CONTEXT_PARAM_RINGSIZE:
- *
- * Sets the size of the CS ringbuffer to use for logical ring contexts. This
- * applies a limit of how many batches can be queued to HW before the caller
- * is blocked due to lack of space for more commands.
- *
- * Only reliably possible to be set prior to first use, i.e. during
- * construction. At any later point, the current execution must be flushed as
- * the ring can only be changed while the context is idle. Note, the ringsize
- * can be specified as a constructor property, see
- * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
- *
- * Only applies to the current set of engine and lost when those engines
- * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
- *
- * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
- * Default is 16 KiB.
+/* This API has been removed. On the off chance someone somewhere has
+ * attempted to use it, never re-use this context param number.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
/* Must be kept compact -- no holes and well documented */
@@ -1807,6 +1879,69 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/**
+ * DOC: Virtual Engine uAPI
+ *
+ * Virtual engine is a concept where userspace is able to configure a set of
+ * physical engines, submit a batch buffer, and let the driver execute it on any
+ * engine from the set as it sees fit.
+ *
+ * This is primarily useful on parts which have multiple instances of a same
+ * class engine, like for example GT3+ Skylake parts with their two VCS engines.
+ *
+ * For instance userspace can enumerate all engines of a certain class using the
+ * previously described `Engine Discovery uAPI`_. After that userspace can
+ * create a GEM context with a placeholder slot for the virtual engine (using
+ * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
+ * and instance respectively) and finally using the
+ * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
+ * the same reserved slot.
+ *
+ * Example of creating a virtual engine and submitting a batch buffer to it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
+ * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
+ * .engine_index = 0, // Place this virtual engine into engine map slot 0
+ * .num_siblings = 2,
+ * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
+ * { I915_ENGINE_CLASS_VIDEO, 1 }, },
+ * };
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ * .engines = { { I915_ENGINE_CLASS_INVALID,
+ * I915_ENGINE_CLASS_INVALID_NONE } },
+ * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // Now we have created a GEM context with its engine map containing a
+ * // single virtual engine. Submissions to this slot can go either to
+ * // vcs0 or vcs1, depending on the load balancing algorithm used inside
+ * // the driver. The load balancing is dynamic from one batch buffer to
+ * // another and transparent to userspace.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
/*
* i915_context_engines_load_balance:
*
@@ -1883,6 +2018,61 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * DOC: Context Engine Map uAPI
+ *
+ * Context engine map is a new way of addressing engines when submitting batch-
+ * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
+ * inside the flags field of `struct drm_i915_gem_execbuffer2`.
+ *
+ * To use it created GEM contexts need to be configured with a list of engines
+ * the user is intending to submit to. This is accomplished using the
+ * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
+ * i915_context_param_engines`.
+ *
+ * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
+ * configured map.
+ *
+ * Example of creating such context and submitting against it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
+ * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
+ * { I915_ENGINE_CLASS_COPY, 0 } }
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // We have now created a GEM context with two engines in the map:
+ * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
+ * // will not be accessible from this context.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -1901,20 +2091,10 @@ struct drm_i915_gem_context_create_ext_setparam {
struct drm_i915_gem_context_param param;
};
-struct drm_i915_gem_context_create_ext_clone {
+/* This API has been removed. On the off chance someone somewhere has
+ * attempted to use it, never re-use this extension number.
+ */
#define I915_CONTEXT_CREATE_EXT_CLONE 1
- struct i915_user_extension base;
- __u32 clone_id;
- __u32 flags;
-#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
-#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
-#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
-#define I915_CONTEXT_CLONE_SSEU (1u << 3)
-#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
-#define I915_CONTEXT_CLONE_VM (1u << 5)
-#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
- __u64 rsvd;
-};
struct drm_i915_gem_context_destroy {
__u32 ctx_id;
@@ -1986,14 +2166,52 @@ struct drm_i915_reset_stats {
__u32 pad;
};
+/**
+ * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
+ *
+ * Userptr objects have several restrictions on what ioctls can be used with the
+ * object handle.
+ */
struct drm_i915_gem_userptr {
+ /**
+ * @user_ptr: The pointer to the allocated memory.
+ *
+ * Needs to be aligned to PAGE_SIZE.
+ */
__u64 user_ptr;
+
+ /**
+ * @user_size:
+ *
+ * The size in bytes for the allocated memory. This will also become the
+ * object size.
+ *
+ * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
+ * or larger.
+ */
__u64 user_size;
+
+ /**
+ * @flags:
+ *
+ * Supported flags:
+ *
+ * I915_USERPTR_READ_ONLY:
+ *
+ * Mark the object as readonly, this also means GPU access can only be
+ * readonly. This is only supported on HW which supports readonly access
+ * through the GTT. If the HW can't support readonly access, an error is
+ * returned.
+ *
+ * I915_USERPTR_UNSYNCHRONIZED:
+ *
+ * NOT USED. Setting this flag will result in an error.
+ */
__u32 flags;
#define I915_USERPTR_READ_ONLY 0x1
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
/**
- * Returned handle for the object.
+ * @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
@@ -2376,6 +2594,76 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * DOC: Engine Discovery uAPI
+ *
+ * Engine discovery uAPI is a way of enumerating physical engines present in a
+ * GPU associated with an open i915 DRM file descriptor. This supersedes the old
+ * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
+ * `I915_PARAM_HAS_BLT`.
+ *
+ * The need for this interface came starting with Icelake and newer GPUs, which
+ * started to establish a pattern of having multiple engines of a same class,
+ * where not all instances were always completely functionally equivalent.
+ *
+ * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
+ * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
+ *
+ * Example for getting the list of engines:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_engine_info *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_ENGINE_INFO;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of engines. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * //
+ * // Alternatively a large buffer can be allocated straight away enabling
+ * // querying in one pass, in which case item.length should contain the
+ * // length of the provided buffer.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with info on all engines.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each engine in the array
+ * for (i = 0; i < info->num_engines; i++) {
+ * struct drm_i915_engine_info einfo = info->engines[i];
+ * u16 class = einfo.engine.class;
+ * u16 instance = einfo.engine.instance;
+ * ....
+ * }
+ *
+ * free(info);
+ *
+ * Each of the enumerated engines, apart from being defined by its class and
+ * instance (see `struct i915_engine_class_instance`), also can have flags and
+ * capabilities defined as documented in i915_drm.h.
+ *
+ * For instance video engines which support HEVC encoding will have the
+ * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
+ *
+ * Engine discovery only fully comes to its own when combined with the new way
+ * of addressing engines when submitting batch buffers using contexts with
+ * engine maps configured.
+ */
+
/**
* struct drm_i915_engine_info
*
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 0e3cef81..dd646aed 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -20,8 +20,6 @@ extern "C" {
* clean these up when kernel uapi headers are sync'd.
*/
-#define I915_MMAP_OFFSET_FIXED 4
-
#if defined(__cplusplus)
}
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915_drm.h sync
2021-09-02 5:40 [igt-dev] [i-g-t] i915_drm.h sync Tejas Upadhyay
@ 2021-09-02 6:20 ` Patchwork
2021-09-02 7:23 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2021-09-02 8:51 ` [igt-dev] [i-g-t] " Petri Latvala
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2021-09-02 6:20 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3338 bytes --]
== Series Details ==
Series: i915_drm.h sync
URL : https://patchwork.freedesktop.org/series/94271/
State : success
== Summary ==
CI Bug Log - changes from IGT_6196 -> IGTPW_6186
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/index.html
Known issues
------------
Here are the changes found in IGTPW_6186 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([i915#2940])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][3] -> [INCOMPLETE][4] ([i915#3921])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#3928])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
* igt@runner@aborted:
- fi-bsw-nick: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / [i915#3428])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-bsw-nick/igt@runner@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][8] ([i915#3928])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-rkl-guc/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][9] ([i915#1888]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
Participating hosts (39 -> 34)
------------------------------
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6196 -> IGTPW_6186
CI-20190529: 20190529
CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6186: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/index.html
IGT_6196: 790964585bc0d7615b439d049fda73d5e26ee633 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/index.html
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915_drm.h sync
2021-09-02 5:40 [igt-dev] [i-g-t] i915_drm.h sync Tejas Upadhyay
2021-09-02 6:20 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-09-02 7:23 ` Patchwork
2021-09-02 8:51 ` [igt-dev] [i-g-t] " Petri Latvala
2 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2021-09-02 7:23 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: igt-dev
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== Series Details ==
Series: i915_drm.h sync
URL : https://patchwork.freedesktop.org/series/94271/
State : success
== Summary ==
CI Bug Log - changes from IGT_6196_full -> IGTPW_6186_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/index.html
Known issues
------------
Here are the changes found in IGTPW_6186_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl7/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb5/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#280])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb7/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: NOTRUN -> [TIMEOUT][5] ([i915#3063])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#2481] / [i915#3070])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb2/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][8] ([i915#2846])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl2/igt@gem_exec_fair@basic-deadline.html
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk8/igt@gem_exec_fair@basic-deadline.html
- shard-apl: NOTRUN -> [FAIL][10] ([i915#2846])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@gem_huc_copy@huc-copy.html
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#111656])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@gem_mmap_gtt@coherency.html
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109292])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb3/igt@gem_mmap_gtt@coherency.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][21] ([i915#2658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb7/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3323])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][23] ([i915#3002])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl1/igt@gem_userptr_blits@input-checking.html
- shard-snb: NOTRUN -> [DMESG-WARN][24] ([i915#3002])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#3297])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb7/igt@gem_userptr_blits@unsync-unmap-cycles.html
- shard-iclb: NOTRUN -> [SKIP][26] ([i915#3297])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb4/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][27] ([i915#2724])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb7/igt@gem_userptr_blits@vma-merge.html
- shard-kbl: NOTRUN -> [FAIL][28] ([i915#3318])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl1/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271]) +417 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb7/igt@gen9_exec_parse@batch-invalid-length.html
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#2856]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb8/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-secure:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#2856]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb1/igt@gen9_exec_parse@bb-secure.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#3288])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb7/igt@i915_pm_dc@dc9-dpms.html
- shard-iclb: NOTRUN -> [FAIL][33] ([i915#3343])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#1902])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb2/igt@i915_pm_lpsp@screens-disabled.html
- shard-iclb: NOTRUN -> [SKIP][35] ([i915#1902])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb7/igt@i915_pm_lpsp@screens-disabled.html
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: [PASS][36] -> [DMESG-WARN][37] ([i915#180])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-apl6/igt@i915_suspend@fence-restore-untiled.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl3/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [PASS][39] -> [DMESG-WARN][40] ([i915#118] / [i915#95]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk9/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111614])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb3/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: [PASS][42] -> [FAIL][43] ([i915#3722])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-tglb3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111615]) +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3689] / [i915#3886]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +11 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278] / [i915#3886]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +6 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3689]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-after-suspend:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb5/igt@kms_chamelium@hdmi-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +7 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb3/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +12 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl4/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +20 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +23 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb7/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-glk: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +7 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk7/igt@kms_color_chamelium@pipe-d-degamma.html
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb7/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][58] ([i915#1319])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl4/igt@kms_content_protection@atomic.html
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109300] / [fdo#111066])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@kms_content_protection@atomic.html
- shard-apl: NOTRUN -> [TIMEOUT][60] ([i915#1319])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl6/igt@kms_content_protection@atomic.html
- shard-tglb: NOTRUN -> [SKIP][61] ([fdo#111828])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109278] / [fdo#109279])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +4 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3359]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271]) +111 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-random:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#3319])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-32x32-random.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109279] / [i915#3359]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109274] / [fdo#109278]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#3788])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb3/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109274]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][72] -> [FAIL][73] ([i915#79])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [PASS][74] -> [FAIL][75] ([i915#79])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-glk: [PASS][76] -> [FAIL][77] ([i915#2546])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109280]) +12 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271]) +227 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +77 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk1/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][81] ([fdo#111825]) +17 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl2/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk5/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-kbl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][85] ([fdo#108145] / [i915#265]) +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][86] ([i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_cursor@pipe-d-viewport-size-64:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109278]) +17 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb8/igt@kms_plane_cursor@pipe-d-viewport-size-64.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#3536]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#3536]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][90] ([fdo#112054]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#2920])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
- shard-iclb: NOTRUN -> [SKIP][93] ([i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-glk: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#658]) +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][96] -> [SKIP][97] ([fdo#109642] / [fdo#111068] / [i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb2/igt@kms_psr2_su@page_flip.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109441])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][99] -> [SKIP][100] ([fdo#109441])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb3/igt@kms_psr@psr2_primary_render.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][101] ([i915#132] / [i915#3467]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb2/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][102] ([IGT#2])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2437])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl3/igt@kms_writeback@writeback-check-output.html
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#2437])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2437])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_api@i915_nv_double_export:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109291]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb6/igt@prime_nv_api@i915_nv_double_export.html
* igt@prime_nv_test@nv_write_i915_cpu_mmap_read:
- shard-tglb: NOTRUN -> [SKIP][107] ([fdo#109291]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb2/igt@prime_nv_test@nv_write_i915_cpu_mmap_read.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl8/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@sema-50:
- shard-glk: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk9/igt@sysfs_clients@sema-50.html
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#2994])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb8/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][111] ([i915#2994]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb7/igt@sysfs_clients@split-10.html
- shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl6/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][113] ([i915#2842]) -> [PASS][114] +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][115] ([i915#2842]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [FAIL][117] ([i915#2842]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-tglb3/igt@gem_exec_fair@basic-pace@vecs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [FAIL][119] ([i915#307]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-glk: [FAIL][121] ([i915#1888] / [i915#307]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk9/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk7/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [DMESG-WARN][123] ([i915#180]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-kbl6/igt@gem_workarounds@suspend-resume.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-kbl2/igt@gem_workarounds@suspend-resume.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][125] ([i915#3921]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-snb6/igt@i915_selftest@live@hangcheck.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-glk: [FAIL][127] ([i915#1888] / [i915#3653]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk8/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk8/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][129] ([i915#180]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@bo-too-big-interruptible@a-hdmi-a1:
- shard-glk: [DMESG-WARN][131] ([i915#118] / [i915#95]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-glk8/igt@kms_flip@bo-too-big-interruptible@a-hdmi-a1.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-glk9/igt@kms_flip@bo-too-big-interruptible@a-hdmi-a1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][133] ([fdo#109441]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-snb: [SKIP][135] ([fdo#109271]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-snb7/igt@kms_vblank@pipe-b-accuracy-idle.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-snb6/igt@kms_vblank@pipe-b-accuracy-idle.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][137] ([i915#658]) -> [SKIP][138] ([i915#588])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][139] ([i915#1804] / [i915#2684]) -> [WARN][140] ([i915#2684])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6196/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/shard-iclb1/igt@i915_pm_rc6_residen
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6186/index.html
[-- Attachment #2: Type: text/html, Size: 33819 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [igt-dev] [i-g-t] i915_drm.h sync
2021-09-02 5:40 [igt-dev] [i-g-t] i915_drm.h sync Tejas Upadhyay
2021-09-02 6:20 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2021-09-02 7:23 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2021-09-02 8:51 ` Petri Latvala
2 siblings, 0 replies; 4+ messages in thread
From: Petri Latvala @ 2021-09-02 8:51 UTC (permalink / raw)
To: Tejas Upadhyay; +Cc: igt-dev
On Thu, Sep 02, 2021 at 11:10:57AM +0530, Tejas Upadhyay wrote:
> Sync to get I915_MMAP_OFFSET_FIXED define value.
>
> Taken from kernel commit:
> commit 7961c5b60f23 ("drm/i915: Add TTM offset argument to mmap.")
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Acked-by: Petri Latvala <petri.latvala@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 450 +++++++++++++++++++++++++++++-------
> lib/i915/i915_drm_local.h | 2 -
> 2 files changed, 369 insertions(+), 83 deletions(-)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a1c0030c..b9632bb2 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -849,45 +849,94 @@ struct drm_i915_gem_mmap_gtt {
> __u64 offset;
> };
>
> +/**
> + * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
> + *
> + * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
> + * and is used to retrieve the fake offset to mmap an object specified by &handle.
> + *
> + * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
> + * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
> + * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
> + */
> struct drm_i915_gem_mmap_offset {
> - /** Handle for the object being mapped. */
> + /** @handle: Handle for the object being mapped. */
> __u32 handle;
> + /** @pad: Must be zero */
> __u32 pad;
> /**
> - * Fake offset to use for subsequent mmap call
> + * @offset: The fake offset to use for subsequent mmap call
> *
> * This is a fixed-size type for 32/64 compatibility.
> */
> __u64 offset;
>
> /**
> - * Flags for extended behaviour.
> + * @flags: Flags for extended behaviour.
> *
> - * It is mandatory that one of the MMAP_OFFSET types
> - * (GTT, WC, WB, UC, etc) should be included.
> + * It is mandatory that one of the `MMAP_OFFSET` types
> + * should be included:
> + *
> + * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
> + * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
> + * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
> + * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
> + *
> + * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
> + * type. On devices without local memory, this caching mode is invalid.
> + *
> + * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
> + * be used, depending on the object placement on creation. WB will be used
> + * when the object can only exist in system memory, WC otherwise.
> */
> __u64 flags;
> -#define I915_MMAP_OFFSET_GTT 0
> -#define I915_MMAP_OFFSET_WC 1
> -#define I915_MMAP_OFFSET_WB 2
> -#define I915_MMAP_OFFSET_UC 3
>
> - /*
> - * Zero-terminated chain of extensions.
> +#define I915_MMAP_OFFSET_GTT 0
> +#define I915_MMAP_OFFSET_WC 1
> +#define I915_MMAP_OFFSET_WB 2
> +#define I915_MMAP_OFFSET_UC 3
> +#define I915_MMAP_OFFSET_FIXED 4
> +
> + /**
> + * @extensions: Zero-terminated chain of extensions.
> *
> * No current extensions defined; mbz.
> */
> __u64 extensions;
> };
>
> +/**
> + * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
> + * preparation for accessing the pages via some CPU domain.
> + *
> + * Specifying a new write or read domain will flush the object out of the
> + * previous domain(if required), before then updating the objects domain
> + * tracking with the new domain.
> + *
> + * Note this might involve waiting for the object first if it is still active on
> + * the GPU.
> + *
> + * Supported values for @read_domains and @write_domain:
> + *
> + * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
> + * - I915_GEM_DOMAIN_CPU: CPU cache domain
> + * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
> + *
> + * All other domains are rejected.
> + */
> struct drm_i915_gem_set_domain {
> - /** Handle for the object */
> + /** @handle: Handle for the object. */
> __u32 handle;
>
> - /** New read domains */
> + /** @read_domains: New read domains. */
> __u32 read_domains;
>
> - /** New write domain */
> + /**
> + * @write_domain: New write domain.
> + *
> + * Note that having something in the write domain implies it's in the
> + * read domain, and only that read domain.
> + */
> __u32 write_domain;
> };
>
> @@ -1348,12 +1397,11 @@ struct drm_i915_gem_busy {
> * reading from the object simultaneously.
> *
> * The value of each engine class is the same as specified in the
> - * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
> + * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
> * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
> - * reported as active itself. Some hardware may have parallel
> - * execution engines, e.g. multiple media engines, which are
> - * mapped to the same class identifier and so are not separately
> - * reported for busyness.
> + * Some hardware may have parallel execution engines, e.g. multiple
> + * media engines, which are mapped to the same class identifier and so
> + * are not separately reported for busyness.
> *
> * Caveat emptor:
> * Only the boolean result of this query is reliable; that is whether
> @@ -1364,43 +1412,79 @@ struct drm_i915_gem_busy {
> };
>
> /**
> - * I915_CACHING_NONE
> - *
> - * GPU access is not coherent with cpu caches. Default for machines without an
> - * LLC.
> - */
> -#define I915_CACHING_NONE 0
> -/**
> - * I915_CACHING_CACHED
> - *
> - * GPU access is coherent with cpu caches and furthermore the data is cached in
> - * last-level caches shared between cpu cores and the gpu GT. Default on
> - * machines with HAS_LLC.
> + * struct drm_i915_gem_caching - Set or get the caching for given object
> + * handle.
> + *
> + * Allow userspace to control the GTT caching bits for a given object when the
> + * object is later mapped through the ppGTT(or GGTT on older platforms lacking
> + * ppGTT support, or if the object is used for scanout). Note that this might
> + * require unbinding the object from the GTT first, if its current caching value
> + * doesn't match.
> + *
> + * Note that this all changes on discrete platforms, starting from DG1, the
> + * set/get caching is no longer supported, and is now rejected. Instead the CPU
> + * caching attributes(WB vs WC) will become an immutable creation time property
> + * for the object, along with the GTT caching level. For now we don't expose any
> + * new uAPI for this, instead on DG1 this is all implicit, although this largely
> + * shouldn't matter since DG1 is coherent by default(without any way of
> + * controlling it).
> + *
> + * Implicit caching rules, starting from DG1:
> + *
> + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
> + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
> + * mapped as write-combined only.
> + *
> + * - Everything else is always allocated and mapped as write-back, with the
> + * guarantee that everything is also coherent with the GPU.
> + *
> + * Note that this is likely to change in the future again, where we might need
> + * more flexibility on future devices, so making this all explicit as part of a
> + * new &drm_i915_gem_create_ext extension is probable.
> + *
> + * Side note: Part of the reason for this is that changing the at-allocation-time CPU
> + * caching attributes for the pages might be required(and is expensive) if we
> + * need to then CPU map the pages later with different caching attributes. This
> + * inconsistent caching behaviour, while supported on x86, is not universally
> + * supported on other architectures. So for simplicity we opt for setting
> + * everything at creation time, whilst also making it immutable, on discrete
> + * platforms.
> */
> -#define I915_CACHING_CACHED 1
> -/**
> - * I915_CACHING_DISPLAY
> - *
> - * Special GPU caching mode which is coherent with the scanout engines.
> - * Transparently falls back to I915_CACHING_NONE on platforms where no special
> - * cache mode (like write-through or gfdt flushing) is available. The kernel
> - * automatically sets this mode when using a buffer as a scanout target.
> - * Userspace can manually set this mode to avoid a costly stall and clflush in
> - * the hotpath of drawing the first frame.
> - */
> -#define I915_CACHING_DISPLAY 2
> -
> struct drm_i915_gem_caching {
> /**
> - * Handle of the buffer to set/get the caching level of. */
> + * @handle: Handle of the buffer to set/get the caching level.
> + */
> __u32 handle;
>
> /**
> - * Cacheing level to apply or return value
> + * @caching: The GTT caching level to apply or possible return value.
> + *
> + * The supported @caching values:
> + *
> + * I915_CACHING_NONE:
> + *
> + * GPU access is not coherent with CPU caches. Default for machines
> + * without an LLC. This means manual flushing might be needed, if we
> + * want GPU access to be coherent.
> + *
> + * I915_CACHING_CACHED:
> + *
> + * GPU access is coherent with CPU caches and furthermore the data is
> + * cached in last-level caches shared between CPU cores and the GPU GT.
> *
> - * bits0-15 are for generic caching control (i.e. the above defined
> - * values). bits16-31 are reserved for platform-specific variations
> - * (e.g. l3$ caching on gen7). */
> + * I915_CACHING_DISPLAY:
> + *
> + * Special GPU caching mode which is coherent with the scanout engines.
> + * Transparently falls back to I915_CACHING_NONE on platforms where no
> + * special cache mode (like write-through or gfdt flushing) is
> + * available. The kernel automatically sets this mode when using a
> + * buffer as a scanout target. Userspace can manually set this mode to
> + * avoid a costly stall and clflush in the hotpath of drawing the first
> + * frame.
> + */
> +#define I915_CACHING_NONE 0
> +#define I915_CACHING_CACHED 1
> +#define I915_CACHING_DISPLAY 2
> __u32 caching;
> };
>
> @@ -1639,6 +1723,10 @@ struct drm_i915_gem_context_param {
> __u32 size;
> __u64 param;
> #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
> +/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
> + * someone somewhere has attempted to use it, never re-use this context
> + * param number.
> + */
> #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
> #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
> #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
> @@ -1723,24 +1811,8 @@ struct drm_i915_gem_context_param {
> */
> #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
>
> -/*
> - * I915_CONTEXT_PARAM_RINGSIZE:
> - *
> - * Sets the size of the CS ringbuffer to use for logical ring contexts. This
> - * applies a limit of how many batches can be queued to HW before the caller
> - * is blocked due to lack of space for more commands.
> - *
> - * Only reliably possible to be set prior to first use, i.e. during
> - * construction. At any later point, the current execution must be flushed as
> - * the ring can only be changed while the context is idle. Note, the ringsize
> - * can be specified as a constructor property, see
> - * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
> - *
> - * Only applies to the current set of engine and lost when those engines
> - * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
> - *
> - * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
> - * Default is 16 KiB.
> +/* This API has been removed. On the off chance someone somewhere has
> + * attempted to use it, never re-use this context param number.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> /* Must be kept compact -- no holes and well documented */
> @@ -1807,6 +1879,69 @@ struct drm_i915_gem_context_param_sseu {
> __u32 rsvd;
> };
>
> +/**
> + * DOC: Virtual Engine uAPI
> + *
> + * Virtual engine is a concept where userspace is able to configure a set of
> + * physical engines, submit a batch buffer, and let the driver execute it on any
> + * engine from the set as it sees fit.
> + *
> + * This is primarily useful on parts which have multiple instances of a same
> + * class engine, like for example GT3+ Skylake parts with their two VCS engines.
> + *
> + * For instance userspace can enumerate all engines of a certain class using the
> + * previously described `Engine Discovery uAPI`_. After that userspace can
> + * create a GEM context with a placeholder slot for the virtual engine (using
> + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
> + * and instance respectively) and finally using the
> + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
> + * the same reserved slot.
> + *
> + * Example of creating a virtual engine and submitting a batch buffer to it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
> + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
> + * .engine_index = 0, // Place this virtual engine into engine map slot 0
> + * .num_siblings = 2,
> + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
> + * { I915_ENGINE_CLASS_VIDEO, 1 }, },
> + * };
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
> + * .engines = { { I915_ENGINE_CLASS_INVALID,
> + * I915_ENGINE_CLASS_INVALID_NONE } },
> + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // Now we have created a GEM context with its engine map containing a
> + * // single virtual engine. Submissions to this slot can go either to
> + * // vcs0 or vcs1, depending on the load balancing algorithm used inside
> + * // the driver. The load balancing is dynamic from one batch buffer to
> + * // another and transparent to userspace.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> /*
> * i915_context_engines_load_balance:
> *
> @@ -1883,6 +2018,61 @@ struct i915_context_engines_bond {
> struct i915_engine_class_instance engines[N__]; \
> } __attribute__((packed)) name__
>
> +/**
> + * DOC: Context Engine Map uAPI
> + *
> + * Context engine map is a new way of addressing engines when submitting batch-
> + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
> + * inside the flags field of `struct drm_i915_gem_execbuffer2`.
> + *
> + * To use it created GEM contexts need to be configured with a list of engines
> + * the user is intending to submit to. This is accomplished using the
> + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
> + * i915_context_param_engines`.
> + *
> + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
> + * configured map.
> + *
> + * Example of creating such context and submitting against it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
> + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
> + * { I915_ENGINE_CLASS_COPY, 0 } }
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // We have now created a GEM context with two engines in the map:
> + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
> + * // will not be accessible from this context.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> struct i915_context_param_engines {
> __u64 extensions; /* linked chain of extension blocks, 0 terminates */
> #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
> @@ -1901,20 +2091,10 @@ struct drm_i915_gem_context_create_ext_setparam {
> struct drm_i915_gem_context_param param;
> };
>
> -struct drm_i915_gem_context_create_ext_clone {
> +/* This API has been removed. On the off chance someone somewhere has
> + * attempted to use it, never re-use this extension number.
> + */
> #define I915_CONTEXT_CREATE_EXT_CLONE 1
> - struct i915_user_extension base;
> - __u32 clone_id;
> - __u32 flags;
> -#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
> -#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
> -#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
> -#define I915_CONTEXT_CLONE_SSEU (1u << 3)
> -#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
> -#define I915_CONTEXT_CLONE_VM (1u << 5)
> -#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
> - __u64 rsvd;
> -};
>
> struct drm_i915_gem_context_destroy {
> __u32 ctx_id;
> @@ -1986,14 +2166,52 @@ struct drm_i915_reset_stats {
> __u32 pad;
> };
>
> +/**
> + * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
> + *
> + * Userptr objects have several restrictions on what ioctls can be used with the
> + * object handle.
> + */
> struct drm_i915_gem_userptr {
> + /**
> + * @user_ptr: The pointer to the allocated memory.
> + *
> + * Needs to be aligned to PAGE_SIZE.
> + */
> __u64 user_ptr;
> +
> + /**
> + * @user_size:
> + *
> + * The size in bytes for the allocated memory. This will also become the
> + * object size.
> + *
> + * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
> + * or larger.
> + */
> __u64 user_size;
> +
> + /**
> + * @flags:
> + *
> + * Supported flags:
> + *
> + * I915_USERPTR_READ_ONLY:
> + *
> + * Mark the object as readonly, this also means GPU access can only be
> + * readonly. This is only supported on HW which supports readonly access
> + * through the GTT. If the HW can't support readonly access, an error is
> + * returned.
> + *
> + * I915_USERPTR_UNSYNCHRONIZED:
> + *
> + * NOT USED. Setting this flag will result in an error.
> + */
> __u32 flags;
> #define I915_USERPTR_READ_ONLY 0x1
> #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
> /**
> - * Returned handle for the object.
> + * @handle: Returned handle for the object.
> *
> * Object handles are nonzero.
> */
> @@ -2376,6 +2594,76 @@ struct drm_i915_query_topology_info {
> __u8 data[];
> };
>
> +/**
> + * DOC: Engine Discovery uAPI
> + *
> + * Engine discovery uAPI is a way of enumerating physical engines present in a
> + * GPU associated with an open i915 DRM file descriptor. This supersedes the old
> + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
> + * `I915_PARAM_HAS_BLT`.
> + *
> + * The need for this interface came starting with Icelake and newer GPUs, which
> + * started to establish a pattern of having multiple engines of a same class,
> + * where not all instances were always completely functionally equivalent.
> + *
> + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
> + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
> + *
> + * Example for getting the list of engines:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_i915_query_engine_info *info;
> + * struct drm_i915_query_item item = {
> + * .query_id = DRM_I915_QUERY_ENGINE_INFO;
> + * };
> + * struct drm_i915_query query = {
> + * .num_items = 1,
> + * .items_ptr = (uintptr_t)&item,
> + * };
> + * int err, i;
> + *
> + * // First query the size of the blob we need, this needs to be large
> + * // enough to hold our array of engines. The kernel will fill out the
> + * // item.length for us, which is the number of bytes we need.
> + * //
> + * // Alternatively a large buffer can be allocated straight away enabling
> + * // querying in one pass, in which case item.length should contain the
> + * // length of the provided buffer.
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * info = calloc(1, item.length);
> + * // Now that we allocated the required number of bytes, we call the ioctl
> + * // again, this time with the data_ptr pointing to our newly allocated
> + * // blob, which the kernel can then populate with info on all engines.
> + * item.data_ptr = (uintptr_t)&info,
> + *
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * // We can now access each engine in the array
> + * for (i = 0; i < info->num_engines; i++) {
> + * struct drm_i915_engine_info einfo = info->engines[i];
> + * u16 class = einfo.engine.class;
> + * u16 instance = einfo.engine.instance;
> + * ....
> + * }
> + *
> + * free(info);
> + *
> + * Each of the enumerated engines, apart from being defined by its class and
> + * instance (see `struct i915_engine_class_instance`), also can have flags and
> + * capabilities defined as documented in i915_drm.h.
> + *
> + * For instance video engines which support HEVC encoding will have the
> + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
> + *
> + * Engine discovery only fully comes to its own when combined with the new way
> + * of addressing engines when submitting batch buffers using contexts with
> + * engine maps configured.
> + */
> +
> /**
> * struct drm_i915_engine_info
> *
> diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
> index 0e3cef81..dd646aed 100644
> --- a/lib/i915/i915_drm_local.h
> +++ b/lib/i915/i915_drm_local.h
> @@ -20,8 +20,6 @@ extern "C" {
> * clean these up when kernel uapi headers are sync'd.
> */
>
> -#define I915_MMAP_OFFSET_FIXED 4
> -
> #if defined(__cplusplus)
> }
> #endif
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2021-09-02 5:40 [igt-dev] [i-g-t] i915_drm.h sync Tejas Upadhyay
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2021-09-02 8:51 ` [igt-dev] [i-g-t] " Petri Latvala
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