* [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs @ 2021-09-07 21:39 Lucas De Marchi 2021-09-07 22:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork ` (3 more replies) 0 siblings, 4 replies; 7+ messages in thread From: Lucas De Marchi @ 2021-09-07 21:39 UTC (permalink / raw) To: intel-gfx; +Cc: Andi Shyti, Chris Wilson, Joonas Lahtinen Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a gt aware debugfs") says it was moving debug files to gt/, the i915_frequency_info file was left behind and its implementation copied into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several patches having to change both places to keep them in sync (and some patches failing to do so). The initial idea was to remove i915_frequency_info, but there are user space tools using it. From a quick code search there are other scripts and test tools besides igt, so it's not simply updating igt to get rid of the older file. Here we export a function using drm_printer as parameter and make both show() implementations to call this same function. Aside from a few variable name differences, for i915_frequency_info this brings a few lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP DOWN THRESHOLD and RP DOWN EI. These came in as part of commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to determine clk frequencies"), which didn't change both places. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++++++------- drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 2 + drivers/gpu/drm/i915/i915_debugfs.c | 227 +----------------------- 3 files changed, 74 insertions(+), 282 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c index f6733f279890..6a27c011d0ff 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c @@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused) } DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc); -static int frequency_show(struct seq_file *m, void *unused) +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) { - struct intel_gt *gt = m->private; struct drm_i915_private *i915 = gt->i915; struct intel_uncore *uncore = gt->uncore; struct intel_rps *rps = >->rps; @@ -254,21 +253,21 @@ static int frequency_show(struct seq_file *m, void *unused) u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); - seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); - seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); - seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> + drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); + drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); + drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> MEMSTAT_VID_SHIFT); - seq_printf(m, "Current P-state: %d\n", + drm_printf(p, "Current P-state: %d\n", (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { u32 rpmodectl, freq_sts; rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); - seq_printf(m, "Video Turbo Mode: %s\n", + drm_printf(p, "Video Turbo Mode: %s\n", yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); - seq_printf(m, "HW control enabled: %s\n", + drm_printf(p, "HW control enabled: %s\n", yesno(rpmodectl & GEN6_RP_ENABLE)); - seq_printf(m, "SW control enabled: %s\n", + drm_printf(p, "SW control enabled: %s\n", yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); @@ -276,25 +275,25 @@ static int frequency_show(struct seq_file *m, void *unused) freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); vlv_punit_put(i915); - seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); - seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq); + drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); + drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); - seq_printf(m, "actual GPU freq: %d MHz\n", + drm_printf(p, "actual GPU freq: %d MHz\n", intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); - seq_printf(m, "current GPU freq: %d MHz\n", + drm_printf(p, "current GPU freq: %d MHz\n", intel_gpu_freq(rps, rps->cur_freq)); - seq_printf(m, "max GPU freq: %d MHz\n", + drm_printf(p, "max GPU freq: %d MHz\n", intel_gpu_freq(rps, rps->max_freq)); - seq_printf(m, "min GPU freq: %d MHz\n", + drm_printf(p, "min GPU freq: %d MHz\n", intel_gpu_freq(rps, rps->min_freq)); - seq_printf(m, "idle GPU freq: %d MHz\n", + drm_printf(p, "idle GPU freq: %d MHz\n", intel_gpu_freq(rps, rps->idle_freq)); - seq_printf(m, "efficient (RPe) frequency: %d MHz\n", + drm_printf(p, "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(rps, rps->efficient_freq)); } else if (GRAPHICS_VER(i915) >= 6) { u32 rp_state_limits; @@ -374,109 +373,117 @@ static int frequency_show(struct seq_file *m, void *unused) } pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); - seq_printf(m, "Video Turbo Mode: %s\n", + drm_printf(p, "Video Turbo Mode: %s\n", yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); - seq_printf(m, "HW control enabled: %s\n", + drm_printf(p, "HW control enabled: %s\n", yesno(rpmodectl & GEN6_RP_ENABLE)); - seq_printf(m, "SW control enabled: %s\n", + drm_printf(p, "SW control enabled: %s\n", yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == GEN6_RP_MEDIA_SW_MODE)); - seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", + drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", pm_ier, pm_imr, pm_mask); if (GRAPHICS_VER(i915) <= 10) - seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", + drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", pm_isr, pm_iir); - seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", rps->pm_intrmsk_mbz); - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); - seq_printf(m, "Render p-state ratio: %d\n", + drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); + drm_printf(p, "Render p-state ratio: %d\n", (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); - seq_printf(m, "Render p-state VID: %d\n", + drm_printf(p, "Render p-state VID: %d\n", gt_perf_status & 0xff); - seq_printf(m, "Render p-state limit: %d\n", + drm_printf(p, "Render p-state limit: %d\n", rp_state_limits & 0xff); - seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); - seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); - seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); - seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); - seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); - seq_printf(m, "CAGF: %dMHz\n", cagf); - seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", + drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); + drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); + drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); + drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); + drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); + drm_printf(p, "CAGF: %dMHz\n", cagf); + drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", rpcurupei, intel_gt_pm_interval_to_ns(gt, rpcurupei)); - seq_printf(m, "RP CUR UP: %d (%lldns)\n", + drm_printf(p, "RP CUR UP: %d (%lldns)\n", rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); - seq_printf(m, "RP PREV UP: %d (%lldns)\n", + drm_printf(p, "RP PREV UP: %d (%lldns)\n", rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); - seq_printf(m, "Up threshold: %d%%\n", + drm_printf(p, "Up threshold: %d%%\n", rps->power.up_threshold); - seq_printf(m, "RP UP EI: %d (%lldns)\n", + drm_printf(p, "RP UP EI: %d (%lldns)\n", rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); - seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n", + drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); - seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", + drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", rpcurdownei, intel_gt_pm_interval_to_ns(gt, rpcurdownei)); - seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", + drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", rpcurdown, intel_gt_pm_interval_to_ns(gt, rpcurdown)); - seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", + drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", rpprevdown, intel_gt_pm_interval_to_ns(gt, rpprevdown)); - seq_printf(m, "Down threshold: %d%%\n", + drm_printf(p, "Down threshold: %d%%\n", rps->power.down_threshold); - seq_printf(m, "RP DOWN EI: %d (%lldns)\n", + drm_printf(p, "RP DOWN EI: %d (%lldns)\n", rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); - seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n", + drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(rps, max_freq)); - seq_printf(m, "Max overclocked frequency: %dMHz\n", + drm_printf(p, "Max overclocked frequency: %dMHz\n", intel_gpu_freq(rps, rps->max_freq)); - seq_printf(m, "Current freq: %d MHz\n", + drm_printf(p, "Current freq: %d MHz\n", intel_gpu_freq(rps, rps->cur_freq)); - seq_printf(m, "Actual freq: %d MHz\n", cagf); - seq_printf(m, "Idle freq: %d MHz\n", + drm_printf(p, "Actual freq: %d MHz\n", cagf); + drm_printf(p, "Idle freq: %d MHz\n", intel_gpu_freq(rps, rps->idle_freq)); - seq_printf(m, "Min freq: %d MHz\n", + drm_printf(p, "Min freq: %d MHz\n", intel_gpu_freq(rps, rps->min_freq)); - seq_printf(m, "Boost freq: %d MHz\n", + drm_printf(p, "Boost freq: %d MHz\n", intel_gpu_freq(rps, rps->boost_freq)); - seq_printf(m, "Max freq: %d MHz\n", + drm_printf(p, "Max freq: %d MHz\n", intel_gpu_freq(rps, rps->max_freq)); - seq_printf(m, + drm_printf(p, "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(rps, rps->efficient_freq)); } else { - seq_puts(m, "no P-state info available\n"); + drm_puts(p, "no P-state info available\n"); } - seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); - seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); + drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); + drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); + drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); intel_runtime_pm_put(uncore->rpm, wakeref); +} + +static int frequency_show(struct seq_file *m, void *unused) +{ + struct intel_gt *gt = m->private; + struct drm_printer p = drm_seq_file_printer(m); + + debugfs_gt_pm_frequency_dump(gt, &p); return 0; } diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h index 4cf5f5c9da7d..8eb1b77137fd 100644 --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h @@ -8,7 +8,9 @@ struct intel_gt; struct dentry; +struct drm_printer; +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m); void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root); #endif /* DEBUGFS_GT_PM_H */ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 04351a851586..edc9a6f92c4f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -32,6 +32,7 @@ #include <drm/drm_debugfs.h> #include "gem/i915_gem_context.h" +#include "gt/debugfs_gt_pm.h" #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_gt_clock_utils.h" #include "gt/intel_gt.h" @@ -354,230 +355,12 @@ static const struct file_operations i915_error_state_fops = { static int i915_frequency_info(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); - struct intel_uncore *uncore = &dev_priv->uncore; - struct intel_rps *rps = &dev_priv->gt.rps; - intel_wakeref_t wakeref; - - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - - if (GRAPHICS_VER(dev_priv) == 5) { - u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); - u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); - - seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); - seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); - seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> - MEMSTAT_VID_SHIFT); - seq_printf(m, "Current P-state: %d\n", - (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - u32 rpmodectl, freq_sts; - - rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); - seq_printf(m, "Video Turbo Mode: %s\n", - yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); - seq_printf(m, "HW control enabled: %s\n", - yesno(rpmodectl & GEN6_RP_ENABLE)); - seq_printf(m, "SW control enabled: %s\n", - yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == - GEN6_RP_MEDIA_SW_MODE)); - - vlv_punit_get(dev_priv); - freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); - vlv_punit_put(dev_priv); - - seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); - seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); - - seq_printf(m, "actual GPU freq: %d MHz\n", - intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); - - seq_printf(m, "current GPU freq: %d MHz\n", - intel_gpu_freq(rps, rps->cur_freq)); - - seq_printf(m, "max GPU freq: %d MHz\n", - intel_gpu_freq(rps, rps->max_freq)); - - seq_printf(m, "min GPU freq: %d MHz\n", - intel_gpu_freq(rps, rps->min_freq)); - - seq_printf(m, "idle GPU freq: %d MHz\n", - intel_gpu_freq(rps, rps->idle_freq)); - - seq_printf(m, - "efficient (RPe) frequency: %d MHz\n", - intel_gpu_freq(rps, rps->efficient_freq)); - } else if (GRAPHICS_VER(dev_priv) >= 6) { - u32 rp_state_limits; - u32 gt_perf_status; - u32 rp_state_cap; - u32 rpmodectl, rpinclimit, rpdeclimit; - u32 rpstat, cagf, reqf; - u32 rpupei, rpcurup, rpprevup; - u32 rpdownei, rpcurdown, rpprevdown; - u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; - int max_freq; - - rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS); - rp_state_cap = intel_rps_read_state_cap(rps); - if (IS_GEN9_LP(dev_priv)) - gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS); - else - gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS); - - /* RPSTAT1 is in the GT power well */ - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); - - reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ); - if (GRAPHICS_VER(dev_priv) >= 9) - reqf >>= 23; - else { - reqf &= ~GEN6_TURBO_DISABLE; - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - reqf >>= 24; - else - reqf >>= 25; - } - reqf = intel_gpu_freq(rps, reqf); - - rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); - rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD); - rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD); - - rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1); - rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; - rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; - rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; - rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; - rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; - rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; - cagf = intel_rps_read_actual_frequency(rps); - - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); - - if (GRAPHICS_VER(dev_priv) >= 11) { - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); - /* - * The equivalent to the PM ISR & IIR cannot be read - * without affecting the current state of the system - */ - pm_isr = 0; - pm_iir = 0; - } else if (GRAPHICS_VER(dev_priv) >= 8) { - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2)); - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2)); - pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2)); - pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2)); - } else { - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER); - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR); - pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR); - pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); - } - pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK); - - seq_printf(m, "Video Turbo Mode: %s\n", - yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); - seq_printf(m, "HW control enabled: %s\n", - yesno(rpmodectl & GEN6_RP_ENABLE)); - seq_printf(m, "SW control enabled: %s\n", - yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == - GEN6_RP_MEDIA_SW_MODE)); - - seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", - pm_ier, pm_imr, pm_mask); - if (GRAPHICS_VER(dev_priv) <= 10) - seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", - pm_isr, pm_iir); - seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", - rps->pm_intrmsk_mbz); - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); - seq_printf(m, "Render p-state ratio: %d\n", - (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); - seq_printf(m, "Render p-state VID: %d\n", - gt_perf_status & 0xff); - seq_printf(m, "Render p-state limit: %d\n", - rp_state_limits & 0xff); - seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); - seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); - seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); - seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); - seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); - seq_printf(m, "CAGF: %dMHz\n", cagf); - seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", - rpupei, - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); - seq_printf(m, "RP CUR UP: %d (%lldun)\n", - rpcurup, - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); - seq_printf(m, "RP PREV UP: %d (%lldns)\n", - rpprevup, - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); - seq_printf(m, "Up threshold: %d%%\n", - rps->power.up_threshold); - - seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", - rpdownei, - intel_gt_pm_interval_to_ns(&dev_priv->gt, - rpdownei)); - seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", - rpcurdown, - intel_gt_pm_interval_to_ns(&dev_priv->gt, - rpcurdown)); - seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", - rpprevdown, - intel_gt_pm_interval_to_ns(&dev_priv->gt, - rpprevdown)); - seq_printf(m, "Down threshold: %d%%\n", - rps->power.down_threshold); - - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : - rp_state_cap >> 16) & 0xff; - max_freq *= (IS_GEN9_BC(dev_priv) || - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", - intel_gpu_freq(rps, max_freq)); - - max_freq = (rp_state_cap & 0xff00) >> 8; - max_freq *= (IS_GEN9_BC(dev_priv) || - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", - intel_gpu_freq(rps, max_freq)); - - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : - rp_state_cap >> 0) & 0xff; - max_freq *= (IS_GEN9_BC(dev_priv) || - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); - seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", - intel_gpu_freq(rps, max_freq)); - seq_printf(m, "Max overclocked frequency: %dMHz\n", - intel_gpu_freq(rps, rps->max_freq)); - - seq_printf(m, "Current freq: %d MHz\n", - intel_gpu_freq(rps, rps->cur_freq)); - seq_printf(m, "Actual freq: %d MHz\n", cagf); - seq_printf(m, "Idle freq: %d MHz\n", - intel_gpu_freq(rps, rps->idle_freq)); - seq_printf(m, "Min freq: %d MHz\n", - intel_gpu_freq(rps, rps->min_freq)); - seq_printf(m, "Boost freq: %d MHz\n", - intel_gpu_freq(rps, rps->boost_freq)); - seq_printf(m, "Max freq: %d MHz\n", - intel_gpu_freq(rps, rps->max_freq)); - seq_printf(m, - "efficient (RPe) frequency: %d MHz\n", - intel_gpu_freq(rps, rps->efficient_freq)); - } else { - seq_puts(m, "no P-state info available\n"); - } + struct drm_i915_private *i915 = node_to_i915(m->private); + struct intel_gt *gt = &i915->gt; + struct drm_printer p = drm_seq_file_printer(m); - seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); - seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); - seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); + debugfs_gt_pm_frequency_dump(gt, &p); - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); return 0; } -- 2.32.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: deduplicate frequency dump on debugfs 2021-09-07 21:39 [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs Lucas De Marchi @ 2021-09-07 22:35 ` Patchwork 2021-09-07 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-09-07 22:35 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: drm/i915: deduplicate frequency dump on debugfs URL : https://patchwork.freedesktop.org/series/94455/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7c0de9fb0c56 drm/i915: deduplicate frequency dump on debugfs -:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #11: patches failing to do so). The initial idea was to remove i915_frequency_info, total: 0 errors, 1 warnings, 0 checks, 481 lines checked ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: deduplicate frequency dump on debugfs 2021-09-07 21:39 [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs Lucas De Marchi 2021-09-07 22:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2021-09-07 23:21 ` Patchwork 2021-09-08 3:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-09-08 8:54 ` [Intel-gfx] [PATCH] " Jani Nikula 3 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-09-07 23:21 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5118 bytes --] == Series Details == Series: drm/i915: deduplicate frequency dump on debugfs URL : https://patchwork.freedesktop.org/series/94455/ State : success == Summary == CI Bug Log - changes from CI_DRM_10559 -> Patchwork_20983 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/index.html Known issues ------------ Here are the changes found in Patchwork_20983 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html * igt@i915_selftest@live@gt_timelines: - fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#4034]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-rkl-guc/igt@i915_selftest@live@gt_timelines.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-n3050: [PASS][5] -> [DMESG-FAIL][6] ([i915#2927] / [i915#3428]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html * igt@runner@aborted: - fi-rkl-guc: NOTRUN -> [FAIL][8] ([i915#3928]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-rkl-guc/igt@runner@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / [i915#3428]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-bsw-n3050/igt@runner@aborted.html #### Possible fixes #### * igt@i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/fi-tgl-dsi/igt@i915_module_load@reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-tgl-dsi/igt@i915_module_load@reload.html * igt@i915_selftest@live@hangcheck: - {fi-hsw-gt1}: [DMESG-WARN][12] ([i915#3303]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [DMESG-WARN][14] ([i915#295]) -> [PASS][15] +11 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928 [i915#4034]: https://gitlab.freedesktop.org/drm/intel/issues/4034 Participating hosts (48 -> 40) ------------------------------ Missing (8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus Build changes ------------- * Linux: CI_DRM_10559 -> Patchwork_20983 CI-20190529: 20190529 CI_DRM_10559: 084c93c6caab7b5b67361e090a21a607f8fd02e0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6198: 0f17f38c3e5e2139e59f1458c149bb7a93c88bbf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20983: 7c0de9fb0c56de6db7b4290b3fa8d7f8c4eaf243 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7c0de9fb0c56 drm/i915: deduplicate frequency dump on debugfs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/index.html [-- Attachment #2: Type: text/html, Size: 6162 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: deduplicate frequency dump on debugfs 2021-09-07 21:39 [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs Lucas De Marchi 2021-09-07 22:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2021-09-07 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-09-08 3:20 ` Patchwork 2021-09-08 8:54 ` [Intel-gfx] [PATCH] " Jani Nikula 3 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2021-09-08 3:20 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30270 bytes --] == Series Details == Series: drm/i915: deduplicate frequency dump on debugfs URL : https://patchwork.freedesktop.org/series/94455/ State : success == Summary == CI Bug Log - changes from CI_DRM_10559_full -> Patchwork_20983_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_20983_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@gem_create@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#198]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl9/igt@gem_ctx_isolation@preservation-s3@bcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl10/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][4] -> [INCOMPLETE][5] ([i915#794]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_ctx_persistence@process: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-snb2/igt@gem_ctx_persistence@process.html * igt@gem_ctx_shared@q-in-order: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +221 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-snb2/igt@gem_ctx_shared@q-in-order.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#3063] / [i915#3648]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb6/igt@gem_eio@unwedge-stress.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb8/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][16] -> [SKIP][17] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][18] -> [SKIP][19] ([i915#2190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb2/igt@gem_huc_copy@huc-copy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb6/igt@gem_huc_copy@huc-copy.html * igt@gem_mmap_gtt@cpuset-big-copy-xy: - shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2428]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy-xy.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][22] ([i915#2658]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@gem_pwrite@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-tglb: NOTRUN -> [DMESG-WARN][23] ([i915#3002]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][24] ([i915#3318]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl1/igt@gem_userptr_blits@vma-merge.html * igt@gem_workarounds@suspend-resume: - shard-tglb: [PASS][25] -> [INCOMPLETE][26] ([i915#456]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb1/igt@gem_workarounds@suspend-resume.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@gem_workarounds@suspend-resume.html * igt@gen9_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> [SKIP][27] ([i915#2856]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@gen9_exec_parse@basic-rejected.html * igt@gen9_exec_parse@bb-chained: - shard-tglb: NOTRUN -> [SKIP][28] ([i915#2856]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@gen9_exec_parse@bb-chained.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271]) +218 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: NOTRUN -> [DMESG-WARN][30] ([i915#180]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl7/igt@i915_suspend@fence-restore-untiled.html * igt@kms_big_fb@linear-32bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][31] ([fdo#110725] / [fdo#111614]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_big_fb@linear-32bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +3 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3777]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +10 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][38] ([i915#3689]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_ccs@pipe-d-bad-aux-stride-yf_tiled_ccs.html * igt@kms_chamelium@hdmi-crc-fast: - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109284] / [fdo#111827]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_chamelium@hdmi-crc-fast.html - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_chamelium@vga-hpd: - shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +15 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_chamelium@vga-hpd.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +11 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-a-ctm-green-to-red: - shard-glk: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl6/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-d-ctm-green-to-red: - shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][46] ([i915#1319]) +1 similar issue [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl1/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@dp-mst-type-1: - shard-iclb: NOTRUN -> [SKIP][47] ([i915#3116]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_content_protection@dp-mst-type-1.html - shard-tglb: NOTRUN -> [SKIP][48] ([i915#3116]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_content_protection@dp-mst-type-1.html * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen: - shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +34 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl6/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size: - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109274] / [fdo#109278]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][51] -> [FAIL][52] ([i915#2346]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_fbcon_fbt@psr-suspend: - shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#2411] / [i915#456]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb8/igt@kms_fbcon_fbt@psr-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-flip-vs-suspend-interruptible: - shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111825]) +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_flip@2x-flip-vs-suspend-interruptible.html - shard-skl: NOTRUN -> [SKIP][56] ([fdo#109271]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl7/igt@kms_flip@2x-flip-vs-suspend-interruptible.html * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2: - shard-glk: [PASS][57] -> [FAIL][58] ([i915#79]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][59] -> [INCOMPLETE][60] ([i915#636]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: - shard-skl: [PASS][61] -> [FAIL][62] ([i915#2122]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl10/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile: - shard-iclb: [PASS][63] -> [SKIP][64] ([i915#3701]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render: - shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109280]) +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw: - shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271]) +34 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][67] -> [FAIL][68] ([i915#1188]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl2/igt@kms_hdr@bpc-switch.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl4/igt@kms_hdr@bpc-switch.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_hdr@static-toggle-dpms: - shard-tglb: NOTRUN -> [SKIP][71] ([i915#1187]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@kms_hdr@static-toggle-dpms.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-glk: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265]) +2 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][75] ([i915#265]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][76] -> [FAIL][77] ([fdo#108145] / [i915#265]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: NOTRUN -> [SKIP][78] ([i915#3536]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][79] ([fdo#112054]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html * igt@kms_psr2_sf@cursor-plane-update-sf: - shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_psr2_sf@cursor-plane-update-sf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2: - shard-tglb: NOTRUN -> [SKIP][81] ([i915#2920]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1: - shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][84] -> [SKIP][85] ([fdo#109642] / [fdo#111068] / [i915#658]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb2/igt@kms_psr2_su@frontbuffer.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb4/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][86] -> [SKIP][87] ([fdo#109441]) +2 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb2/igt@kms_psr@psr2_dpms.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb4/igt@kms_psr@psr2_dpms.html * igt@kms_psr@psr2_sprite_blt: - shard-tglb: NOTRUN -> [FAIL][88] ([i915#132] / [i915#3467]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@kms_psr@psr2_sprite_blt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][89] -> [DMESG-WARN][90] ([i915#180] / [i915#295]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-idle-hang: - shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278]) +5 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb3/igt@kms_vblank@pipe-d-ts-continuation-idle-hang.html * igt@kms_writeback@writeback-invalid-parameters: - shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2437]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@kms_writeback@writeback-invalid-parameters.html * igt@nouveau_crc@pipe-a-source-outp-complete: - shard-iclb: NOTRUN -> [SKIP][93] ([i915#2530]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@nouveau_crc@pipe-a-source-outp-complete.html * igt@nouveau_crc@pipe-d-source-rg: - shard-tglb: NOTRUN -> [SKIP][94] ([i915#2530]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb7/igt@nouveau_crc@pipe-d-source-rg.html - shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278] / [i915#2530]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@nouveau_crc@pipe-d-source-rg.html * igt@prime_nv_test@i915_blt_fill_nv_read: - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109291]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb8/igt@prime_nv_test@i915_blt_fill_nv_read.html * igt@prime_vgem@coherency-blt: - shard-glk: [PASS][97] -> [INCOMPLETE][98] ([i915#2944]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-glk9/igt@prime_vgem@coherency-blt.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk8/igt@prime_vgem@coherency-blt.html * igt@sysfs_clients@sema-10: - shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994]) +2 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl1/igt@sysfs_clients@sema-10.html * igt@sysfs_clients@sema-50: - shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk5/igt@sysfs_clients@sema-50.html #### Possible fixes #### * igt@gem_eio@in-flight-contexts-immediate: - shard-iclb: [TIMEOUT][101] ([i915#3070]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb1/igt@gem_eio@in-flight-contexts-immediate.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb3/igt@gem_eio@in-flight-contexts-immediate.html * igt@gem_eio@kms: - shard-skl: [TIMEOUT][103] ([i915#3063]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl4/igt@gem_eio@kms.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl10/igt@gem_eio@kms.html * igt@gem_eio@unwedge-stress: - shard-iclb: [TIMEOUT][105] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb6/igt@gem_eio@unwedge-stress.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb6/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [FAIL][107] ([i915#2842]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl6/igt@gem_exec_fair@basic-none@vecs0.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][109] ([i915#2842]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][111] ([i915#2849]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_mmap_gtt@cpuset-medium-copy-odd: - shard-iclb: [FAIL][113] ([i915#2428]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb6/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb2/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html * igt@gem_softpin@noreloc-s3: - shard-apl: [DMESG-WARN][115] ([i915#180]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-apl8/igt@gem_softpin@noreloc-s3.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-apl8/igt@gem_softpin@noreloc-s3.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][117] ([i915#454]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb8/igt@i915_pm_dc@dc6-psr.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb5/igt@i915_pm_dc@dc6-psr.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-kbl7/igt@i915_suspend@sysfs-reader.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-kbl6/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@x-tiled-32bpp-rotate-0: - shard-glk: [DMESG-WARN][121] ([i915#118] / [i915#95]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html * igt@kms_big_fb@y-tiled-64bpp-rotate-180: - shard-iclb: [DMESG-WARN][123] ([i915#3621]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb1/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb3/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-tglb: [INCOMPLETE][125] ([i915#2411] / [i915#456]) -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][127] ([i915#72]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][129] ([i915#2122]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [FAIL][131] ([i915#79]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-modeset-vs-hang@a-edp1: - shard-skl: [DMESG-WARN][133] ([i915#1982]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl5/igt@kms_flip@flip-vs-modeset-vs-hang@a-edp1.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl9/igt@kms_flip@flip-vs-modeset-vs-hang@a-edp1.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][135] ([fdo#108145] / [i915#265]) -> [PASS][136] [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][137] ([fdo#109441]) -> [PASS][138] +1 similar issue [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb3/igt@kms_psr@psr2_no_drrs.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb2/igt@kms_psr@psr2_no_drrs.html * igt@perf@polling-parameterized: - shard-skl: [FAIL][139] ([i915#1542]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-skl9/igt@perf@polling-parameterized.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-skl10/igt@perf@polling-parameterized.html #### Warnings #### * igt@gem_exec_fair@basic-pace@vcs1: - shard-tglb: [FAIL][141] ([i915#2842]) -> [FAIL][142] ([i915#2876]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-tglb8/igt@gem_exec_fair@basic-pace@vcs1.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][143] ([i915#1804] / [i915#2684]) -> [WARN][144] ([i915#2684]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][145] ([i915#2684]) -> [WARN][146] ([i915#1804] / [i915#2684]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10559/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20983/index.html [-- Attachment #2: Type: text/html, Size: 33574 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs 2021-09-07 21:39 [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs Lucas De Marchi ` (2 preceding siblings ...) 2021-09-08 3:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-09-08 8:54 ` Jani Nikula 2021-09-08 14:14 ` Lucas De Marchi 3 siblings, 1 reply; 7+ messages in thread From: Jani Nikula @ 2021-09-08 8:54 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Andi Shyti, Chris Wilson, Joonas Lahtinen On Tue, 07 Sep 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a > gt aware debugfs") says it was moving debug files to gt/, the > i915_frequency_info file was left behind and its implementation copied > into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several > patches having to change both places to keep them in sync (and some > patches failing to do so). The initial idea was to remove i915_frequency_info, > but there are user space tools using it. From a quick code search there > are other scripts and test tools besides igt, so it's not simply > updating igt to get rid of the older file. > > Here we export a function using drm_printer as parameter and make > both show() implementations to call this same function. Aside from a few > variable name differences, for i915_frequency_info this brings a few > lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP > DOWN THRESHOLD and RP DOWN EI. These came in as part of > commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to > determine clk frequencies"), which didn't change both places. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++++++------- > drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 2 + > drivers/gpu/drm/i915/i915_debugfs.c | 227 +----------------------- > 3 files changed, 74 insertions(+), 282 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > index f6733f279890..6a27c011d0ff 100644 > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c > @@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused) > } > DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc); > > -static int frequency_show(struct seq_file *m, void *unused) > +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) The debugfs prefix belongs to debugfs, and I don't think we should have non-static functions with that prefix. I know it's in line with what's currently in the file, and I've complained about it before, but apparently that hasn't been enough. BR, Jani. > { > - struct intel_gt *gt = m->private; > struct drm_i915_private *i915 = gt->i915; > struct intel_uncore *uncore = gt->uncore; > struct intel_rps *rps = >->rps; > @@ -254,21 +253,21 @@ static int frequency_show(struct seq_file *m, void *unused) > u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); > u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); > > - seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); > - seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); > - seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> > + drm_printf(p, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); > + drm_printf(p, "Requested VID: %d\n", rgvswctl & 0x3f); > + drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> > MEMSTAT_VID_SHIFT); > - seq_printf(m, "Current P-state: %d\n", > + drm_printf(p, "Current P-state: %d\n", > (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > u32 rpmodectl, freq_sts; > > rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL); > - seq_printf(m, "Video Turbo Mode: %s\n", > + drm_printf(p, "Video Turbo Mode: %s\n", > yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > - seq_printf(m, "HW control enabled: %s\n", > + drm_printf(p, "HW control enabled: %s\n", > yesno(rpmodectl & GEN6_RP_ENABLE)); > - seq_printf(m, "SW control enabled: %s\n", > + drm_printf(p, "SW control enabled: %s\n", > yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > GEN6_RP_MEDIA_SW_MODE)); > > @@ -276,25 +275,25 @@ static int frequency_show(struct seq_file *m, void *unused) > freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > > - seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); > - seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq); > + drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); > + drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); > > - seq_printf(m, "actual GPU freq: %d MHz\n", > + drm_printf(p, "actual GPU freq: %d MHz\n", > intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); > > - seq_printf(m, "current GPU freq: %d MHz\n", > + drm_printf(p, "current GPU freq: %d MHz\n", > intel_gpu_freq(rps, rps->cur_freq)); > > - seq_printf(m, "max GPU freq: %d MHz\n", > + drm_printf(p, "max GPU freq: %d MHz\n", > intel_gpu_freq(rps, rps->max_freq)); > > - seq_printf(m, "min GPU freq: %d MHz\n", > + drm_printf(p, "min GPU freq: %d MHz\n", > intel_gpu_freq(rps, rps->min_freq)); > > - seq_printf(m, "idle GPU freq: %d MHz\n", > + drm_printf(p, "idle GPU freq: %d MHz\n", > intel_gpu_freq(rps, rps->idle_freq)); > > - seq_printf(m, "efficient (RPe) frequency: %d MHz\n", > + drm_printf(p, "efficient (RPe) frequency: %d MHz\n", > intel_gpu_freq(rps, rps->efficient_freq)); > } else if (GRAPHICS_VER(i915) >= 6) { > u32 rp_state_limits; > @@ -374,109 +373,117 @@ static int frequency_show(struct seq_file *m, void *unused) > } > pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK); > > - seq_printf(m, "Video Turbo Mode: %s\n", > + drm_printf(p, "Video Turbo Mode: %s\n", > yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > - seq_printf(m, "HW control enabled: %s\n", > + drm_printf(p, "HW control enabled: %s\n", > yesno(rpmodectl & GEN6_RP_ENABLE)); > - seq_printf(m, "SW control enabled: %s\n", > + drm_printf(p, "SW control enabled: %s\n", > yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > GEN6_RP_MEDIA_SW_MODE)); > > - seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", > + drm_printf(p, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", > pm_ier, pm_imr, pm_mask); > if (GRAPHICS_VER(i915) <= 10) > - seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", > + drm_printf(p, "PM ISR=0x%08x IIR=0x%08x\n", > pm_isr, pm_iir); > - seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", > + drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); > - seq_printf(m, "Render p-state ratio: %d\n", > + drm_printf(p, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); > + drm_printf(p, "Render p-state ratio: %d\n", > (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8); > - seq_printf(m, "Render p-state VID: %d\n", > + drm_printf(p, "Render p-state VID: %d\n", > gt_perf_status & 0xff); > - seq_printf(m, "Render p-state limit: %d\n", > + drm_printf(p, "Render p-state limit: %d\n", > rp_state_limits & 0xff); > - seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); > - seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); > - seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); > - seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); > - seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); > - seq_printf(m, "CAGF: %dMHz\n", cagf); > - seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", > + drm_printf(p, "RPSTAT1: 0x%08x\n", rpstat); > + drm_printf(p, "RPMODECTL: 0x%08x\n", rpmodectl); > + drm_printf(p, "RPINCLIMIT: 0x%08x\n", rpinclimit); > + drm_printf(p, "RPDECLIMIT: 0x%08x\n", rpdeclimit); > + drm_printf(p, "RPNSWREQ: %dMHz\n", reqf); > + drm_printf(p, "CAGF: %dMHz\n", cagf); > + drm_printf(p, "RP CUR UP EI: %d (%lldns)\n", > rpcurupei, > intel_gt_pm_interval_to_ns(gt, rpcurupei)); > - seq_printf(m, "RP CUR UP: %d (%lldns)\n", > + drm_printf(p, "RP CUR UP: %d (%lldns)\n", > rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup)); > - seq_printf(m, "RP PREV UP: %d (%lldns)\n", > + drm_printf(p, "RP PREV UP: %d (%lldns)\n", > rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup)); > - seq_printf(m, "Up threshold: %d%%\n", > + drm_printf(p, "Up threshold: %d%%\n", > rps->power.up_threshold); > - seq_printf(m, "RP UP EI: %d (%lldns)\n", > + drm_printf(p, "RP UP EI: %d (%lldns)\n", > rpupei, intel_gt_pm_interval_to_ns(gt, rpupei)); > - seq_printf(m, "RP UP THRESHOLD: %d (%lldns)\n", > + drm_printf(p, "RP UP THRESHOLD: %d (%lldns)\n", > rpupt, intel_gt_pm_interval_to_ns(gt, rpupt)); > > - seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", > + drm_printf(p, "RP CUR DOWN EI: %d (%lldns)\n", > rpcurdownei, > intel_gt_pm_interval_to_ns(gt, rpcurdownei)); > - seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", > + drm_printf(p, "RP CUR DOWN: %d (%lldns)\n", > rpcurdown, > intel_gt_pm_interval_to_ns(gt, rpcurdown)); > - seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", > + drm_printf(p, "RP PREV DOWN: %d (%lldns)\n", > rpprevdown, > intel_gt_pm_interval_to_ns(gt, rpprevdown)); > - seq_printf(m, "Down threshold: %d%%\n", > + drm_printf(p, "Down threshold: %d%%\n", > rps->power.down_threshold); > - seq_printf(m, "RP DOWN EI: %d (%lldns)\n", > + drm_printf(p, "RP DOWN EI: %d (%lldns)\n", > rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei)); > - seq_printf(m, "RP DOWN THRESHOLD: %d (%lldns)\n", > + drm_printf(p, "RP DOWN THRESHOLD: %d (%lldns)\n", > rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt)); > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 : > rp_state_cap >> 16) & 0xff; > max_freq *= (IS_GEN9_BC(i915) || > GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", > + drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(rps, max_freq)); > > max_freq = (rp_state_cap & 0xff00) >> 8; > max_freq *= (IS_GEN9_BC(i915) || > GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", > + drm_printf(p, "Nominal (RP1) frequency: %dMHz\n", > intel_gpu_freq(rps, max_freq)); > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 : > rp_state_cap >> 0) & 0xff; > max_freq *= (IS_GEN9_BC(i915) || > GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", > + drm_printf(p, "Max non-overclocked (RP0) frequency: %dMHz\n", > intel_gpu_freq(rps, max_freq)); > - seq_printf(m, "Max overclocked frequency: %dMHz\n", > + drm_printf(p, "Max overclocked frequency: %dMHz\n", > intel_gpu_freq(rps, rps->max_freq)); > > - seq_printf(m, "Current freq: %d MHz\n", > + drm_printf(p, "Current freq: %d MHz\n", > intel_gpu_freq(rps, rps->cur_freq)); > - seq_printf(m, "Actual freq: %d MHz\n", cagf); > - seq_printf(m, "Idle freq: %d MHz\n", > + drm_printf(p, "Actual freq: %d MHz\n", cagf); > + drm_printf(p, "Idle freq: %d MHz\n", > intel_gpu_freq(rps, rps->idle_freq)); > - seq_printf(m, "Min freq: %d MHz\n", > + drm_printf(p, "Min freq: %d MHz\n", > intel_gpu_freq(rps, rps->min_freq)); > - seq_printf(m, "Boost freq: %d MHz\n", > + drm_printf(p, "Boost freq: %d MHz\n", > intel_gpu_freq(rps, rps->boost_freq)); > - seq_printf(m, "Max freq: %d MHz\n", > + drm_printf(p, "Max freq: %d MHz\n", > intel_gpu_freq(rps, rps->max_freq)); > - seq_printf(m, > + drm_printf(p, > "efficient (RPe) frequency: %d MHz\n", > intel_gpu_freq(rps, rps->efficient_freq)); > } else { > - seq_puts(m, "no P-state info available\n"); > + drm_puts(p, "no P-state info available\n"); > } > > - seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); > - seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); > - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); > + drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk); > + drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq); > + drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); > > intel_runtime_pm_put(uncore->rpm, wakeref); > +} > + > +static int frequency_show(struct seq_file *m, void *unused) > +{ > + struct intel_gt *gt = m->private; > + struct drm_printer p = drm_seq_file_printer(m); > + > + debugfs_gt_pm_frequency_dump(gt, &p); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h > index 4cf5f5c9da7d..8eb1b77137fd 100644 > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.h > @@ -8,7 +8,9 @@ > > struct intel_gt; > struct dentry; > +struct drm_printer; > > +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m); > void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root); > > #endif /* DEBUGFS_GT_PM_H */ > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 04351a851586..edc9a6f92c4f 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -32,6 +32,7 @@ > #include <drm/drm_debugfs.h> > > #include "gem/i915_gem_context.h" > +#include "gt/debugfs_gt_pm.h" > #include "gt/intel_gt_buffer_pool.h" > #include "gt/intel_gt_clock_utils.h" > #include "gt/intel_gt.h" > @@ -354,230 +355,12 @@ static const struct file_operations i915_error_state_fops = { > > static int i915_frequency_info(struct seq_file *m, void *unused) > { > - struct drm_i915_private *dev_priv = node_to_i915(m->private); > - struct intel_uncore *uncore = &dev_priv->uncore; > - struct intel_rps *rps = &dev_priv->gt.rps; > - intel_wakeref_t wakeref; > - > - wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); > - > - if (GRAPHICS_VER(dev_priv) == 5) { > - u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); > - u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); > - > - seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); > - seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); > - seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> > - MEMSTAT_VID_SHIFT); > - seq_printf(m, "Current P-state: %d\n", > - (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); > - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > - u32 rpmodectl, freq_sts; > - > - rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); > - seq_printf(m, "Video Turbo Mode: %s\n", > - yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > - seq_printf(m, "HW control enabled: %s\n", > - yesno(rpmodectl & GEN6_RP_ENABLE)); > - seq_printf(m, "SW control enabled: %s\n", > - yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > - GEN6_RP_MEDIA_SW_MODE)); > - > - vlv_punit_get(dev_priv); > - freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > - vlv_punit_put(dev_priv); > - > - seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); > - seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); > - > - seq_printf(m, "actual GPU freq: %d MHz\n", > - intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); > - > - seq_printf(m, "current GPU freq: %d MHz\n", > - intel_gpu_freq(rps, rps->cur_freq)); > - > - seq_printf(m, "max GPU freq: %d MHz\n", > - intel_gpu_freq(rps, rps->max_freq)); > - > - seq_printf(m, "min GPU freq: %d MHz\n", > - intel_gpu_freq(rps, rps->min_freq)); > - > - seq_printf(m, "idle GPU freq: %d MHz\n", > - intel_gpu_freq(rps, rps->idle_freq)); > - > - seq_printf(m, > - "efficient (RPe) frequency: %d MHz\n", > - intel_gpu_freq(rps, rps->efficient_freq)); > - } else if (GRAPHICS_VER(dev_priv) >= 6) { > - u32 rp_state_limits; > - u32 gt_perf_status; > - u32 rp_state_cap; > - u32 rpmodectl, rpinclimit, rpdeclimit; > - u32 rpstat, cagf, reqf; > - u32 rpupei, rpcurup, rpprevup; > - u32 rpdownei, rpcurdown, rpprevdown; > - u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; > - int max_freq; > - > - rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS); > - rp_state_cap = intel_rps_read_state_cap(rps); > - if (IS_GEN9_LP(dev_priv)) > - gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS); > - else > - gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS); > - > - /* RPSTAT1 is in the GT power well */ > - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); > - > - reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ); > - if (GRAPHICS_VER(dev_priv) >= 9) > - reqf >>= 23; > - else { > - reqf &= ~GEN6_TURBO_DISABLE; > - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > - reqf >>= 24; > - else > - reqf >>= 25; > - } > - reqf = intel_gpu_freq(rps, reqf); > - > - rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); > - rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD); > - rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD); > - > - rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1); > - rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > - rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > - rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > - rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; > - rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; > - rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; > - cagf = intel_rps_read_actual_frequency(rps); > - > - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); > - > - if (GRAPHICS_VER(dev_priv) >= 11) { > - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); > - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); > - /* > - * The equivalent to the PM ISR & IIR cannot be read > - * without affecting the current state of the system > - */ > - pm_isr = 0; > - pm_iir = 0; > - } else if (GRAPHICS_VER(dev_priv) >= 8) { > - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2)); > - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2)); > - pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2)); > - pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2)); > - } else { > - pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER); > - pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR); > - pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR); > - pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); > - } > - pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK); > - > - seq_printf(m, "Video Turbo Mode: %s\n", > - yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); > - seq_printf(m, "HW control enabled: %s\n", > - yesno(rpmodectl & GEN6_RP_ENABLE)); > - seq_printf(m, "SW control enabled: %s\n", > - yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > - GEN6_RP_MEDIA_SW_MODE)); > - > - seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", > - pm_ier, pm_imr, pm_mask); > - if (GRAPHICS_VER(dev_priv) <= 10) > - seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", > - pm_isr, pm_iir); > - seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", > - rps->pm_intrmsk_mbz); > - seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); > - seq_printf(m, "Render p-state ratio: %d\n", > - (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); > - seq_printf(m, "Render p-state VID: %d\n", > - gt_perf_status & 0xff); > - seq_printf(m, "Render p-state limit: %d\n", > - rp_state_limits & 0xff); > - seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); > - seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); > - seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); > - seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); > - seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); > - seq_printf(m, "CAGF: %dMHz\n", cagf); > - seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", > - rpupei, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); > - seq_printf(m, "RP CUR UP: %d (%lldun)\n", > - rpcurup, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); > - seq_printf(m, "RP PREV UP: %d (%lldns)\n", > - rpprevup, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); > - seq_printf(m, "Up threshold: %d%%\n", > - rps->power.up_threshold); > - > - seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", > - rpdownei, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, > - rpdownei)); > - seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", > - rpcurdown, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, > - rpcurdown)); > - seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", > - rpprevdown, > - intel_gt_pm_interval_to_ns(&dev_priv->gt, > - rpprevdown)); > - seq_printf(m, "Down threshold: %d%%\n", > - rps->power.down_threshold); > - > - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : > - rp_state_cap >> 16) & 0xff; > - max_freq *= (IS_GEN9_BC(dev_priv) || > - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", > - intel_gpu_freq(rps, max_freq)); > - > - max_freq = (rp_state_cap & 0xff00) >> 8; > - max_freq *= (IS_GEN9_BC(dev_priv) || > - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", > - intel_gpu_freq(rps, max_freq)); > - > - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : > - rp_state_cap >> 0) & 0xff; > - max_freq *= (IS_GEN9_BC(dev_priv) || > - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1); > - seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", > - intel_gpu_freq(rps, max_freq)); > - seq_printf(m, "Max overclocked frequency: %dMHz\n", > - intel_gpu_freq(rps, rps->max_freq)); > - > - seq_printf(m, "Current freq: %d MHz\n", > - intel_gpu_freq(rps, rps->cur_freq)); > - seq_printf(m, "Actual freq: %d MHz\n", cagf); > - seq_printf(m, "Idle freq: %d MHz\n", > - intel_gpu_freq(rps, rps->idle_freq)); > - seq_printf(m, "Min freq: %d MHz\n", > - intel_gpu_freq(rps, rps->min_freq)); > - seq_printf(m, "Boost freq: %d MHz\n", > - intel_gpu_freq(rps, rps->boost_freq)); > - seq_printf(m, "Max freq: %d MHz\n", > - intel_gpu_freq(rps, rps->max_freq)); > - seq_printf(m, > - "efficient (RPe) frequency: %d MHz\n", > - intel_gpu_freq(rps, rps->efficient_freq)); > - } else { > - seq_puts(m, "no P-state info available\n"); > - } > + struct drm_i915_private *i915 = node_to_i915(m->private); > + struct intel_gt *gt = &i915->gt; > + struct drm_printer p = drm_seq_file_printer(m); > > - seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); > - seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); > - seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); > + debugfs_gt_pm_frequency_dump(gt, &p); > > - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); > return 0; > } -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs 2021-09-08 8:54 ` [Intel-gfx] [PATCH] " Jani Nikula @ 2021-09-08 14:14 ` Lucas De Marchi 2021-09-08 14:57 ` Lucas De Marchi 0 siblings, 1 reply; 7+ messages in thread From: Lucas De Marchi @ 2021-09-08 14:14 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Andi Shyti, Chris Wilson, Joonas Lahtinen On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote: >On Tue, 07 Sep 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >> Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a >> gt aware debugfs") says it was moving debug files to gt/, the >> i915_frequency_info file was left behind and its implementation copied >> into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several >> patches having to change both places to keep them in sync (and some >> patches failing to do so). The initial idea was to remove i915_frequency_info, >> but there are user space tools using it. From a quick code search there >> are other scripts and test tools besides igt, so it's not simply >> updating igt to get rid of the older file. >> >> Here we export a function using drm_printer as parameter and make >> both show() implementations to call this same function. Aside from a few >> variable name differences, for i915_frequency_info this brings a few >> lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP >> DOWN THRESHOLD and RP DOWN EI. These came in as part of >> commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to >> determine clk frequencies"), which didn't change both places. >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> --- >> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++++++------- >> drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 2 + >> drivers/gpu/drm/i915/i915_debugfs.c | 227 +----------------------- >> 3 files changed, 74 insertions(+), 282 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >> index f6733f279890..6a27c011d0ff 100644 >> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >> @@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused) >> } >> DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc); >> >> -static int frequency_show(struct seq_file *m, void *unused) >> +void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) > >The debugfs prefix belongs to debugfs, and I don't think we should have >non-static functions with that prefix. > >I know it's in line with what's currently in the file, and I've >complained about it before, but apparently that hasn't been enough. I was surprised by the prefix too. intel_gt_pm_debugfs.[hc] - would that be better or do you have another suggestion? thanks Lucas De Marchi ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs 2021-09-08 14:14 ` Lucas De Marchi @ 2021-09-08 14:57 ` Lucas De Marchi 0 siblings, 0 replies; 7+ messages in thread From: Lucas De Marchi @ 2021-09-08 14:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Andi Shyti, Chris Wilson, Joonas Lahtinen On Wed, Sep 08, 2021 at 07:14:00AM -0700, Lucas De Marchi wrote: >On Wed, Sep 08, 2021 at 11:54:40AM +0300, Jani Nikula wrote: >>On Tue, 07 Sep 2021, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>Although commit 9dd4b065446a ("drm/i915/gt: Move pm debug files into a >>>gt aware debugfs") says it was moving debug files to gt/, the >>>i915_frequency_info file was left behind and its implementation copied >>>into drivers/gpu/drm/i915/gt/debugfs_gt_pm.c. Over time we had several >>>patches having to change both places to keep them in sync (and some >>>patches failing to do so). The initial idea was to remove i915_frequency_info, >>>but there are user space tools using it. From a quick code search there >>>are other scripts and test tools besides igt, so it's not simply >>>updating igt to get rid of the older file. >>> >>>Here we export a function using drm_printer as parameter and make >>>both show() implementations to call this same function. Aside from a few >>>variable name differences, for i915_frequency_info this brings a few >>>lines that were not previously printed: RP UP EI, RP UP THRESHOLD, RP >>>DOWN THRESHOLD and RP DOWN EI. These came in as part of >>>commit 9c878557b1eb ("drm/i915/gt: Use the RPM config register to >>>determine clk frequencies"), which didn't change both places. >>> >>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >>>--- >>> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 127 ++++++------- >>> drivers/gpu/drm/i915/gt/debugfs_gt_pm.h | 2 + >>> drivers/gpu/drm/i915/i915_debugfs.c | 227 +----------------------- >>> 3 files changed, 74 insertions(+), 282 deletions(-) >>> >>>diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >>>index f6733f279890..6a27c011d0ff 100644 >>>--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >>>+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c >>>@@ -240,9 +240,8 @@ static int drpc_show(struct seq_file *m, void *unused) >>> } >>> DEFINE_GT_DEBUGFS_ATTRIBUTE(drpc); >>> >>>-static int frequency_show(struct seq_file *m, void *unused) >>>+void debugfs_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) >> >>The debugfs prefix belongs to debugfs, and I don't think we should have >>non-static functions with that prefix. >> >>I know it's in line with what's currently in the file, and I've >>complained about it before, but apparently that hasn't been enough. > >I was surprised by the prefix too. > >intel_gt_pm_debugfs.[hc] - would that be better or do you have another >suggestion? Something like the below: renamed: drivers/gpu/drm/i915/gt/debugfs_gt.c -> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c renamed: drivers/gpu/drm/i915/gt/debugfs_gt.h -> drivers/gpu/drm/i915/gt/intel_gt_debugfs.h renamed: drivers/gpu/drm/i915/gt/debugfs_engines.c -> drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.c renamed: drivers/gpu/drm/i915/gt/debugfs_engines.h -> drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h renamed: drivers/gpu/drm/i915/gt/debugfs_gt_pm.c -> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c renamed: drivers/gpu/drm/i915/gt/debugfs_gt_pm.h -> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h and then rename the functions/macros in these files to follow th filename Lucas De Marchi > >thanks >Lucas De Marchi ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-09-08 14:57 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-07 21:39 [Intel-gfx] [PATCH] drm/i915: deduplicate frequency dump on debugfs Lucas De Marchi 2021-09-07 22:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2021-09-07 23:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-08 3:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-09-08 8:54 ` [Intel-gfx] [PATCH] " Jani Nikula 2021-09-08 14:14 ` Lucas De Marchi 2021-09-08 14:57 ` Lucas De Marchi
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