* [PATCH v3] drm/amd/display: Only define DP 2.0 symbols if not already defined
@ 2021-09-28 20:37 ` Harry Wentland
0 siblings, 0 replies; 6+ messages in thread
From: Harry Wentland @ 2021-09-28 20:37 UTC (permalink / raw)
To: alexander.deucher, amd-gfx, jerry.zuo
Cc: jani.nikula, Sunpeng.Li, nathan, intel-gfx, dri-devel,
ville.syrjala, manasi.d.navare, christian.koenig, Xinhui.Pan,
sfr, linux-next, airlied, daniel.vetter, Harry Wentland,
Fangzhi Zuo
[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
^
1 error generated.
[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.
We also ensure drm_dp_helper.h is included before dc_dp_types.h.
v3: Ensure drm_dp_helper.h is included before dc_dp_types.h
v2: Add one missing endif
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 54 ++++++++++++++++++--
drivers/gpu/drm/amd/display/dc/os_types.h | 1 +
2 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..9de86ff5ef1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -860,28 +860,72 @@ struct psr_caps {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
+#endif
+#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
+#endif
+#ifndef DP_FEC_CAPABILITY_1
#define DP_FEC_CAPABILITY_1 0x091
+#endif
+#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+#endif
+#ifndef DP_DSC_CONFIGURATION
#define DP_DSC_CONFIGURATION 0x161
+#endif
+#ifndef DP_PHY_SQUARE_PATTERN
#define DP_PHY_SQUARE_PATTERN 0x249
+#endif
+#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
+#endif
+#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
+#endif
+#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
-# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
-# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
-# define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
+#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+#endif
+#ifndef DP_DSC_DECODER_COUNT_MASK
+#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+#endif
+#ifndef DP_DSC_DECODER_COUNT_SHIFT
+#define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
+#endif
+#ifndef DP_PHY_REPEATER_128b_132b_RATES
#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
+#endif
+#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
+#endif
/* TODO - Use DRM header to replace above once available */
union dp_main_line_channel_coding_cap {
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index f50cae252de4..34efb708ea12 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -35,6 +35,7 @@
#include <asm/byteorder.h>
#include <drm/drm_print.h>
+#include <drm/drm_dp_helper.h>
#include "cgs_common.h"
--
2.33.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH v3] drm/amd/display: Only define DP 2.0 symbols if not already defined
@ 2021-09-28 20:37 ` Harry Wentland
0 siblings, 0 replies; 6+ messages in thread
From: Harry Wentland @ 2021-09-28 20:37 UTC (permalink / raw)
To: alexander.deucher, amd-gfx, jerry.zuo
Cc: jani.nikula, Sunpeng.Li, nathan, intel-gfx, dri-devel,
ville.syrjala, manasi.d.navare, christian.koenig, Xinhui.Pan,
sfr, linux-next, airlied, daniel.vetter, Harry Wentland,
Fangzhi Zuo
[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
^
1 error generated.
[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.
We also ensure drm_dp_helper.h is included before dc_dp_types.h.
v3: Ensure drm_dp_helper.h is included before dc_dp_types.h
v2: Add one missing endif
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 54 ++++++++++++++++++--
drivers/gpu/drm/amd/display/dc/os_types.h | 1 +
2 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..9de86ff5ef1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -860,28 +860,72 @@ struct psr_caps {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
+#endif
+#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
+#endif
+#ifndef DP_FEC_CAPABILITY_1
#define DP_FEC_CAPABILITY_1 0x091
+#endif
+#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+#endif
+#ifndef DP_DSC_CONFIGURATION
#define DP_DSC_CONFIGURATION 0x161
+#endif
+#ifndef DP_PHY_SQUARE_PATTERN
#define DP_PHY_SQUARE_PATTERN 0x249
+#endif
+#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
+#endif
+#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
+#endif
+#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
-# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
-# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
-# define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
+#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+#endif
+#ifndef DP_DSC_DECODER_COUNT_MASK
+#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+#endif
+#ifndef DP_DSC_DECODER_COUNT_SHIFT
+#define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
+#endif
+#ifndef DP_PHY_REPEATER_128b_132b_RATES
#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
+#endif
+#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
+#endif
/* TODO - Use DRM header to replace above once available */
union dp_main_line_channel_coding_cap {
diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index f50cae252de4..34efb708ea12 100644
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -35,6 +35,7 @@
#include <asm/byteorder.h>
#include <drm/drm_print.h>
+#include <drm/drm_dp_helper.h>
#include "cgs_common.h"
--
2.33.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
2021-09-28 20:37 ` [Intel-gfx] " Harry Wentland
(?)
@ 2021-09-28 21:19 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-09-28 21:19 UTC (permalink / raw)
To: Harry Wentland; +Cc: intel-gfx
== Series Details ==
Series: drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
URL : https://patchwork.freedesktop.org/series/95164/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5ad853d0cb0d drm/amd/display: Only define DP 2.0 symbols if not already defined
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
total: 0 errors, 1 warnings, 0 checks, 84 lines checked
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
2021-09-28 20:37 ` [Intel-gfx] " Harry Wentland
(?)
(?)
@ 2021-09-28 21:22 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-09-28 21:22 UTC (permalink / raw)
To: Harry Wentland; +Cc: intel-gfx
== Series Details ==
Series: drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
URL : https://patchwork.freedesktop.org/series/95164/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
- #define DP_MAIN_LINK_CHANNEL_CODIN
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
2021-09-28 20:37 ` [Intel-gfx] " Harry Wentland
` (2 preceding siblings ...)
(?)
@ 2021-09-28 21:48 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-09-28 21:48 UTC (permalink / raw)
To: Harry Wentland; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5093 bytes --]
== Series Details ==
Series: drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
URL : https://patchwork.freedesktop.org/series/95164/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10655 -> Patchwork_21180
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/index.html
Known issues
------------
Here are the changes found in Patchwork_21180 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7500u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-7500u/igt@amdgpu/amd_basic@cs-sdma.html
* igt@amdgpu/amd_basic@semaphore:
- fi-bsw-nick: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-bsw-nick/igt@amdgpu/amd_basic@semaphore.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-7500u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-7500u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick: [DMESG-FAIL][9] ([i915#2927] / [i915#3428]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [FAIL][11] ([i915#1161]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
#### Warnings ####
* igt@kms_chamelium@vga-hpd-fast:
- fi-kbl-7500u: [{ABORT}][13] ([i915#1814]) -> [SKIP][14] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/fi-kbl-7500u/igt@kms_chamelium@vga-hpd-fast.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (45 -> 37)
------------------------------
Additional (1): fi-kbl-soraka
Missing (9): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 bat-jsl-2 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10655 -> Patchwork_21180
CI-20190529: 20190529
CI_DRM_10655: 88d6ecae86a7bb32e8bf2bd233f7f9f9c8bd7abc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6226: 18278534c085c35adcf62f158a8d5356e5496f8d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21180: 5ad853d0cb0d51c38ff1ac5936876e3158fe89ee @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5ad853d0cb0d drm/amd/display: Only define DP 2.0 symbols if not already defined
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/index.html
[-- Attachment #2: Type: text/html, Size: 6483 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
2021-09-28 20:37 ` [Intel-gfx] " Harry Wentland
` (3 preceding siblings ...)
(?)
@ 2021-09-29 0:07 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2021-09-29 0:07 UTC (permalink / raw)
To: Harry Wentland; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30296 bytes --]
== Series Details ==
Series: drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2)
URL : https://patchwork.freedesktop.org/series/95164/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10655_full -> Patchwork_21180_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21180_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21180_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21180_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@syncobj-channel:
- shard-skl: [PASS][1] -> [WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl5/igt@gem_exec_fence@syncobj-channel.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl3/igt@gem_exec_fence@syncobj-channel.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
Known issues
------------
Here are the changes found in Patchwork_21180_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][5] ([fdo#111827])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@feature_discovery@chamelium.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][6] ([fdo#109314])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([i915#3778])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb6/igt@gem_exec_endless@dispatch@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb3/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_params@no-bsd:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@gem_exec_params@no-bsd.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#112283])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@gem_exec_params@secure-non-root.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@gem_pwrite@basic-exhaustion.html
- shard-apl: NOTRUN -> [WARN][20] ([i915#2658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][21] ([i915#3002])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-snb7/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#3297])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@gem_userptr_blits@unsync-overlap.html
* igt@gen7_exec_parse@basic-allocation:
- shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271]) +33 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglb: NOTRUN -> [SKIP][24] ([i915#2856])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#110892])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: NOTRUN -> [DMESG-WARN][26] ([i915#180])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl6/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110725] / [fdo#111614])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111614])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb2/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#110723])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#2705])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb6/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +8 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +10 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3689] / [i915#3886])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3689]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109284] / [fdo#111827]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +13 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl7/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +15 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_color@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#1149])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_color@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#109284] / [fdo#111827]) +5 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][46] ([i915#1319])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#3116]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb2/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111828])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb2/igt@kms_content_protection@mei_interface.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][49] ([i915#2105])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl1/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [PASS][51] -> [INCOMPLETE][52] ([i915#2411] / [i915#2828] / [i915#456])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [FAIL][56] ([i915#79])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109274]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][58] ([i915#180])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [PASS][59] -> [DMESG-WARN][60] ([i915#1982]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl9/igt@kms_flip@flip-vs-suspend@a-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +106 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109280]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111825]) +21 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-iclb: [PASS][64] -> [FAIL][65] ([i915#2546])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][66] -> [FAIL][67] ([i915#1188]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-glk: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109278]) +4 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#3536]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb6/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_plane_lowres@pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][74] ([fdo#112054]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_plane_lowres@pipe-d-tiling-yf.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#1836])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#658])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#2920])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#658])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][82] ([i915#132] / [i915#3467])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][83] -> [SKIP][84] ([fdo#109441]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][85] ([fdo#111615]) +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][86] -> [DMESG-WARN][87] ([i915#180] / [i915#295])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][88] -> [DMESG-WARN][89] ([i915#180]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-tglb: [PASS][90] -> [INCOMPLETE][91] ([i915#2828] / [i915#456])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2437])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2437])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271]) +209 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_nv_pcopy@test2:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271]) +183 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@prime_nv_pcopy@test2.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#109291])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@prime_nv_pcopy@test3_2.html
* igt@prime_vgem@basic-userptr:
- shard-tglb: NOTRUN -> [SKIP][97] ([i915#3301])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@fence-read-hang:
- shard-tglb: NOTRUN -> [SKIP][98] ([fdo#109295])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb2/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@create:
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2994])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk4/igt@sysfs_clients@create.html
* igt@sysfs_clients@recycle:
- shard-apl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl7/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@sema-25:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#2994]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2994]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][103] ([i915#2842]) -> [PASS][104] +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk3/igt@gem_exec_fair@basic-none@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][105] ([i915#2842]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][107] ([i915#2842] / [i915#3468]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][109] ([i915#2842]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_parallel@fds@vecs0:
- shard-iclb: [INCOMPLETE][111] ([i915#1895]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb7/igt@gem_exec_parallel@fds@vecs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb4/igt@gem_exec_parallel@fds@vecs0.html
* igt@gem_mmap_offset@bad-flags:
- shard-glk: [DMESG-WARN][113] ([i915#118] / [i915#95]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-glk5/igt@gem_mmap_offset@bad-flags.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-glk3/igt@gem_mmap_offset@bad-flags.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][115] ([i915#454]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [FAIL][117] ([i915#454]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl4/igt@i915_pm_dc@dc6-psr.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [DMESG-WARN][119] ([i915#1982]) -> [PASS][120] +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl6/igt@kms_color@pipe-c-ctm-0-25.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl6/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [INCOMPLETE][121] ([i915#2411] / [i915#4173] / [i915#456]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][123] ([i915#2122]) -> [PASS][124] +2 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][125] ([i915#3701]) -> [PASS][126] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128] +6 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][129] ([i915#1188]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-skl4/igt@kms_hdr@bpc-switch.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][131] ([i915#180]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10655/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][133] ([fdo#108145] / [i915#265]) -> [PASS][134]
[133]: https://intel-gfx
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21180/index.html
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end of thread, other threads:[~2021-09-29 0:07 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-28 20:37 [PATCH v3] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
2021-09-28 20:37 ` [Intel-gfx] " Harry Wentland
2021-09-28 21:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/amd/display: Only define DP 2.0 symbols if not already defined (rev2) Patchwork
2021-09-28 21:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-28 21:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-29 0:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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