* [Intel-gfx] [PATCH 2/4] drm/i915: Call intel_ddi_init_dp_buf_reg() earlier
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
@ 2021-09-30 13:43 ` Ville Syrjala
2021-09-30 15:51 ` Imre Deak
2021-09-30 13:43 ` [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code Ville Syrjala
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-09-30 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Imre Deak
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I want intel_dp->DP to be fully populated by the time the
initial vswing programming happens. To that end move the
intel_ddi_init_dp_buf_reg() call to an earlier spot.
Additionally we don't want intel_ddi_init_dp_buf_reg() to
set DDI_BUF_CTL_ENABLE since the port should only get enabled
at the start of link training (see intel_ddi_prepare_link_retrain()).
So any earlier write to the register should not set the enable bit.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 44 +++++++++++-------------
1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 51d07e9af9f3..65e59f16879d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -282,9 +282,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
intel_dp->DP = dig_port->saved_port_bits |
- DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
- intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
+ DDI_PORT_WIDTH(crtc_state->lane_count) |
+ DDI_BUF_TRANS_SELECT(0);
if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
@@ -2360,6 +2361,12 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count);
+ /*
+ * We only configure what the register value will be here. Actual
+ * enabling happens during link training farther down.
+ */
+ intel_ddi_init_dp_buf_reg(encoder, crtc_state);
+
/*
* 1. Enable Power Wells
*
@@ -2416,16 +2423,6 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 5.e Configure voltage swing and related IO settings */
intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
- /*
- * 5.f Configure and enable DDI_BUF_CTL
- * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
- * after 1200 us.
- *
- * We only configure what the register value will be here. Actual
- * enabling happens during link training farther down.
- */
- intel_ddi_init_dp_buf_reg(encoder, crtc_state);
-
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
@@ -2473,6 +2470,12 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
+ /*
+ * We only configure what the register value will be here. Actual
+ * enabling happens during link training farther down.
+ */
+ intel_ddi_init_dp_buf_reg(encoder, crtc_state);
+
/*
* 1. Enable Power Wells
*
@@ -2554,16 +2557,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
*/
intel_ddi_mso_configure(crtc_state);
- /*
- * 7.g Configure and enable DDI_BUF_CTL
- * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
- * after 500 us.
- *
- * We only configure what the register value will be here. Actual
- * enabling happens during link training farther down.
- */
- intel_ddi_init_dp_buf_reg(encoder, crtc_state);
-
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
@@ -2620,6 +2613,12 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
crtc_state->port_clock,
crtc_state->lane_count);
+ /*
+ * We only configure what the register value will be here. Actual
+ * enabling happens during link training farther down.
+ */
+ intel_ddi_init_dp_buf_reg(encoder, crtc_state);
+
intel_pps_on(intel_dp);
intel_ddi_enable_clock(encoder, crtc_state);
@@ -2641,7 +2640,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_power_up_lanes(encoder, crtc_state);
- intel_ddi_init_dp_buf_reg(encoder, crtc_state);
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Call intel_ddi_init_dp_buf_reg() earlier
2021-09-30 13:43 ` [Intel-gfx] [PATCH 2/4] drm/i915: Call intel_ddi_init_dp_buf_reg() earlier Ville Syrjala
@ 2021-09-30 15:51 ` Imre Deak
0 siblings, 0 replies; 13+ messages in thread
From: Imre Deak @ 2021-09-30 15:51 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 04:43:08PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I want intel_dp->DP to be fully populated by the time the
> initial vswing programming happens. To that end move the
> intel_ddi_init_dp_buf_reg() call to an earlier spot.
>
> Additionally we don't want intel_ddi_init_dp_buf_reg() to
> set DDI_BUF_CTL_ENABLE since the port should only get enabled
> at the start of link training (see intel_ddi_prepare_link_retrain()).
> So any earlier write to the register should not set the enable bit.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 44 +++++++++++-------------
> 1 file changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 51d07e9af9f3..65e59f16879d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -282,9 +282,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> + /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> intel_dp->DP = dig_port->saved_port_bits |
> - DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
> - intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
> + DDI_PORT_WIDTH(crtc_state->lane_count) |
> + DDI_BUF_TRANS_SELECT(0);
>
> if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> @@ -2360,6 +2361,12 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> crtc_state->lane_count);
>
> + /*
> + * We only configure what the register value will be here. Actual
> + * enabling happens during link training farther down.
> + */
> + intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> +
> /*
> * 1. Enable Power Wells
> *
> @@ -2416,16 +2423,6 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
> /* 5.e Configure voltage swing and related IO settings */
> intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
>
> - /*
> - * 5.f Configure and enable DDI_BUF_CTL
> - * 5.g Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
> - * after 1200 us.
> - *
> - * We only configure what the register value will be here. Actual
> - * enabling happens during link training farther down.
> - */
> - intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> -
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
>
> @@ -2473,6 +2470,12 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> crtc_state->port_clock,
> crtc_state->lane_count);
>
> + /*
> + * We only configure what the register value will be here. Actual
> + * enabling happens during link training farther down.
> + */
> + intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> +
> /*
> * 1. Enable Power Wells
> *
> @@ -2554,16 +2557,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> */
> intel_ddi_mso_configure(crtc_state);
>
> - /*
> - * 7.g Configure and enable DDI_BUF_CTL
> - * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
> - * after 500 us.
> - *
> - * We only configure what the register value will be here. Actual
> - * enabling happens during link training farther down.
> - */
> - intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> -
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
>
> @@ -2620,6 +2613,12 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
> crtc_state->port_clock,
> crtc_state->lane_count);
>
> + /*
> + * We only configure what the register value will be here. Actual
> + * enabling happens during link training farther down.
> + */
> + intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> +
> intel_pps_on(intel_dp);
>
> intel_ddi_enable_clock(encoder, crtc_state);
> @@ -2641,7 +2640,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
>
> intel_ddi_power_up_lanes(encoder, crtc_state);
>
> - intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
2021-09-30 13:43 ` [Intel-gfx] [PATCH 2/4] drm/i915: Call intel_ddi_init_dp_buf_reg() earlier Ville Syrjala
@ 2021-09-30 13:43 ` Ville Syrjala
2021-09-30 16:09 ` Imre Deak
2021-09-30 13:43 ` [Intel-gfx] [PATCH 4/4] drm/i915: Nuke local copies/pointers of intel_dp->DP Ville Syrjala
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-09-30 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Imre Deak
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Setting DP_PORT_EN in intel_dp->DP is already handled by
intel_dp_enable_port() so there is no point in setting it also
from the link training code.
For DDI platforms a bit with that name doesn't even exist. The
counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
so there was no harm in doing this from the platform independent
code as well. But it's just confusing when platform independent
code sets platform specific bits in intel_dp->DP. Just get rid
of it.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 449499a5c4c1..053ed9302cda 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -499,8 +499,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
- intel_dp->DP |= DP_PORT_EN;
-
return true;
}
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code
2021-09-30 13:43 ` [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code Ville Syrjala
@ 2021-09-30 16:09 ` Imre Deak
2021-09-30 16:16 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Imre Deak @ 2021-09-30 16:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 04:43:09PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Setting DP_PORT_EN in intel_dp->DP is already handled by
> intel_dp_enable_port() so there is no point in setting it also
> from the link training code.
>
> For DDI platforms a bit with that name doesn't even exist. The
> counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
> intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
> so there was no harm in doing this from the platform independent
> code as well. But it's just confusing when platform independent
> code sets platform specific bits in intel_dp->DP. Just get rid
> of it.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak.intel.com>
On pre-DDI platforms intel_dp_enable_port() may not be called before
short HPD/link-retraining, but the init/resume time HW readout will
set DP_PORT_EN for that case.
> ---
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 449499a5c4c1..053ed9302cda 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -499,8 +499,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
>
> - intel_dp->DP |= DP_PORT_EN;
> -
> return true;
> }
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code
2021-09-30 16:09 ` Imre Deak
@ 2021-09-30 16:16 ` Ville Syrjälä
2021-09-30 16:19 ` Imre Deak
0 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjälä @ 2021-09-30 16:16 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 07:09:03PM +0300, Imre Deak wrote:
> On Thu, Sep 30, 2021 at 04:43:09PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Setting DP_PORT_EN in intel_dp->DP is already handled by
> > intel_dp_enable_port() so there is no point in setting it also
> > from the link training code.
> >
> > For DDI platforms a bit with that name doesn't even exist. The
> > counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
> > intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
> > so there was no harm in doing this from the platform independent
> > code as well. But it's just confusing when platform independent
> > code sets platform specific bits in intel_dp->DP. Just get rid
> > of it.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Imre Deak <imre.deak.intel.com>
>
> On pre-DDI platforms intel_dp_enable_port() may not be called before
> short HPD/link-retraining, but the init/resume time HW readout will
> set DP_PORT_EN for that case.
I actually wonder what happens on DDI platforms. We don't do the resume
readout there AFAICS, so if link retraining happens before any modesets
are we just screwed atm?
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 --
> > 1 file changed, 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 449499a5c4c1..053ed9302cda 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -499,8 +499,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> > DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> >
> > - intel_dp->DP |= DP_PORT_EN;
> > -
> > return true;
> > }
> >
> > --
> > 2.32.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code
2021-09-30 16:16 ` Ville Syrjälä
@ 2021-09-30 16:19 ` Imre Deak
2021-09-30 16:21 ` Imre Deak
0 siblings, 1 reply; 13+ messages in thread
From: Imre Deak @ 2021-09-30 16:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 07:16:10PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 30, 2021 at 07:09:03PM +0300, Imre Deak wrote:
> > On Thu, Sep 30, 2021 at 04:43:09PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Setting DP_PORT_EN in intel_dp->DP is already handled by
> > > intel_dp_enable_port() so there is no point in setting it also
> > > from the link training code.
> > >
> > > For DDI platforms a bit with that name doesn't even exist. The
> > > counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
> > > intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
> > > so there was no harm in doing this from the platform independent
> > > code as well. But it's just confusing when platform independent
> > > code sets platform specific bits in intel_dp->DP. Just get rid
> > > of it.
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reviewed-by: Imre Deak <imre.deak.intel.com>
> >
> > On pre-DDI platforms intel_dp_enable_port() may not be called before
> > short HPD/link-retraining, but the init/resume time HW readout will
> > set DP_PORT_EN for that case.
>
> I actually wonder what happens on DDI platforms. We don't do the resume
> readout there AFAICS, so if link retraining happens before any modesets
> are we just screwed atm?
Yea.
>
> >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 --
> > > 1 file changed, 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > index 449499a5c4c1..053ed9302cda 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > @@ -499,8 +499,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> > > DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > > drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> > >
> > > - intel_dp->DP |= DP_PORT_EN;
> > > -
> > > return true;
> > > }
> > >
> > > --
> > > 2.32.0
> > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code
2021-09-30 16:19 ` Imre Deak
@ 2021-09-30 16:21 ` Imre Deak
0 siblings, 0 replies; 13+ messages in thread
From: Imre Deak @ 2021-09-30 16:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 07:19:06PM +0300, Imre Deak wrote:
> On Thu, Sep 30, 2021 at 07:16:10PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 30, 2021 at 07:09:03PM +0300, Imre Deak wrote:
> > > On Thu, Sep 30, 2021 at 04:43:09PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Setting DP_PORT_EN in intel_dp->DP is already handled by
> > > > intel_dp_enable_port() so there is no point in setting it also
> > > > from the link training code.
> > > >
> > > > For DDI platforms a bit with that name doesn't even exist. The
> > > > counterpart is DDI_BUF_CTL_ENABLE, which is already set up by
> > > > intel_ddi_prepare_link_retrain(). Fortunately it is the same bit
> > > > so there was no harm in doing this from the platform independent
> > > > code as well. But it's just confusing when platform independent
> > > > code sets platform specific bits in intel_dp->DP. Just get rid
> > > > of it.
> > > >
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Reviewed-by: Imre Deak <imre.deak.intel.com>
> > >
> > > On pre-DDI platforms intel_dp_enable_port() may not be called before
> > > short HPD/link-retraining, but the init/resume time HW readout will
> > > set DP_PORT_EN for that case.
> >
> > I actually wonder what happens on DDI platforms. We don't do the resume
> > readout there AFAICS, so if link retraining happens before any modesets
> > are we just screwed atm?
>
> Yea.
It's unlikely to cause a problem though, since resume mostly happens
with disabled outputs?
>
> >
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 --
> > > > 1 file changed, 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > index 449499a5c4c1..053ed9302cda 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > > > @@ -499,8 +499,6 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
> > > > DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> > > > drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
> > > >
> > > > - intel_dp->DP |= DP_PORT_EN;
> > > > -
> > > > return true;
> > > > }
> > > >
> > > > --
> > > > 2.32.0
> > > >
> >
> > --
> > Ville Syrjälä
> > Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915: Nuke local copies/pointers of intel_dp->DP
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
2021-09-30 13:43 ` [Intel-gfx] [PATCH 2/4] drm/i915: Call intel_ddi_init_dp_buf_reg() earlier Ville Syrjala
2021-09-30 13:43 ` [Intel-gfx] [PATCH 3/4] drm/i915: Remove DP_PORT_EN stuff from link training code Ville Syrjala
@ 2021-09-30 13:43 ` Ville Syrjala
2021-09-30 16:15 ` Imre Deak
2021-09-30 15:25 ` [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Imre Deak
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-09-30 13:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Imre Deak
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the local copies and pointers of intel_dp->DP and
instead just poke at it directly. Makes it much easier to see
where it actually gets used/modified.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 45 ++++++++++++---------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 8e0620ae2ed1..69a2e5ad2317 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -426,7 +426,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum port port = encoder->port;
- u32 DP = intel_dp->DP;
if (drm_WARN_ON(&dev_priv->drm,
(intel_de_read(dev_priv, intel_dp->output_reg) &
@@ -437,17 +436,17 @@ intel_dp_link_down(struct intel_encoder *encoder,
if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
- DP &= ~DP_LINK_TRAIN_MASK_CPT;
- DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
+ intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
- DP &= ~DP_LINK_TRAIN_MASK;
- DP |= DP_LINK_TRAIN_PAT_IDLE;
+ intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
}
- intel_de_write(dev_priv, intel_dp->output_reg, DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
- DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
- intel_de_write(dev_priv, intel_dp->output_reg, DP);
+ intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
/*
@@ -464,14 +463,14 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
/* always enable with pattern 1 (as per spec) */
- DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
- DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
+ intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
+ intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
DP_LINK_TRAIN_PAT_1;
- intel_de_write(dev_priv, intel_dp->output_reg, DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
- DP &= ~DP_PORT_EN;
- intel_de_write(dev_priv, intel_dp->output_reg, DP);
+ intel_dp->DP &= ~DP_PORT_EN;
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
@@ -481,8 +480,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
msleep(intel_dp->pps.panel_power_down_delay);
- intel_dp->DP = DP;
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_wakeref_t wakeref;
@@ -582,19 +579,18 @@ cpt_set_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 *DP = &intel_dp->DP;
- *DP &= ~DP_LINK_TRAIN_MASK_CPT;
+ intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
case DP_TRAINING_PATTERN_DISABLE:
- *DP |= DP_LINK_TRAIN_OFF_CPT;
+ intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
break;
case DP_TRAINING_PATTERN_1:
- *DP |= DP_LINK_TRAIN_PAT_1_CPT;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
break;
case DP_TRAINING_PATTERN_2:
- *DP |= DP_LINK_TRAIN_PAT_2_CPT;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
break;
default:
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
@@ -611,19 +607,18 @@ g4x_set_link_train(struct intel_dp *intel_dp,
u8 dp_train_pat)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 *DP = &intel_dp->DP;
- *DP &= ~DP_LINK_TRAIN_MASK;
+ intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
case DP_TRAINING_PATTERN_DISABLE:
- *DP |= DP_LINK_TRAIN_OFF;
+ intel_dp->DP |= DP_LINK_TRAIN_OFF;
break;
case DP_TRAINING_PATTERN_1:
- *DP |= DP_LINK_TRAIN_PAT_1;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
break;
case DP_TRAINING_PATTERN_2:
- *DP |= DP_LINK_TRAIN_PAT_2;
+ intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
break;
default:
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Intel-gfx] [PATCH 4/4] drm/i915: Nuke local copies/pointers of intel_dp->DP
2021-09-30 13:43 ` [Intel-gfx] [PATCH 4/4] drm/i915: Nuke local copies/pointers of intel_dp->DP Ville Syrjala
@ 2021-09-30 16:15 ` Imre Deak
0 siblings, 0 replies; 13+ messages in thread
From: Imre Deak @ 2021-09-30 16:15 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 04:43:10PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Get rid of the local copies and pointers of intel_dp->DP and
> instead just poke at it directly. Makes it much easier to see
> where it actually gets used/modified.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 45 ++++++++++++---------------
> 1 file changed, 20 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 8e0620ae2ed1..69a2e5ad2317 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -426,7 +426,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> enum port port = encoder->port;
> - u32 DP = intel_dp->DP;
>
> if (drm_WARN_ON(&dev_priv->drm,
> (intel_de_read(dev_priv, intel_dp->output_reg) &
> @@ -437,17 +436,17 @@ intel_dp_link_down(struct intel_encoder *encoder,
>
> if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> - DP &= ~DP_LINK_TRAIN_MASK_CPT;
> - DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> + intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> } else {
> - DP &= ~DP_LINK_TRAIN_MASK;
> - DP |= DP_LINK_TRAIN_PAT_IDLE;
> + intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> }
> - intel_de_write(dev_priv, intel_dp->output_reg, DP);
> + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
> intel_de_posting_read(dev_priv, intel_dp->output_reg);
>
> - DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
> - intel_de_write(dev_priv, intel_dp->output_reg, DP);
> + intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
> + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
> intel_de_posting_read(dev_priv, intel_dp->output_reg);
>
> /*
> @@ -464,14 +463,14 @@ intel_dp_link_down(struct intel_encoder *encoder,
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
>
> /* always enable with pattern 1 (as per spec) */
> - DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
> - DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
> + intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
> + intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
> DP_LINK_TRAIN_PAT_1;
> - intel_de_write(dev_priv, intel_dp->output_reg, DP);
> + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
> intel_de_posting_read(dev_priv, intel_dp->output_reg);
>
> - DP &= ~DP_PORT_EN;
> - intel_de_write(dev_priv, intel_dp->output_reg, DP);
> + intel_dp->DP &= ~DP_PORT_EN;
> + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
> intel_de_posting_read(dev_priv, intel_dp->output_reg);
>
> intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
> @@ -481,8 +480,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
>
> msleep(intel_dp->pps.panel_power_down_delay);
>
> - intel_dp->DP = DP;
> -
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_wakeref_t wakeref;
>
> @@ -582,19 +579,18 @@ cpt_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 *DP = &intel_dp->DP;
>
> - *DP &= ~DP_LINK_TRAIN_MASK_CPT;
> + intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
>
> switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
> case DP_TRAINING_PATTERN_DISABLE:
> - *DP |= DP_LINK_TRAIN_OFF_CPT;
> + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> break;
> case DP_TRAINING_PATTERN_1:
> - *DP |= DP_LINK_TRAIN_PAT_1_CPT;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
> break;
> case DP_TRAINING_PATTERN_2:
> - *DP |= DP_LINK_TRAIN_PAT_2_CPT;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
> break;
> default:
> MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
> @@ -611,19 +607,18 @@ g4x_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 *DP = &intel_dp->DP;
>
> - *DP &= ~DP_LINK_TRAIN_MASK;
> + intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
>
> switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
> case DP_TRAINING_PATTERN_DISABLE:
> - *DP |= DP_LINK_TRAIN_OFF;
> + intel_dp->DP |= DP_LINK_TRAIN_OFF;
> break;
> case DP_TRAINING_PATTERN_1:
> - *DP |= DP_LINK_TRAIN_PAT_1;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
> break;
> case DP_TRAINING_PATTERN_2:
> - *DP |= DP_LINK_TRAIN_PAT_2;
> + intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
> break;
> default:
> MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
` (2 preceding siblings ...)
2021-09-30 13:43 ` [Intel-gfx] [PATCH 4/4] drm/i915: Nuke local copies/pointers of intel_dp->DP Ville Syrjala
@ 2021-09-30 15:25 ` Imre Deak
2021-09-30 16:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
2021-09-30 19:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Imre Deak @ 2021-09-30 15:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Sep 30, 2021 at 04:43:07PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we clear the leftover vswing/preemphasis values only
> at the start of link training. That means the initial vswing
> programming performed during modeset is going to use stale values
> left over from the previous link training sequence, and then at
> the start of link training we're going to reset the levels back
> to 0. Seems much better to make sure we start with level 0 from
> the get go.
>
> Additionally if LTTPRs are present the leftover vswing/preemphasis
> values are those of the last link in the chain, so not the values
> that our PHY is even using after a successful link training sequence.
>
> So let's make sure everything is cleared up before we start
> programming anything.
>
> Suggested-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8f5a935b72b6..74a657ae131a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1835,6 +1835,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> void intel_dp_set_link_params(struct intel_dp *intel_dp,
> int link_rate, int lane_count)
> {
> + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> intel_dp->link_trained = false;
> intel_dp->link_rate = link_rate;
> intel_dp->lane_count = lane_count;
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
` (3 preceding siblings ...)
2021-09-30 15:25 ` [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Imre Deak
@ 2021-09-30 16:15 ` Patchwork
2021-09-30 19:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-09-30 16:15 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4012 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset
URL : https://patchwork.freedesktop.org/series/95275/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10666 -> Patchwork_21204
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/index.html
Known issues
------------
Here are the changes found in Patchwork_21204 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-kbl-soraka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][3] -> [FAIL][4] ([i915#4165]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][5] -> [DMESG-WARN][6] ([i915#295]) +18 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][7] ([i915#2940]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][9] ([i915#541]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (33 -> 28)
------------------------------
Missing (5): bat-dg1-6 fi-tgl-u2 fi-bsw-cyan bat-adlp-4 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10666 -> Patchwork_21204
CI-20190529: 20190529
CI_DRM_10666: fb718bc531fbe5ccecf5a100280860ce07c25476 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6228: 22643ce4014a0b2dc52ce7916b2f657e2a7757c3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21204: 733bf06f5a89702b70a21d22d4d8296d444b8534 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
733bf06f5a89 drm/i915: Nuke local copies/pointers of intel_dp->DP
ce730375e50f drm/i915: Remove DP_PORT_EN stuff from link training code
df98c6bae80b drm/i915: Call intel_ddi_init_dp_buf_reg() earlier
2637b8567fa3 drm/i915: Clear leftover DP vswing/preemphasis values before modeset
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/index.html
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^ permalink raw reply [flat|nested] 13+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset
2021-09-30 13:43 [Intel-gfx] [PATCH 1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset Ville Syrjala
` (4 preceding siblings ...)
2021-09-30 16:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] " Patchwork
@ 2021-09-30 19:49 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-09-30 19:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30317 bytes --]
== Series Details ==
Series: series starting with [1/4] drm/i915: Clear leftover DP vswing/preemphasis values before modeset
URL : https://patchwork.freedesktop.org/series/95275/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10666_full -> Patchwork_21204_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21204_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb2/igt@feature_discovery@psr2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb7/igt@feature_discovery@psr2.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842] / [i915#3468])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][11] -> [SKIP][12] ([i915#2190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb8/igt@gem_huc_copy@huc-copy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#3297])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][15] ([i915#3318])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl3/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][16] ([i915#2856]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl2/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#1937])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111644] / [i915#1397] / [i915#2411])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#111614])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111615]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3689]) +4 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk4/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +9 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][31] ([i915#3689] / [i915#3886])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +20 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@kms_chamelium@vga-edid-read.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-b-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk4/igt@kms_color_chamelium@pipe-b-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-degamma:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@kms_color_chamelium@pipe-b-degamma.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#3116])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb1/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@kms_content_protection@lic.html
- shard-kbl: NOTRUN -> [TIMEOUT][39] ([i915#1319])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3319]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- shard-apl: NOTRUN -> [FAIL][41] ([i915#3444])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
- shard-skl: NOTRUN -> [FAIL][42] ([i915#3444])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#3359]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271]) +53 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#2346])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl6/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#4103])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][50] -> [FAIL][51] ([i915#79])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][52] ([i915#180])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [PASS][53] -> [SKIP][54] ([i915#3701])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109280]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][56] ([fdo#109271]) +66 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#111825]) +13 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][58] -> [INCOMPLETE][59] ([i915#456])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-skl: [PASS][60] -> [DMESG-WARN][61] ([i915#1982])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][62] ([fdo#109271]) +36 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1188])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][69] ([i915#265])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#265])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][71] -> [FAIL][72] ([fdo#108145] / [i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +8 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][76] -> [SKIP][77] ([fdo#109642] / [fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr2_su@page_flip:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][79] ([i915#132] / [i915#3467])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][82] ([IGT#2])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl6/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2437])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#2437])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2437])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-tglb: NOTRUN -> [SKIP][86] ([fdo#109289])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@perf@unprivileged-single-ctx-counters.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271]) +249 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl6/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@pidname:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#2994])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [TIMEOUT][93] ([i915#3063]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb6/igt@gem_eio@in-flight-contexts-1us.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb1/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][95] ([i915#2842]) -> [PASS][96] +1 similar issue
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][97] ([i915#2842]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][99] ([i915#180]) -> [PASS][100] +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: [INCOMPLETE][101] ([i915#198] / [i915#4173]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl6/igt@i915_suspend@fence-restore-untiled.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [FAIL][103] ([i915#72]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-glk3/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [INCOMPLETE][105] ([i915#146] / [i915#198]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][107] ([i915#79]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][109] ([i915#2122]) -> [PASS][110] +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [SKIP][111] ([i915#3701]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-tglb: [INCOMPLETE][113] ([i915#2411] / [i915#456]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
- shard-skl: [DMESG-WARN][115] ([i915#1982]) -> [PASS][116] +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl10/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl1/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][117] ([fdo#108145] / [i915#265]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][119] ([fdo#109441]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb8/igt@kms_psr@psr2_suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_psr@suspend:
- shard-tglb: [INCOMPLETE][121] ([i915#456]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-tglb7/igt@kms_psr@suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-tglb1/igt@kms_psr@suspend.html
#### Warnings ####
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][123] ([i915#118] / [i915#95]) -> [DMESG-WARN][124] ([i915#118] / [i915#1982] / [i915#95])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: [FAIL][125] ([i915#3722]) -> [FAIL][126] ([i915#3743])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-skl5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][127] ([i915#658]) -> [SKIP][128] ([i915#2920]) +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][129] ([i915#2920]) -> [SKIP][130] ([i915#658])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][131] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][132] ([i915#4148])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-iclb8/igt@kms_psr2_su@page_flip.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][133], [FAIL][134], [FAIL][135]) ([i915#1436] / [i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][136], [FAIL][137]) ([i915#3002] / [i915#3363])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl4/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10666/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/shard-kbl7/igt@runner@aborted.html
- shard-apl: ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([fdo#109271] / [i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][143], [FAIL][144],
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21204/index.html
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