* [PATCH] drm/i915/gt: move remaining debugfs interfaces into gt
@ 2021-09-30 23:11 ` Andi Shyti
0 siblings, 0 replies; 4+ messages in thread
From: Andi Shyti @ 2021-09-30 23:11 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++-
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_debugfs.c | 71 -------
6 files changed, 271 insertions(+), 72 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5c8e022a7383..770565c38448 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -100,6 +100,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 03fb4aefbf90..2daff03a705a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,10 +8,53 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+static int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+static int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >->reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", &reset_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -23,10 +66,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>->uc, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
new file mode 100644
index 000000000000..3cf9ae8437e5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+
+static int interrupt_info_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ int i;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ if (IS_CHERRYVIEW(i915)) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "Master Interrupt Control: %08x\n",
+ intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
+
+ seq_printf(m, "Render/Copy Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RENDER_COPY_INTR_ENABLE));
+ seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS_VECS_INTR_ENABLE));
+ seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_ENABLE));
+ seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+ seq_printf(m, "Crypto Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_ENABLE));
+ seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_ENABLE));
+
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (IS_VALLEYVIEW(i915)) {
+ seq_printf(m, "Master IER:\t%08x\n",
+ intel_uncore_read(uncore, VLV_MASTER_IER));
+
+ seq_printf(m, "Render IER:\t%08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Render IIR:\t%08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Render IMR:\t%08x\n",
+ intel_uncore_read(uncore, GTIMR));
+
+ seq_printf(m, "PM IER:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIER));
+ seq_printf(m, "PM IIR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIIR));
+ seq_printf(m, "PM IMR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIMR));
+
+ } else if (!HAS_PCH_SPLIT(i915)) {
+ seq_printf(m, "Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GEN2_IER));
+ seq_printf(m, "Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GEN2_IIR));
+ seq_printf(m, "Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GEN2_IMR));
+ } else {
+ seq_printf(m, "Graphics Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Graphics Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Graphics Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GTIMR));
+ }
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "RCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RCS0_RSVD_INTR_MASK));
+ seq_printf(m, "BCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_BCS_RSVD_INTR_MASK));
+ seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS0_VCS1_INTR_MASK));
+ seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS2_VCS3_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
+ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
+ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
+
+ seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VECS0_VECS1_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
+ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
+
+ seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_MASK));
+ seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_MASK));
+ seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_MASK));
+ seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_MASK));
+
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ for_each_engine(engine, gt, id) {
+ seq_printf(m,
+ "Graphics Interrupt mask (%s): %08x\n",
+ engine->name, ENGINE_READ(engine, RING_IMR));
+ }
+ }
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return 0;
+}
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "interrupt_info", &interrupt_info_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
new file mode 100644
index 000000000000..95e519705001
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef INTEL_GT_IRQ_DEBUGFS_H
+#define INTEL_GT_IRQ_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_IRQ_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5f84ad602642..c75af6f97e7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -19,6 +19,36 @@
#include "intel_sideband.h"
#include "intel_uncore.h"
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ atomic_inc(>->user_wakeref);
+ intel_gt_pm_get(gt);
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
+
+ return 0;
+}
+
+static int forcewake_user_release(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_put(gt->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>->user_wakeref);
+
+ return 0;
+}
+
+static const struct file_operations forcewake_user_fops = {
+ .owner = THIS_MODULE,
+ .open = forcewake_user_open,
+ .release = forcewake_user_release,
+};
+
static int fw_domains_show(struct seq_file *m, void *data)
{
struct intel_gt *gt = m->private;
@@ -627,6 +657,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{ "drpc", &drpc_fops, NULL },
{ "frequency", &frequency_fops, NULL },
{ "forcewake", &fw_domains_fops, NULL },
+ { "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
};
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..5a2a9315c889 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -554,42 +554,6 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
return 0;
}
-static int
-i915_wedged_get(void *data, u64 *val)
-{
- struct drm_i915_private *i915 = data;
- int ret = intel_gt_terminally_wedged(&i915->gt);
-
- switch (ret) {
- case -EIO:
- *val = 1;
- return 0;
- case 0:
- *val = 0;
- return 0;
- default:
- return ret;
- }
-}
-
-static int
-i915_wedged_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* Flush any previous reset before applying for a new one */
- wait_event(i915->gt.reset.queue,
- !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
-
- intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
- "Manually set wedged engine mask = %llx", val);
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
- i915_wedged_get, i915_wedged_set,
- "%llu\n");
-
static int
i915_perf_noa_delay_set(void *data, u64 val)
{
@@ -725,38 +689,6 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return intel_sseu_status(m, gt);
}
-static int i915_forcewake_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- atomic_inc(>->user_wakeref);
- intel_gt_pm_get(gt);
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_get(gt->uncore);
-
- return 0;
-}
-
-static int i915_forcewake_release(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_put(&i915->uncore);
- intel_gt_pm_put(gt);
- atomic_dec(>->user_wakeref);
-
- return 0;
-}
-
-static const struct file_operations i915_forcewake_fops = {
- .owner = THIS_MODULE,
- .open = i915_forcewake_open,
- .release = i915_forcewake_release,
-};
-
static const struct drm_info_list i915_debugfs_list[] = {
{"i915_capabilities", i915_capabilities, 0},
{"i915_gem_objects", i915_gem_object_info, 0},
@@ -775,7 +707,6 @@ static const struct i915_debugfs_files {
const struct file_operations *fops;
} i915_debugfs_files[] = {
{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
- {"i915_wedged", &i915_wedged_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
{"i915_error_state", &i915_error_state_fops},
@@ -790,8 +721,6 @@ void i915_debugfs_register(struct drm_i915_private *dev_priv)
i915_debugfs_params(dev_priv);
- debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
- to_i915(minor->dev), &i915_forcewake_fops);
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
debugfs_create_file(i915_debugfs_files[i].name,
S_IRUGO | S_IWUSR,
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: move remaining debugfs interfaces into gt
@ 2021-09-30 23:11 ` Andi Shyti
0 siblings, 0 replies; 4+ messages in thread
From: Andi Shyti @ 2021-09-30 23:11 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++-
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_debugfs.c | 71 -------
6 files changed, 271 insertions(+), 72 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5c8e022a7383..770565c38448 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -100,6 +100,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 03fb4aefbf90..2daff03a705a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,10 +8,53 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+static int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+static int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >->reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", &reset_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -23,10 +66,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>->uc, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
new file mode 100644
index 000000000000..3cf9ae8437e5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+
+static int interrupt_info_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ int i;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ if (IS_CHERRYVIEW(i915)) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "Master Interrupt Control: %08x\n",
+ intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
+
+ seq_printf(m, "Render/Copy Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RENDER_COPY_INTR_ENABLE));
+ seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS_VECS_INTR_ENABLE));
+ seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_ENABLE));
+ seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+ seq_printf(m, "Crypto Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_ENABLE));
+ seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_ENABLE));
+
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (IS_VALLEYVIEW(i915)) {
+ seq_printf(m, "Master IER:\t%08x\n",
+ intel_uncore_read(uncore, VLV_MASTER_IER));
+
+ seq_printf(m, "Render IER:\t%08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Render IIR:\t%08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Render IMR:\t%08x\n",
+ intel_uncore_read(uncore, GTIMR));
+
+ seq_printf(m, "PM IER:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIER));
+ seq_printf(m, "PM IIR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIIR));
+ seq_printf(m, "PM IMR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIMR));
+
+ } else if (!HAS_PCH_SPLIT(i915)) {
+ seq_printf(m, "Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GEN2_IER));
+ seq_printf(m, "Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GEN2_IIR));
+ seq_printf(m, "Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GEN2_IMR));
+ } else {
+ seq_printf(m, "Graphics Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Graphics Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Graphics Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GTIMR));
+ }
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "RCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RCS0_RSVD_INTR_MASK));
+ seq_printf(m, "BCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_BCS_RSVD_INTR_MASK));
+ seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS0_VCS1_INTR_MASK));
+ seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS2_VCS3_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
+ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
+ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
+
+ seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VECS0_VECS1_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
+ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
+
+ seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_MASK));
+ seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_MASK));
+ seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_MASK));
+ seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_MASK));
+
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ for_each_engine(engine, gt, id) {
+ seq_printf(m,
+ "Graphics Interrupt mask (%s): %08x\n",
+ engine->name, ENGINE_READ(engine, RING_IMR));
+ }
+ }
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return 0;
+}
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "interrupt_info", &interrupt_info_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
new file mode 100644
index 000000000000..95e519705001
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef INTEL_GT_IRQ_DEBUGFS_H
+#define INTEL_GT_IRQ_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_IRQ_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5f84ad602642..c75af6f97e7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -19,6 +19,36 @@
#include "intel_sideband.h"
#include "intel_uncore.h"
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ atomic_inc(>->user_wakeref);
+ intel_gt_pm_get(gt);
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
+
+ return 0;
+}
+
+static int forcewake_user_release(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_put(gt->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>->user_wakeref);
+
+ return 0;
+}
+
+static const struct file_operations forcewake_user_fops = {
+ .owner = THIS_MODULE,
+ .open = forcewake_user_open,
+ .release = forcewake_user_release,
+};
+
static int fw_domains_show(struct seq_file *m, void *data)
{
struct intel_gt *gt = m->private;
@@ -627,6 +657,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{ "drpc", &drpc_fops, NULL },
{ "frequency", &frequency_fops, NULL },
{ "forcewake", &fw_domains_fops, NULL },
+ { "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
};
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..5a2a9315c889 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -554,42 +554,6 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
return 0;
}
-static int
-i915_wedged_get(void *data, u64 *val)
-{
- struct drm_i915_private *i915 = data;
- int ret = intel_gt_terminally_wedged(&i915->gt);
-
- switch (ret) {
- case -EIO:
- *val = 1;
- return 0;
- case 0:
- *val = 0;
- return 0;
- default:
- return ret;
- }
-}
-
-static int
-i915_wedged_set(void *data, u64 val)
-{
- struct drm_i915_private *i915 = data;
-
- /* Flush any previous reset before applying for a new one */
- wait_event(i915->gt.reset.queue,
- !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
-
- intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
- "Manually set wedged engine mask = %llx", val);
- return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
- i915_wedged_get, i915_wedged_set,
- "%llu\n");
-
static int
i915_perf_noa_delay_set(void *data, u64 val)
{
@@ -725,38 +689,6 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return intel_sseu_status(m, gt);
}
-static int i915_forcewake_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- atomic_inc(>->user_wakeref);
- intel_gt_pm_get(gt);
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_get(gt->uncore);
-
- return 0;
-}
-
-static int i915_forcewake_release(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_put(&i915->uncore);
- intel_gt_pm_put(gt);
- atomic_dec(>->user_wakeref);
-
- return 0;
-}
-
-static const struct file_operations i915_forcewake_fops = {
- .owner = THIS_MODULE,
- .open = i915_forcewake_open,
- .release = i915_forcewake_release,
-};
-
static const struct drm_info_list i915_debugfs_list[] = {
{"i915_capabilities", i915_capabilities, 0},
{"i915_gem_objects", i915_gem_object_info, 0},
@@ -775,7 +707,6 @@ static const struct i915_debugfs_files {
const struct file_operations *fops;
} i915_debugfs_files[] = {
{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
- {"i915_wedged", &i915_wedged_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
{"i915_error_state", &i915_error_state_fops},
@@ -790,8 +721,6 @@ void i915_debugfs_register(struct drm_i915_private *dev_priv)
i915_debugfs_params(dev_priv);
- debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
- to_i915(minor->dev), &i915_forcewake_fops);
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
debugfs_create_file(i915_debugfs_files[i].name,
S_IRUGO | S_IWUSR,
--
2.27.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev7)
2021-09-30 23:11 ` [Intel-gfx] " Andi Shyti
(?)
@ 2021-09-30 23:40 ` Patchwork
-1 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2021-09-30 23:40 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev7)
URL : https://patchwork.freedesktop.org/series/75333/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8fdbaf0abd82 drm/i915/gt: move remaining debugfs interfaces into gt
-:112: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#112:
new file mode 100644
-:245: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#245: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:129:
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
-:249: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#249: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:133:
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
-:258: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#258: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:142:
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
total: 0 errors, 1 warnings, 3 checks, 404 lines checked
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev7)
2021-09-30 23:11 ` [Intel-gfx] " Andi Shyti
(?)
(?)
@ 2021-10-01 0:12 ` Patchwork
-1 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2021-10-01 0:12 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18049 bytes --]
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev7)
URL : https://patchwork.freedesktop.org/series/75333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10670 -> Patchwork_21211
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21211 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21211, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21211:
### IGT changes ###
#### Possible regressions ####
* igt@i915_hangman@error-state-basic:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-kbl-7500u/igt@i915_hangman@error-state-basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-7500u/igt@i915_hangman@error-state-basic.html
- fi-kbl-soraka: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-kbl-soraka/igt@i915_hangman@error-state-basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-soraka/igt@i915_hangman@error-state-basic.html
- fi-bwr-2160: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-bwr-2160/igt@i915_hangman@error-state-basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-bwr-2160/igt@i915_hangman@error-state-basic.html
- fi-kbl-r: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-kbl-r/igt@i915_hangman@error-state-basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-r/igt@i915_hangman@error-state-basic.html
- fi-kbl-8809g: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-kbl-8809g/igt@i915_hangman@error-state-basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-8809g/igt@i915_hangman@error-state-basic.html
- fi-bsw-nick: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-bsw-nick/igt@i915_hangman@error-state-basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-bsw-nick/igt@i915_hangman@error-state-basic.html
- fi-glk-dsi: [PASS][13] -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-glk-dsi/igt@i915_hangman@error-state-basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-glk-dsi/igt@i915_hangman@error-state-basic.html
- fi-icl-u2: [PASS][15] -> [FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-icl-u2/igt@i915_hangman@error-state-basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-icl-u2/igt@i915_hangman@error-state-basic.html
- fi-cfl-8109u: [PASS][17] -> [FAIL][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cfl-8109u/igt@i915_hangman@error-state-basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cfl-8109u/igt@i915_hangman@error-state-basic.html
- fi-skl-6600u: [PASS][19] -> [FAIL][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-skl-6600u/igt@i915_hangman@error-state-basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-skl-6600u/igt@i915_hangman@error-state-basic.html
- fi-cfl-8700k: [PASS][21] -> [FAIL][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cfl-8700k/igt@i915_hangman@error-state-basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cfl-8700k/igt@i915_hangman@error-state-basic.html
- fi-bsw-kefka: [PASS][23] -> [FAIL][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-bsw-kefka/igt@i915_hangman@error-state-basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-bsw-kefka/igt@i915_hangman@error-state-basic.html
- fi-pnv-d510: [PASS][25] -> [FAIL][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-pnv-d510/igt@i915_hangman@error-state-basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-pnv-d510/igt@i915_hangman@error-state-basic.html
- fi-ilk-650: [PASS][27] -> [FAIL][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-ilk-650/igt@i915_hangman@error-state-basic.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-ilk-650/igt@i915_hangman@error-state-basic.html
- fi-tgl-u2: NOTRUN -> [FAIL][29]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@i915_hangman@error-state-basic.html
- fi-bsw-n3050: [PASS][30] -> [FAIL][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-bsw-n3050/igt@i915_hangman@error-state-basic.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-bsw-n3050/igt@i915_hangman@error-state-basic.html
- fi-rkl-11600: [PASS][32] -> [FAIL][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-rkl-11600/igt@i915_hangman@error-state-basic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-rkl-11600/igt@i915_hangman@error-state-basic.html
- fi-kbl-7567u: [PASS][34] -> [FAIL][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-kbl-7567u/igt@i915_hangman@error-state-basic.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-7567u/igt@i915_hangman@error-state-basic.html
- fi-icl-y: [PASS][36] -> [FAIL][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-icl-y/igt@i915_hangman@error-state-basic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-icl-y/igt@i915_hangman@error-state-basic.html
- fi-cfl-guc: [PASS][38] -> [FAIL][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cfl-guc/igt@i915_hangman@error-state-basic.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cfl-guc/igt@i915_hangman@error-state-basic.html
- fi-elk-e7500: [PASS][40] -> [FAIL][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-elk-e7500/igt@i915_hangman@error-state-basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-elk-e7500/igt@i915_hangman@error-state-basic.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][42]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@i915_hangman@error-state-basic.html
- fi-bxt-dsi: [PASS][43] -> [FAIL][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-bxt-dsi/igt@i915_hangman@error-state-basic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-bxt-dsi/igt@i915_hangman@error-state-basic.html
- fi-cml-u2: [PASS][45] -> [FAIL][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cml-u2/igt@i915_hangman@error-state-basic.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cml-u2/igt@i915_hangman@error-state-basic.html
- fi-rkl-guc: [PASS][47] -> [FAIL][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-rkl-guc/igt@i915_hangman@error-state-basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-rkl-guc/igt@i915_hangman@error-state-basic.html
#### Warnings ####
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: [DMESG-WARN][49] ([i915#1610]) -> [FAIL][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-apl-guc/igt@i915_hangman@error-state-basic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@i915_hangman@error-state-basic.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_hangman@error-state-basic:
- {fi-tgl-dsi}: [PASS][51] -> [FAIL][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-tgl-dsi/igt@i915_hangman@error-state-basic.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-dsi/igt@i915_hangman@error-state-basic.html
- {fi-ehl-2}: [PASS][53] -> [FAIL][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-ehl-2/igt@i915_hangman@error-state-basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-ehl-2/igt@i915_hangman@error-state-basic.html
- {fi-jsl-1}: [PASS][55] -> [FAIL][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-jsl-1/igt@i915_hangman@error-state-basic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-jsl-1/igt@i915_hangman@error-state-basic.html
Known issues
------------
Here are the changes found in Patchwork_21211 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][57] ([fdo#109315])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
- fi-kbl-soraka: NOTRUN -> [SKIP][58] ([fdo#109271])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-kbl-soraka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][59] ([fdo#109315] / [i915#2575]) +16 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: NOTRUN -> [INCOMPLETE][60] ([i915#4130])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: NOTRUN -> [FAIL][61] ([i915#1888])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][62] ([i915#2190])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][63] ([i915#2190])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][64] ([i915#1155])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@gt_engines:
- fi-apl-guc: NOTRUN -> [DMESG-FAIL][65] ([i915#2927])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@workarounds:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][66] ([i915#1610])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][67] ([fdo#111827]) +8 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][68] ([fdo#109284] / [fdo#111827]) +8 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-apl-guc: NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +8 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][70] ([i915#4103]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][71] ([i915#4103]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][72] -> [FAIL][73] ([i915#4165]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][74] ([fdo#109285])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-u2: NOTRUN -> [SKIP][75] ([fdo#109285])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][76] -> [DMESG-WARN][77] ([i915#295]) +18 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-apl-guc: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#533])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][79] ([i915#1072]) +3 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@primary_page_flip:
- fi-apl-guc: NOTRUN -> [SKIP][80] ([fdo#109271]) +11 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@kms_psr@primary_page_flip.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][81] ([i915#3301])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][82] ([i915#3301])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-u2: NOTRUN -> [FAIL][83] ([i915#1602] / [i915#2722])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-tgl-u2/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- fi-apl-guc: [FAIL][84] ([i915#2426] / [i915#3363]) -> [FAIL][85] ([fdo#109271] / [i915#2426] / [i915#3363])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10670/fi-apl-guc/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/fi-apl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (32 -> 29)
------------------------------
Additional (2): fi-tgl-1115g4 fi-tgl-u2
Missing (5): bat-dg1-6 fi-bsw-cyan bat-adlp-4 bat-jsl-2 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10670 -> Patchwork_21211
CI-20190529: 20190529
CI_DRM_10670: 3d3b1ccf805891e2b05ba21cb98790aa0cfa48a8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6228: 22643ce4014a0b2dc52ce7916b2f657e2a7757c3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21211: 8fdbaf0abd82f3501d87567b33838786a90b40b0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8fdbaf0abd82 drm/i915/gt: move remaining debugfs interfaces into gt
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21211/index.html
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^ permalink raw reply [flat|nested] 4+ messages in thread
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Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-30 23:11 [PATCH] drm/i915/gt: move remaining debugfs interfaces into gt Andi Shyti
2021-09-30 23:11 ` [Intel-gfx] " Andi Shyti
2021-09-30 23:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev7) Patchwork
2021-10-01 0:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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