* [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next
@ 2021-10-06 21:59 Rodrigo Vivi
2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 2/3] tests/gem_userptr_blits: Remove LOCAL_ Rodrigo Vivi
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2021-10-06 21:59 UTC (permalink / raw)
To: igt-dev; +Cc: Rodrigo Vivi, Petri Latvala, Ashutosh Dixit
Let's do a catch-up on i915_drm.h here.
Only on i915_drm.h for now so we can have a clean
view of the LOCAL_ ones that we need to remove.
Taken from 25fed6b324ac ("Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-next")
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
include/drm-uapi/i915_drm.h | 48 +++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index b9632bb2..c788a1ab 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -572,6 +572,15 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+/*
+ * Indicates the 2k user priority levels are statically mapped into 3 buckets as
+ * follows:
+ *
+ * -1k to -1 Low priority
+ * 0 Normal priority
+ * 1 to 1k Highest priority
+ */
+#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
@@ -674,6 +683,9 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
+#define I915_PARAM_HAS_USERPTR_PROBE 56
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -923,6 +935,25 @@ struct drm_i915_gem_mmap_offset {
* - I915_GEM_DOMAIN_GTT: Mappable aperture domain
*
* All other domains are rejected.
+ *
+ * Note that for discrete, starting from DG1, this is no longer supported, and
+ * is instead rejected. On such platforms the CPU domain is effectively static,
+ * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
+ * which can't be set explicitly and instead depends on the object placements,
+ * as per the below.
+ *
+ * Implicit caching rules, starting from DG1:
+ *
+ * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
+ * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
+ * mapped as write-combined only.
+ *
+ * - Everything else is always allocated and mapped as write-back, with the
+ * guarantee that everything is also coherent with the GPU.
+ *
+ * Note that this is likely to change in the future again, where we might need
+ * more flexibility on future devices, so making this all explicit as part of a
+ * new &drm_i915_gem_create_ext extension is probable.
*/
struct drm_i915_gem_set_domain {
/** @handle: Handle for the object. */
@@ -2203,12 +2234,29 @@ struct drm_i915_gem_userptr {
* through the GTT. If the HW can't support readonly access, an error is
* returned.
*
+ * I915_USERPTR_PROBE:
+ *
+ * Probe the provided @user_ptr range and validate that the @user_ptr is
+ * indeed pointing to normal memory and that the range is also valid.
+ * For example if some garbage address is given to the kernel, then this
+ * should complain.
+ *
+ * Returns -EFAULT if the probe failed.
+ *
+ * Note that this doesn't populate the backing pages, and also doesn't
+ * guarantee that the object will remain valid when the object is
+ * eventually used.
+ *
+ * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
+ * returns a non-zero value.
+ *
* I915_USERPTR_UNSYNCHRONIZED:
*
* NOT USED. Setting this flag will result in an error.
*/
__u32 flags;
#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_PROBE 0x2
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
/**
* @handle: Returned handle for the object.
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [igt-dev] [PATCH i-g-t 2/3] tests/gem_userptr_blits: Remove LOCAL_ 2021-10-06 21:59 [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next Rodrigo Vivi @ 2021-10-06 21:59 ` Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 3/3] include/drm-uapi: Sync with drm-next Rodrigo Vivi ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: Rodrigo Vivi @ 2021-10-06 21:59 UTC (permalink / raw) To: igt-dev Cc: Rodrigo Vivi, Zbigniew Kempczyński, Chris Wilson, Petri Latvala, Ashutosh Dixit These UAPIs are upstreamed now. Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- tests/i915/gem_userptr_blits.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/tests/i915/gem_userptr_blits.c b/tests/i915/gem_userptr_blits.c index 756bd6e4..0d084674 100644 --- a/tests/i915/gem_userptr_blits.c +++ b/tests/i915/gem_userptr_blits.c @@ -2151,16 +2151,13 @@ static int userfaultfd(int flags) return syscall(SYS_userfaultfd, flags); } -#define LOCAL_I915_PARAM_HAS_USERPTR_PROBE 56 -#define LOCAL_I915_USERPTR_PROBE 0x2 - static bool has_userptr_probe(int fd) { struct drm_i915_getparam gp; int value = 0; memset(&gp, 0, sizeof(gp)); - gp.param = LOCAL_I915_PARAM_HAS_USERPTR_PROBE; + gp.param = I915_PARAM_HAS_USERPTR_PROBE; gp.value = &value; ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)); @@ -2222,7 +2219,7 @@ static void test_probe(int fd) } igt_assert_eq(__gem_userptr(fd, ptr + PAGE_SIZE, 3*PAGE_SIZE, - 0, LOCAL_I915_USERPTR_PROBE, &handle), + 0, I915_USERPTR_PROBE, &handle), expected); munmap(ptr, N_PAGES * PAGE_SIZE); -- 2.31.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] [PATCH i-g-t 3/3] include/drm-uapi: Sync with drm-next 2021-10-06 21:59 [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 2/3] tests/gem_userptr_blits: Remove LOCAL_ Rodrigo Vivi @ 2021-10-06 21:59 ` Rodrigo Vivi 2021-10-06 23:08 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] i915_drm.h sync " Patchwork 2021-10-07 1:33 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 3 siblings, 0 replies; 5+ messages in thread From: Rodrigo Vivi @ 2021-10-06 21:59 UTC (permalink / raw) To: igt-dev; +Cc: Rodrigo Vivi, Petri Latvala, Ashutosh Dixit Sync to: 1e3944578b74 ("Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next") Cc: Petri Latvala <petri.latvala@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- include/drm-uapi/drm.h | 14 +- include/drm-uapi/drm_fourcc.h | 115 ++++++++- include/drm-uapi/drm_mode.h | 95 +++++++- include/drm-uapi/msm_drm.h | 14 +- include/drm-uapi/tegra_drm.h | 425 ++++++++++++++++++++++++++++++++-- include/drm-uapi/v3d_drm.h | 136 +++++++++++ include/drm-uapi/vmwgfx_drm.h | 41 ++++ 7 files changed, 807 insertions(+), 33 deletions(-) diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/drm.h index 398c396f..5e54c3aa 100644 --- a/include/drm-uapi/drm.h +++ b/include/drm-uapi/drm.h @@ -629,8 +629,8 @@ struct drm_gem_open { /** * DRM_CAP_VBLANK_HIGH_CRTC * - * If set to 1, the kernel supports specifying a CRTC index in the high bits of - * &drm_wait_vblank_request.type. + * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>` + * in the high bits of &drm_wait_vblank_request.type. * * Starting kernel version 2.6.39, this capability is always set to 1. */ @@ -1044,6 +1044,16 @@ extern "C" { #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) +/** + * DRM_IOCTL_MODE_RMFB - Remove a framebuffer. + * + * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL + * argument is a framebuffer object ID. + * + * Warning: removing a framebuffer currently in-use on an enabled plane will + * disable that plane. The CRTC the plane is linked to may also be disabled + * (depending on driver capabilities). + */ #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h index cd3ce8a8..91b6a0fd 100644 --- a/include/drm-uapi/drm_fourcc.h +++ b/include/drm-uapi/drm_fourcc.h @@ -373,6 +373,12 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#define fourcc_mod_get_vendor(modifier) \ + (((modifier) >> 56) & 0xff) + +#define fourcc_mod_is_vendor(modifier, vendor) \ + (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) + #define fourcc_mod_code(vendor, val) \ ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) @@ -900,9 +906,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) /* * The top 4 bits (out of the 56 bits alloted for specifying vendor specific - * modifiers) denote the category for modifiers. Currently we have only two - * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen - * different categories. + * modifiers) denote the category for modifiers. Currently we have three + * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of + * sixteen different categories. */ #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) @@ -1017,6 +1023,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AFBC_FORMAT_MOD_USM (1ULL << 12) +/* + * Arm Fixed-Rate Compression (AFRC) modifiers + * + * AFRC is a proprietary fixed rate image compression protocol and format, + * designed to provide guaranteed bandwidth and memory footprint + * reductions in graphics and media use-cases. + * + * AFRC buffers consist of one or more planes, with the same components + * and meaning as an uncompressed buffer using the same pixel format. + * + * Within each plane, the pixel/luma/chroma values are grouped into + * "coding unit" blocks which are individually compressed to a + * fixed size (in bytes). All coding units within a given plane of a buffer + * store the same number of values, and have the same compressed size. + * + * The coding unit size is configurable, allowing different rates of compression. + * + * The start of each AFRC buffer plane must be aligned to an alignment granule which + * depends on the coding unit size. + * + * Coding Unit Size Plane Alignment + * ---------------- --------------- + * 16 bytes 1024 bytes + * 24 bytes 512 bytes + * 32 bytes 2048 bytes + * + * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned + * to a multiple of the paging tile dimensions. + * The dimensions of each paging tile depend on whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Layout Paging Tile Width Paging Tile Height + * ------ ----------------- ------------------ + * SCAN 16 coding units 4 coding units + * ROT 8 coding units 8 coding units + * + * The dimensions of each coding unit depend on the number of components + * in the compressed plane and whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Number of Components in Plane Layout Coding Unit Width Coding Unit Height + * ----------------------------- --------- ----------------- ------------------ + * 1 SCAN 16 samples 4 samples + * Example: 16x4 luma samples in a 'Y' plane + * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 1 ROT 8 samples 8 samples + * Example: 8x8 luma samples in a 'Y' plane + * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 2 DONT CARE 8 samples 4 samples + * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 3 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer without alpha + * ----------------------------- --------- ----------------- ------------------ + * 4 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer with alpha + */ + +#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 + +#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) + +/* + * AFRC coding unit size modifier. + * + * Indicates the number of bytes used to store each compressed coding unit for + * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance + * is the same for both Cb and Cr, which may be stored in separate planes. + * + * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store + * each compressed coding unit in the first plane of the buffer. For RGBA buffers + * this is the only plane, while for semi-planar and fully-planar YUV buffers, + * this corresponds to the luma plane. + * + * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store + * each compressed coding unit in the second and third planes in the buffer. + * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). + * + * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified + * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. + * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and + * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. + */ +#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf +#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) + +#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) +#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) + +/* + * AFRC scanline memory layout. + * + * Indicates if the buffer uses the scanline-optimised layout + * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. + * The memory layout is the same for all planes. + */ +#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) + /* * Arm 16x16 Block U-Interleaved modifier * diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h index 9b6722d4..e4a2570a 100644 --- a/include/drm-uapi/drm_mode.h +++ b/include/drm-uapi/drm_mode.h @@ -312,16 +312,48 @@ struct drm_mode_set_plane { __u32 src_w; }; +/** + * struct drm_mode_get_plane - Get plane metadata. + * + * Userspace can perform a GETPLANE ioctl to retrieve information about a + * plane. + * + * To retrieve the number of formats supported, set @count_format_types to zero + * and call the ioctl. @count_format_types will be updated with the value. + * + * To retrieve these formats, allocate an array with the memory needed to store + * @count_format_types formats. Point @format_type_ptr to this array and call + * the ioctl again (with @count_format_types still set to the value returned in + * the first ioctl call). + */ struct drm_mode_get_plane { + /** + * @plane_id: Object ID of the plane whose information should be + * retrieved. Set by caller. + */ __u32 plane_id; + /** @crtc_id: Object ID of the current CRTC. */ __u32 crtc_id; + /** @fb_id: Object ID of the current fb. */ __u32 fb_id; + /** + * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's + * are created and they receive an index, which corresponds to their + * position in the bitmask. Bit N corresponds to + * :ref:`CRTC index<crtc_index>` N. + */ __u32 possible_crtcs; + /** @gamma_size: Never used. */ __u32 gamma_size; + /** @count_format_types: Number of formats. */ __u32 count_format_types; + /** + * @format_type_ptr: Pointer to ``__u32`` array of formats that are + * supported by the plane. These formats do not require modifiers. + */ __u64 format_type_ptr; }; @@ -509,22 +541,74 @@ struct drm_mode_get_connector { */ #define DRM_MODE_PROP_ATOMIC 0x80000000 +/** + * struct drm_mode_property_enum - Description for an enum/bitfield entry. + * @value: numeric value for this enum entry. + * @name: symbolic name for this enum entry. + * + * See struct drm_property_enum for details. + */ struct drm_mode_property_enum { __u64 value; char name[DRM_PROP_NAME_LEN]; }; +/** + * struct drm_mode_get_property - Get property metadata. + * + * User-space can perform a GETPROPERTY ioctl to retrieve information about a + * property. The same property may be attached to multiple objects, see + * "Modeset Base Object Abstraction". + * + * The meaning of the @values_ptr field changes depending on the property type. + * See &drm_property.flags for more details. + * + * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the + * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For + * backwards compatibility, the kernel will always set @count_enum_blobs to + * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must + * ignore these two fields if the property has a different type. + * + * User-space is expected to retrieve values and enums by performing this ioctl + * at least twice: the first time to retrieve the number of elements, the + * second time to retrieve the elements themselves. + * + * To retrieve the number of elements, set @count_values and @count_enum_blobs + * to zero, then call the ioctl. @count_values will be updated with the number + * of elements. If the property has the type &DRM_MODE_PROP_ENUM or + * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well. + * + * To retrieve the elements themselves, allocate an array for @values_ptr and + * set @count_values to its capacity. If the property has the type + * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for + * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl + * again will fill the arrays. + */ struct drm_mode_get_property { - __u64 values_ptr; /* values and blob lengths */ - __u64 enum_blob_ptr; /* enum and blob id ptrs */ + /** @values_ptr: Pointer to a ``__u64`` array. */ + __u64 values_ptr; + /** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */ + __u64 enum_blob_ptr; + /** + * @prop_id: Object ID of the property which should be retrieved. Set + * by the caller. + */ __u32 prop_id; + /** + * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for + * a definition of the flags. + */ __u32 flags; + /** + * @name: Symbolic property name. User-space should use this field to + * recognize properties. + */ char name[DRM_PROP_NAME_LEN]; + /** @count_values: Number of elements in @values_ptr. */ __u32 count_values; - /* This is only used to count enum values, not blobs. The _blobs is - * simply because of a historical reason, i.e. backwards compat. */ + /** @count_enum_blobs: Number of elements in @enum_blob_ptr. */ __u32 count_enum_blobs; }; @@ -1026,6 +1110,9 @@ struct drm_mode_destroy_blob { * struct drm_mode_create_lease - Create lease * * Lease mode resources, creating another drm_master. + * + * The @object_ids array must reference at least one CRTC, one connector and + * one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. */ struct drm_mode_create_lease { /** @object_ids: Pointer to array of object ids (__u32) */ diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h index f0758510..6b8fffc2 100644 --- a/include/drm-uapi/msm_drm.h +++ b/include/drm-uapi/msm_drm.h @@ -73,11 +73,19 @@ struct drm_msm_timespec { #define MSM_PARAM_MAX_FREQ 0x04 #define MSM_PARAM_TIMESTAMP 0x05 #define MSM_PARAM_GMEM_BASE 0x06 -#define MSM_PARAM_NR_RINGS 0x07 +#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */ #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */ #define MSM_PARAM_FAULTS 0x09 #define MSM_PARAM_SUSPENDS 0x0a +/* For backwards compat. The original support for preemption was based on + * a single ring per priority level so # of priority levels equals the # + * of rings. With drm/scheduler providing additional levels of priority, + * the number of priorities is greater than the # of rings. The param is + * renamed to better reflect this. + */ +#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES + struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ __u32 param; /* in, MSM_PARAM_x */ @@ -304,6 +312,10 @@ struct drm_msm_gem_madvise { #define MSM_SUBMITQUEUE_FLAGS (0) +/* + * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1, + * a lower numeric value is higher priority. + */ struct drm_msm_submitqueue { __u32 flags; /* in, MSM_SUBMITQUEUE_x */ __u32 prio; /* in, Priority level */ diff --git a/include/drm-uapi/tegra_drm.h b/include/drm-uapi/tegra_drm.h index 6c07919c..bb1adff0 100644 --- a/include/drm-uapi/tegra_drm.h +++ b/include/drm-uapi/tegra_drm.h @@ -1,24 +1,5 @@ -/* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +/* SPDX-License-Identifier: MIT */ +/* Copyright (c) 2012-2020 NVIDIA Corporation */ #ifndef _TEGRA_DRM_H_ #define _TEGRA_DRM_H_ @@ -29,6 +10,8 @@ extern "C" { #endif +/* Tegra DRM legacy UAPI. Only enabled with STAGING */ + #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) @@ -649,8 +632,8 @@ struct drm_tegra_gem_get_flags { #define DRM_TEGRA_SYNCPT_READ 0x02 #define DRM_TEGRA_SYNCPT_INCR 0x03 #define DRM_TEGRA_SYNCPT_WAIT 0x04 -#define DRM_TEGRA_OPEN_CHANNEL 0x05 -#define DRM_TEGRA_CLOSE_CHANNEL 0x06 +#define DRM_TEGRA_OPEN_CHANNEL 0x05 +#define DRM_TEGRA_CLOSE_CHANNEL 0x06 #define DRM_TEGRA_GET_SYNCPT 0x07 #define DRM_TEGRA_SUBMIT 0x08 #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 @@ -674,6 +657,402 @@ struct drm_tegra_gem_get_flags { #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) +/* New Tegra DRM UAPI */ + +/* + * Reported by the driver in the `capabilities` field. + * + * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent + * with regard to the system memory. + */ +#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0) + +struct drm_tegra_channel_open { + /** + * @host1x_class: [in] + * + * Host1x class of the engine that will be programmed using this + * channel. + */ + __u32 host1x_class; + + /** + * @flags: [in] + * + * Flags. + */ + __u32 flags; + + /** + * @context: [out] + * + * Opaque identifier corresponding to the opened channel. + */ + __u32 context; + + /** + * @version: [out] + * + * Version of the engine hardware. This can be used by userspace + * to determine how the engine needs to be programmed. + */ + __u32 version; + + /** + * @capabilities: [out] + * + * Flags describing the hardware capabilities. + */ + __u32 capabilities; + __u32 padding; +}; + +struct drm_tegra_channel_close { + /** + * @context: [in] + * + * Identifier of the channel to close. + */ + __u32 context; + __u32 padding; +}; + +/* + * Mapping flags that can be used to influence how the mapping is created. + * + * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access + * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access + */ +#define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) +#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) +#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \ + DRM_TEGRA_CHANNEL_MAP_WRITE) + +struct drm_tegra_channel_map { + /** + * @context: [in] + * + * Identifier of the channel to which make memory available for. + */ + __u32 context; + + /** + * @handle: [in] + * + * GEM handle of the memory to map. + */ + __u32 handle; + + /** + * @flags: [in] + * + * Flags. + */ + __u32 flags; + + /** + * @mapping: [out] + * + * Identifier corresponding to the mapping, to be used for + * relocations or unmapping later. + */ + __u32 mapping; +}; + +struct drm_tegra_channel_unmap { + /** + * @context: [in] + * + * Channel identifier of the channel to unmap memory from. + */ + __u32 context; + + /** + * @mapping: [in] + * + * Mapping identifier of the memory mapping to unmap. + */ + __u32 mapping; +}; + +/* Submission */ + +/** + * Specify that bit 39 of the patched-in address should be set to switch + * swizzling between Tegra and non-Tegra sector layout on systems that store + * surfaces in system memory in non-Tegra sector layout. + */ +#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0) + +struct drm_tegra_submit_buf { + /** + * @mapping: [in] + * + * Identifier of the mapping to use in the submission. + */ + __u32 mapping; + + /** + * @flags: [in] + * + * Flags. + */ + __u32 flags; + + /** + * Information for relocation patching. + */ + struct { + /** + * @target_offset: [in] + * + * Offset from the start of the mapping of the data whose + * address is to be patched into the gather. + */ + __u64 target_offset; + + /** + * @gather_offset_words: [in] + * + * Offset in words from the start of the gather data to + * where the address should be patched into. + */ + __u32 gather_offset_words; + + /** + * @shift: [in] + * + * Number of bits the address should be shifted right before + * patching in. + */ + __u32 shift; + } reloc; +}; + +/** + * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr` + * buffer. Each GATHER_UPTR command uses successive words from the buffer. + */ +#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0 +/** + * Wait for a syncpoint to reach a value before continuing with further + * commands. + */ +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1 +/** + * Wait for a syncpoint to reach a value before continuing with further + * commands. The threshold is calculated relative to the start of the job. + */ +#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2 + +struct drm_tegra_submit_cmd_gather_uptr { + __u32 words; + __u32 reserved[3]; +}; + +struct drm_tegra_submit_cmd_wait_syncpt { + __u32 id; + __u32 value; + __u32 reserved[2]; +}; + +struct drm_tegra_submit_cmd { + /** + * @type: [in] + * + * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD* + * defines. + */ + __u32 type; + + /** + * @flags: [in] + * + * Flags. + */ + __u32 flags; + + union { + struct drm_tegra_submit_cmd_gather_uptr gather_uptr; + struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt; + __u32 reserved[4]; + }; +}; + +struct drm_tegra_submit_syncpt { + /** + * @id: [in] + * + * ID of the syncpoint that the job will increment. + */ + __u32 id; + + /** + * @flags: [in] + * + * Flags. + */ + __u32 flags; + + /** + * @increments: [in] + * + * Number of times the job will increment this syncpoint. + */ + __u32 increments; + + /** + * @value: [out] + * + * Value the syncpoint will have once the job has completed all + * its specified syncpoint increments. + * + * Note that the kernel may increment the syncpoint before or after + * the job. These increments are not reflected in this field. + * + * If the job hangs or times out, not all of the increments may + * get executed. + */ + __u32 value; +}; + +struct drm_tegra_channel_submit { + /** + * @context: [in] + * + * Identifier of the channel to submit this job to. + */ + __u32 context; + + /** + * @num_bufs: [in] + * + * Number of elements in the `bufs_ptr` array. + */ + __u32 num_bufs; + + /** + * @num_cmds: [in] + * + * Number of elements in the `cmds_ptr` array. + */ + __u32 num_cmds; + + /** + * @gather_data_words: [in] + * + * Number of 32-bit words in the `gather_data_ptr` array. + */ + __u32 gather_data_words; + + /** + * @bufs_ptr: [in] + * + * Pointer to an array of drm_tegra_submit_buf structures. + */ + __u64 bufs_ptr; + + /** + * @cmds_ptr: [in] + * + * Pointer to an array of drm_tegra_submit_cmd structures. + */ + __u64 cmds_ptr; + + /** + * @gather_data_ptr: [in] + * + * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR + * commands. + */ + __u64 gather_data_ptr; + + /** + * @syncobj_in: [in] + * + * Handle for DRM syncobj that will be waited before submission. + * Ignored if zero. + */ + __u32 syncobj_in; + + /** + * @syncobj_out: [in] + * + * Handle for DRM syncobj that will have its fence replaced with + * the job's completion fence. Ignored if zero. + */ + __u32 syncobj_out; + + /** + * @syncpt_incr: [in,out] + * + * Information about the syncpoint the job will increment. + */ + struct drm_tegra_submit_syncpt syncpt; +}; + +struct drm_tegra_syncpoint_allocate { + /** + * @id: [out] + * + * ID of allocated syncpoint. + */ + __u32 id; + __u32 padding; +}; + +struct drm_tegra_syncpoint_free { + /** + * @id: [in] + * + * ID of syncpoint to free. + */ + __u32 id; + __u32 padding; +}; + +struct drm_tegra_syncpoint_wait { + /** + * @timeout: [in] + * + * Absolute timestamp at which the wait will time out. + */ + __s64 timeout_ns; + + /** + * @id: [in] + * + * ID of syncpoint to wait on. + */ + __u32 id; + + /** + * @threshold: [in] + * + * Threshold to wait for. + */ + __u32 threshold; + + /** + * @value: [out] + * + * Value of the syncpoint upon wait completion. + */ + __u32 value; + + __u32 padding; +}; + +#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) +#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) +#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) +#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) +#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) + +#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) +#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) +#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) + #if defined(__cplusplus) } #endif diff --git a/include/drm-uapi/v3d_drm.h b/include/drm-uapi/v3d_drm.h index 1ce746e2..4104f22f 100644 --- a/include/drm-uapi/v3d_drm.h +++ b/include/drm-uapi/v3d_drm.h @@ -38,6 +38,9 @@ extern "C" { #define DRM_V3D_GET_BO_OFFSET 0x05 #define DRM_V3D_SUBMIT_TFU 0x06 #define DRM_V3D_SUBMIT_CSD 0x07 +#define DRM_V3D_PERFMON_CREATE 0x08 +#define DRM_V3D_PERFMON_DESTROY 0x09 +#define DRM_V3D_PERFMON_GET_VALUES 0x0a #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) @@ -47,6 +50,12 @@ extern "C" { #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) +#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \ + struct drm_v3d_perfmon_create) +#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \ + struct drm_v3d_perfmon_destroy) +#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \ + struct drm_v3d_perfmon_get_values) #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 @@ -127,6 +136,11 @@ struct drm_v3d_submit_cl { __u32 bo_handle_count; __u32 flags; + + /* ID of the perfmon to attach to this job. 0 means no perfmon. */ + __u32 perfmon_id; + + __u32 pad; }; /** @@ -195,6 +209,7 @@ enum drm_v3d_param { DRM_V3D_PARAM_SUPPORTS_TFU, DRM_V3D_PARAM_SUPPORTS_CSD, DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH, + DRM_V3D_PARAM_SUPPORTS_PERFMON, }; struct drm_v3d_get_param { @@ -258,6 +273,127 @@ struct drm_v3d_submit_csd { __u32 in_sync; /* Sync object to signal when the CSD job is done. */ __u32 out_sync; + + /* ID of the perfmon to attach to this job. 0 means no perfmon. */ + __u32 perfmon_id; +}; + +enum { + V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS, + V3D_PERFCNT_FEP_VALID_PRIMS, + V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS, + V3D_PERFCNT_FEP_VALID_QUADS, + V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL, + V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL, + V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS, + V3D_PERFCNT_TLB_QUADS_ZERO_COV, + V3D_PERFCNT_TLB_QUADS_NONZERO_COV, + V3D_PERFCNT_TLB_QUADS_WRITTEN, + V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD, + V3D_PERFCNT_PTB_PRIM_CLIP, + V3D_PERFCNT_PTB_PRIM_REV, + V3D_PERFCNT_QPU_IDLE_CYCLES, + V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER, + V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG, + V3D_PERFCNT_QPU_CYCLES_VALID_INSTR, + V3D_PERFCNT_QPU_CYCLES_TMU_STALL, + V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL, + V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL, + V3D_PERFCNT_QPU_IC_HIT, + V3D_PERFCNT_QPU_IC_MISS, + V3D_PERFCNT_QPU_UC_HIT, + V3D_PERFCNT_QPU_UC_MISS, + V3D_PERFCNT_TMU_TCACHE_ACCESS, + V3D_PERFCNT_TMU_TCACHE_MISS, + V3D_PERFCNT_VPM_VDW_STALL, + V3D_PERFCNT_VPM_VCD_STALL, + V3D_PERFCNT_BIN_ACTIVE, + V3D_PERFCNT_RDR_ACTIVE, + V3D_PERFCNT_L2T_HITS, + V3D_PERFCNT_L2T_MISSES, + V3D_PERFCNT_CYCLE_COUNT, + V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER, + V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT, + V3D_PERFCNT_PTB_PRIMS_BINNED, + V3D_PERFCNT_AXI_WRITES_WATCH_0, + V3D_PERFCNT_AXI_READS_WATCH_0, + V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0, + V3D_PERFCNT_AXI_READ_STALLS_WATCH_0, + V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0, + V3D_PERFCNT_AXI_READ_BYTES_WATCH_0, + V3D_PERFCNT_AXI_WRITES_WATCH_1, + V3D_PERFCNT_AXI_READS_WATCH_1, + V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1, + V3D_PERFCNT_AXI_READ_STALLS_WATCH_1, + V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1, + V3D_PERFCNT_AXI_READ_BYTES_WATCH_1, + V3D_PERFCNT_TLB_PARTIAL_QUADS, + V3D_PERFCNT_TMU_CONFIG_ACCESSES, + V3D_PERFCNT_L2T_NO_ID_STALL, + V3D_PERFCNT_L2T_COM_QUE_STALL, + V3D_PERFCNT_L2T_TMU_WRITES, + V3D_PERFCNT_TMU_ACTIVE_CYCLES, + V3D_PERFCNT_TMU_STALLED_CYCLES, + V3D_PERFCNT_CLE_ACTIVE, + V3D_PERFCNT_L2T_TMU_READS, + V3D_PERFCNT_L2T_CLE_READS, + V3D_PERFCNT_L2T_VCD_READS, + V3D_PERFCNT_L2T_TMUCFG_READS, + V3D_PERFCNT_L2T_SLC0_READS, + V3D_PERFCNT_L2T_SLC1_READS, + V3D_PERFCNT_L2T_SLC2_READS, + V3D_PERFCNT_L2T_TMU_W_MISSES, + V3D_PERFCNT_L2T_TMU_R_MISSES, + V3D_PERFCNT_L2T_CLE_MISSES, + V3D_PERFCNT_L2T_VCD_MISSES, + V3D_PERFCNT_L2T_TMUCFG_MISSES, + V3D_PERFCNT_L2T_SLC0_MISSES, + V3D_PERFCNT_L2T_SLC1_MISSES, + V3D_PERFCNT_L2T_SLC2_MISSES, + V3D_PERFCNT_CORE_MEM_WRITES, + V3D_PERFCNT_L2T_MEM_WRITES, + V3D_PERFCNT_PTB_MEM_WRITES, + V3D_PERFCNT_TLB_MEM_WRITES, + V3D_PERFCNT_CORE_MEM_READS, + V3D_PERFCNT_L2T_MEM_READS, + V3D_PERFCNT_PTB_MEM_READS, + V3D_PERFCNT_PSE_MEM_READS, + V3D_PERFCNT_TLB_MEM_READS, + V3D_PERFCNT_GMP_MEM_READS, + V3D_PERFCNT_PTB_W_MEM_WORDS, + V3D_PERFCNT_TLB_W_MEM_WORDS, + V3D_PERFCNT_PSE_R_MEM_WORDS, + V3D_PERFCNT_TLB_R_MEM_WORDS, + V3D_PERFCNT_TMU_MRU_HITS, + V3D_PERFCNT_COMPUTE_ACTIVE, + V3D_PERFCNT_NUM, +}; + +#define DRM_V3D_MAX_PERF_COUNTERS 32 + +struct drm_v3d_perfmon_create { + __u32 id; + __u32 ncounters; + __u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; +}; + +struct drm_v3d_perfmon_destroy { + __u32 id; +}; + +/* + * Returns the values of the performance counters tracked by this + * perfmon (as an array of ncounters u64 values). + * + * No implicit synchronization is performed, so the user has to + * guarantee that any jobs using this perfmon have already been + * completed (probably by blocking on the seqno returned by the + * last exec that used the perfmon). + */ +struct drm_v3d_perfmon_get_values { + __u32 id; + __u32 pad; + __u64 values_ptr; }; #if defined(__cplusplus) diff --git a/include/drm-uapi/vmwgfx_drm.h b/include/drm-uapi/vmwgfx_drm.h index 02e91750..9078775f 100644 --- a/include/drm-uapi/vmwgfx_drm.h +++ b/include/drm-uapi/vmwgfx_drm.h @@ -72,6 +72,9 @@ extern "C" { #define DRM_VMW_GB_SURFACE_CREATE_EXT 27 #define DRM_VMW_GB_SURFACE_REF_EXT 28 #define DRM_VMW_MSG 29 +#define DRM_VMW_MKSSTAT_RESET 30 +#define DRM_VMW_MKSSTAT_ADD 31 +#define DRM_VMW_MKSSTAT_REMOVE 32 /*************************************************************************/ /** @@ -1236,6 +1239,44 @@ struct drm_vmw_msg_arg { __u32 receive_len; }; +/** + * struct drm_vmw_mksstat_add_arg + * + * @stat: Pointer to user-space stat-counters array, page-aligned. + * @info: Pointer to user-space counter-infos array, page-aligned. + * @strs: Pointer to user-space stat strings, page-aligned. + * @stat_len: Length in bytes of stat-counters array. + * @info_len: Length in bytes of counter-infos array. + * @strs_len: Length in bytes of the stat strings, terminators included. + * @description: Pointer to instance descriptor string; will be truncated + * to MKS_GUEST_STAT_INSTANCE_DESC_LENGTH chars. + * @id: Output identifier of the produced record; -1 if error. + * + * Argument to the DRM_VMW_MKSSTAT_ADD ioctl. + */ +struct drm_vmw_mksstat_add_arg { + __u64 stat; + __u64 info; + __u64 strs; + __u64 stat_len; + __u64 info_len; + __u64 strs_len; + __u64 description; + __u64 id; +}; + +/** + * struct drm_vmw_mksstat_remove_arg + * + * @id: Identifier of the record being disposed, originally obtained through + * DRM_VMW_MKSSTAT_ADD ioctl. + * + * Argument to the DRM_VMW_MKSSTAT_REMOVE ioctl. + */ +struct drm_vmw_mksstat_remove_arg { + __u64 id; +}; + #if defined(__cplusplus) } #endif -- 2.31.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] i915_drm.h sync with drm-next 2021-10-06 21:59 [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 2/3] tests/gem_userptr_blits: Remove LOCAL_ Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 3/3] include/drm-uapi: Sync with drm-next Rodrigo Vivi @ 2021-10-06 23:08 ` Patchwork 2021-10-07 1:33 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 3 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2021-10-06 23:08 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 3727 bytes --] == Series Details == Series: series starting with [i-g-t,1/3] i915_drm.h sync with drm-next URL : https://patchwork.freedesktop.org/series/95537/ State : success == Summary == CI Bug Log - changes from IGT_6235 -> IGTPW_6298 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/index.html Known issues ------------ Here are the changes found in IGTPW_6298 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fence@basic-busy@bcs0: - fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-apl-guc/igt@gem_exec_fence@basic-busy@bcs0.html * igt@i915_hangman@error-state-basic: - fi-apl-guc: NOTRUN -> [DMESG-WARN][2] ([i915#1610]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-apl-guc/igt@i915_hangman@error-state-basic.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2940]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/fi-bsw-n3050/igt@i915_selftest@live@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-bsw-n3050/igt@i915_selftest@live@execlists.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#4269]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][7] ([i915#2029] / [i915#3363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-skl-6600u/igt@runner@aborted.html - fi-apl-guc: NOTRUN -> [FAIL][8] ([i915#2426] / [i915#3363]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-apl-guc/igt@runner@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / [i915#3428]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/fi-bsw-n3050/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 Participating hosts (41 -> 37) ------------------------------ Additional (1): fi-apl-guc Missing (5): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-bsw-cyan fi-ctg-p8600 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_6235 -> IGTPW_6298 CI-20190529: 20190529 CI_DRM_10690: 08f4ed46e449b8f4d1e258c879b22c2c22bb1e84 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_6298: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/index.html IGT_6235: 65dd7d484d5d09de196def254afebf41dfde1052 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/index.html [-- Attachment #2: Type: text/html, Size: 4538 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/3] i915_drm.h sync with drm-next 2021-10-06 21:59 [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next Rodrigo Vivi ` (2 preceding siblings ...) 2021-10-06 23:08 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] i915_drm.h sync " Patchwork @ 2021-10-07 1:33 ` Patchwork 3 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2021-10-07 1:33 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: igt-dev [-- Attachment #1: Type: text/plain, Size: 30280 bytes --] == Series Details == Series: series starting with [i-g-t,1/3] i915_drm.h sync with drm-next URL : https://patchwork.freedesktop.org/series/95537/ State : success == Summary == CI Bug Log - changes from IGT_6235_full -> IGTPW_6298_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/index.html Known issues ------------ Here are the changes found in IGTPW_6298_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb5/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +6 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb2/igt@gem_ctx_persistence@engines-mixed-process.html * igt@gem_eio@unwedge-stress: - shard-snb: NOTRUN -> [FAIL][3] ([i915#3354]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb5/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk3/igt@gem_exec_fair@basic-deadline.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk8/igt@gem_exec_fair@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][6] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl2/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2842]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb3/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_suspend@basic-s3: - shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#456]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-tglb3/igt@gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@gem_exec_suspend@basic-s3.html * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk9/igt@gem_exec_whisper@basic-fds-priority.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk1/igt@gem_exec_whisper@basic-fds-priority.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][15] ([i915#2658]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl2/igt@gem_pwrite@basic-exhaustion.html * igt@gem_pxp@verify-pxp-stale-ctx-execution: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4270]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb2/igt@gem_pxp@verify-pxp-stale-ctx-execution.html * igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#768]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb3/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html * igt@gem_softpin@evict-snoop: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109312]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb2/igt@gem_softpin@evict-snoop.html * igt@gem_userptr_blits@access-control: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#3297]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb3/igt@gem_userptr_blits@access-control.html * igt@gem_userptr_blits@create-destroy-unsync: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#3297]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@gem_userptr_blits@create-destroy-unsync.html * igt@gem_userptr_blits@dmabuf-sync: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#3323]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb3/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][22] ([i915#3002]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl3/igt@gem_userptr_blits@input-checking.html * igt@gen9_exec_parse@basic-rejected-ctx-param: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#2856]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb4/igt@gen9_exec_parse@basic-rejected-ctx-param.html * igt@gen9_exec_parse@batch-invalid-length: - shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271]) +448 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb6/igt@gen9_exec_parse@batch-invalid-length.html * igt@gen9_exec_parse@bb-start-cmd: - shard-tglb: NOTRUN -> [SKIP][25] ([i915#2856]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb5/igt@gen9_exec_parse@bb-start-cmd.html * igt@i915_pm_dc@dc6-psr: - shard-tglb: NOTRUN -> [FAIL][26] ([i915#454]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rc6_residency@media-rc6-accuracy: - shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109289] / [fdo#111719]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb2/igt@i915_pm_rc6_residency@media-rc6-accuracy.html * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271]) +304 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl7/igt@i915_pm_rpm@modeset-lpsp-stress.html * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111644] / [i915#1397] / [i915#2411]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-iclb: NOTRUN -> [SKIP][30] ([i915#1769]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html * igt@kms_big_fb@linear-32bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][31] ([fdo#110725] / [fdo#111614]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@kms_big_fb@linear-32bpp-rotate-270.html * igt@kms_big_fb@y-tiled-16bpp-rotate-180: - shard-glk: [PASS][32] -> [DMESG-FAIL][33] ([i915#118]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk9/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-8bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110723]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_joiner@basic: - shard-tglb: NOTRUN -> [SKIP][37] ([i915#2705]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb3/igt@kms_big_joiner@basic.html - shard-iclb: NOTRUN -> [SKIP][38] ([i915#2705]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_big_joiner@basic.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html - shard-tglb: NOTRUN -> [SKIP][40] ([i915#3689] / [i915#3886]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +13 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +4 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#3886]) +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][44] ([i915#3689]) +4 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb8/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_ccs.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +9 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk9/igt@kms_chamelium@dp-hpd-storm-disable.html * igt@kms_chamelium@vga-hpd: - shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +23 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl7/igt@kms_chamelium@vga-hpd.html * igt@kms_chamelium@vga-hpd-with-enabled-mode: - shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +4 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb6/igt@kms_chamelium@vga-hpd-with-enabled-mode.html * igt@kms_color@pipe-d-ctm-negative: - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#1149]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb8/igt@kms_color@pipe-d-ctm-negative.html * igt@kms_color_chamelium@pipe-a-ctm-0-75: - shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +8 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +20 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-0-5: - shard-tglb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +9 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@kms_color_chamelium@pipe-d-gamma.html * igt@kms_concurrent@pipe-d: - shard-tglb: NOTRUN -> [FAIL][53] ([i915#1385]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb6/igt@kms_concurrent@pipe-d.html * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> [TIMEOUT][54] ([i915#1319]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl3/igt@kms_content_protection@atomic.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][55] ([i915#1319]) +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl1/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@mei_interface: - shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109300] / [fdo#111066]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb5/igt@kms_content_protection@mei_interface.html * igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][57] ([i915#3319]) +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-tglb: [PASS][58] -> [INCOMPLETE][59] ([i915#2411] / [i915#456]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-512x512-random: - shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109279] / [i915#3359]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html * igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen: - shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278]) +13 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][62] ([i915#3359]) +3 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271]) +110 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions: - shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109274] / [fdo#109278]) +2 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html * igt@kms_flip@2x-flip-vs-rmfb: - shard-tglb: NOTRUN -> [SKIP][65] ([fdo#111825]) +27 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb6/igt@kms_flip@2x-flip-vs-rmfb.html - shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109274]) +1 similar issue [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_flip@2x-flip-vs-rmfb.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: NOTRUN -> [DMESG-WARN][67] ([i915#180]) +3 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2672]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen: - shard-glk: NOTRUN -> [SKIP][69] ([fdo#109271]) +74 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt: - shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109280]) +9 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +3 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c: - shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109289]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html - shard-tglb: NOTRUN -> [SKIP][74] ([fdo#109289]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb2/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html * igt@kms_pipe_crc_basic@read-crc-pipe-d: - shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265]) +4 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-glk: NOTRUN -> [FAIL][77] ([i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk5/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-glk: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][79] ([i915#265]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][80] ([fdo#108145] / [i915#265]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_plane_lowres@pipe-b-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][81] ([fdo#112054]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb8/igt@kms_plane_lowres@pipe-b-tiling-yf.html * igt@kms_prime@basic-crc@first-to-second: - shard-iclb: NOTRUN -> [SKIP][82] ([i915#1836]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb3/igt@kms_prime@basic-crc@first-to-second.html - shard-tglb: NOTRUN -> [SKIP][83] ([i915#1836]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb1/igt@kms_prime@basic-crc@first-to-second.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3: - shard-kbl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +2 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html - shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +5 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1: - shard-iclb: NOTRUN -> [SKIP][86] ([i915#658]) +2 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html - shard-glk: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html - shard-tglb: NOTRUN -> [SKIP][88] ([i915#2920]) +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html * igt@kms_psr2_su@page_flip: - shard-tglb: NOTRUN -> [SKIP][89] ([i915#1911]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb8/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109441]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@kms_psr@psr2_no_drrs.html - shard-tglb: NOTRUN -> [FAIL][91] ([i915#132] / [i915#3467]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb6/igt@kms_psr@psr2_no_drrs.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][92] -> [SKIP][93] ([fdo#109441]) +1 similar issue [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0: - shard-tglb: NOTRUN -> [SKIP][94] ([fdo#111615]) +4 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html * igt@kms_vblank@pipe-a-wait-forked-hang: - shard-kbl: [PASS][95] -> [SKIP][96] ([fdo#109271]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-kbl6/igt@kms_vblank@pipe-a-wait-forked-hang.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl3/igt@kms_vblank@pipe-a-wait-forked-hang.html - shard-apl: [PASS][97] -> [SKIP][98] ([fdo#109271]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-apl6/igt@kms_vblank@pipe-a-wait-forked-hang.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl2/igt@kms_vblank@pipe-a-wait-forked-hang.html - shard-glk: [PASS][99] -> [SKIP][100] ([fdo#109271]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk6/igt@kms_vblank@pipe-a-wait-forked-hang.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk1/igt@kms_vblank@pipe-a-wait-forked-hang.html * igt@kms_writeback@writeback-check-output: - shard-glk: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2437]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk9/igt@kms_writeback@writeback-check-output.html * igt@nouveau_crc@pipe-a-ctx-flip-detection: - shard-tglb: NOTRUN -> [SKIP][102] ([i915#2530]) +1 similar issue [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb1/igt@nouveau_crc@pipe-a-ctx-flip-detection.html * igt@nouveau_crc@pipe-a-source-outp-inactive: - shard-iclb: NOTRUN -> [SKIP][103] ([i915#2530]) +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@nouveau_crc@pipe-a-source-outp-inactive.html * igt@prime_nv_api@i915_self_import_to_different_fd: - shard-tglb: NOTRUN -> [SKIP][104] ([fdo#109291]) +2 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb3/igt@prime_nv_api@i915_self_import_to_different_fd.html * igt@prime_udl: - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109291]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb1/igt@prime_udl.html * igt@sysfs_clients@fair-1: - shard-glk: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk1/igt@sysfs_clients@fair-1.html - shard-iclb: NOTRUN -> [SKIP][107] ([i915#2994]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb4/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@pidname: - shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994]) +3 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl6/igt@sysfs_clients@pidname.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglb: [INCOMPLETE][109] ([i915#1373]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@rcs0.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb1/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][111] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-tglb7/igt@gem_eio@unwedge-stress.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [FAIL][113] ([i915#2846]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-kbl1/igt@gem_exec_fair@basic-deadline.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl1/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [FAIL][115] ([i915#2842]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][117] ([i915#2842]) -> [PASS][118] [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120] +1 similar issue [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-kbl6/igt@gem_exec_suspend@basic-s3.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-kbl1/igt@gem_exec_suspend@basic-s3.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-glk: [DMESG-WARN][121] ([i915#118]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk3/igt@gem_exec_whisper@basic-fds-forked-all.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk2/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@gem_sync@basic-many-each: - shard-snb: [INCOMPLETE][123] ([i915#2055]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-snb5/igt@gem_sync@basic-many-each.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-snb6/igt@gem_sync@basic-many-each.html - shard-iclb: [INCOMPLETE][125] -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-iclb7/igt@gem_sync@basic-many-each.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb7/igt@gem_sync@basic-many-each.html * igt@kms_busy@extended-pageflip-hang-newfb@pipe-d: - shard-tglb: [INCOMPLETE][127] -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-tglb6/igt@kms_busy@extended-pageflip-hang-newfb@pipe-d.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-tglb7/igt@kms_busy@extended-pageflip-hang-newfb@pipe-d.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][129] ([i915#180]) -> [PASS][130] +3 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][131] ([i915#72]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][133] ([fdo#109441]) -> [PASS][134] +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html #### Warnings #### * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][135] ([i915#588]) -> [SKIP][136] ([i915#658]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][137] ([i915#1804] / [i915#2684]) -> [WARN][138] ([i915#2684]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6235/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6298/index.html [-- Attachment #2: Type: text/html, Size: 33896 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-10-07 1:33 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-06 21:59 [igt-dev] [PATCH i-g-t 1/3] i915_drm.h sync with drm-next Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 2/3] tests/gem_userptr_blits: Remove LOCAL_ Rodrigo Vivi 2021-10-06 21:59 ` [igt-dev] [PATCH i-g-t 3/3] include/drm-uapi: Sync with drm-next Rodrigo Vivi 2021-10-06 23:08 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] i915_drm.h sync " Patchwork 2021-10-07 1:33 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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