* [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt @ 2021-10-07 23:09 ` Andi Shyti 0 siblings, 0 replies; 11+ messages in thread From: Andi Shyti @ 2021-10-07 23:09 UTC (permalink / raw) To: Intel GFX, DRI Devel Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti From: Andi Shyti <andi.shyti@intel.com> The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset For backwards compatibility with existing igt (and the slight semantic difference between operating on the i915 abi entry points and the deep gt info): dri/0 | +-- i915_wedged | \-- i915_forcewake_user remain at the top level. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- Hi, I am reproposing this patch exactly as it was proposed initially where the original interfaces are kept where they have been originally placed. It might generate some duplicated code but, well, it's debugfs and I don't see any issue. In the future we can transform the upper interfaces to act upon all the GTs and provide information from all the GTs. This is, for example, how the sysfs interfaces will act. The reason I removed them in V1 is because igt as only user is not a strong reason to keep duplicated code, but as Chris suggested offline: "It's debugfs, igt is the primary consumer. CI has to be bridged over changes to the interfaces it is using in any case, as you want comparable results before/after the patches land. For i915_forcewake_user, it's not just igt testing, but part of the tools/ packaged up by distro. That makes it a very strong candidate to be moved out of debugfs into sysfs/gt." I, therefore, repropose this patch with the idea of improving the behavior of the upper level interfaces as described above. Thanks, Andi Changelog: ---------- v1 -> v2: * keep the original interfaces intact (thanks Chris). drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++- .../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++ drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++ 5 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index cdc244bbbfc1..e92984954ba8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -98,6 +98,7 @@ gt-y += \ gt/intel_gt_debugfs.o \ gt/intel_gt_engines_debugfs.o \ gt/intel_gt_irq.o \ + gt/intel_gt_irq_debugfs.o \ gt/intel_gt_pm.o \ gt/intel_gt_pm_debugfs.o \ gt/intel_gt_pm_irq.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index 1fe19ccd2794..d3075c138585 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -8,11 +8,54 @@ #include "i915_drv.h" #include "intel_gt_debugfs.h" #include "intel_gt_engines_debugfs.h" +#include "intel_gt_irq_debugfs.h" +#include "intel_gt_pm.h" #include "intel_gt_pm_debugfs.h" +#include "intel_gt_requests.h" #include "intel_sseu_debugfs.h" #include "pxp/intel_pxp_debugfs.h" #include "uc/intel_uc_debugfs.h" +static int reset_show(void *data, u64 *val) +{ + struct intel_gt *gt = data; + int ret = intel_gt_terminally_wedged(gt); + + switch (ret) { + case -EIO: + *val = 1; + return 0; + case 0: + *val = 0; + return 0; + default: + return ret; + } +} + +static int reset_store(void *data, u64 val) +{ + struct intel_gt *gt = data; + + /* Flush any previous reset before applying for a new one */ + wait_event(gt->reset.queue, + !test_bit(I915_RESET_BACKOFF, >->reset.flags)); + + intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE, + "Manually reset engine mask to %llx", val); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n"); + +static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "reset", &reset_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} + void intel_gt_debugfs_register(struct intel_gt *gt) { struct dentry *root; @@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt) if (IS_ERR(root)) return; + gt_debugfs_register(gt, root); + intel_gt_engines_debugfs_register(gt, root); intel_gt_pm_debugfs_register(gt, root); + intel_gt_irq_debugfs_register(gt, root); intel_sseu_debugfs_register(gt, root); - intel_uc_debugfs_register(>->uc, root); intel_pxp_debugfs_register(>->pxp, root); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c new file mode 100644 index 000000000000..3cf9ae8437e5 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: MIT + +/* + * Copyright © 2020 Intel Corporation + */ + +#include "i915_drv.h" +#include "intel_gt_debugfs.h" +#include "intel_gt_irq_debugfs.h" + +static int interrupt_info_show(struct seq_file *m, void *data) +{ + struct intel_gt *gt = m->private; + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = gt->uncore; + struct intel_engine_cs *engine; + enum intel_engine_id id; + intel_wakeref_t wakeref; + int i; + + wakeref = intel_runtime_pm_get(uncore->rpm); + + if (IS_CHERRYVIEW(i915)) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "Master Interrupt Control: %08x\n", + intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ)); + + seq_printf(m, "Render/Copy Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_RENDER_COPY_INTR_ENABLE)); + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_VCS_VECS_INTR_ENABLE)); + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_ENABLE)); + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_ENABLE)); + seq_printf(m, "Crypto Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_ENABLE)); + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_ENABLE)); + + } else if (GRAPHICS_VER(i915) >= 8) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (IS_VALLEYVIEW(i915)) { + seq_printf(m, "Master IER:\t%08x\n", + intel_uncore_read(uncore, VLV_MASTER_IER)); + + seq_printf(m, "Render IER:\t%08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Render IIR:\t%08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Render IMR:\t%08x\n", + intel_uncore_read(uncore, GTIMR)); + + seq_printf(m, "PM IER:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIER)); + seq_printf(m, "PM IIR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIIR)); + seq_printf(m, "PM IMR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIMR)); + + } else if (!HAS_PCH_SPLIT(i915)) { + seq_printf(m, "Interrupt enable: %08x\n", + intel_uncore_read(uncore, GEN2_IER)); + seq_printf(m, "Interrupt identity: %08x\n", + intel_uncore_read(uncore, GEN2_IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + intel_uncore_read(uncore, GEN2_IMR)); + } else { + seq_printf(m, "Graphics Interrupt enable: %08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + intel_uncore_read(uncore, GTIMR)); + } + + if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "RCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_RCS0_RSVD_INTR_MASK)); + seq_printf(m, "BCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_BCS_RSVD_INTR_MASK)); + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS2_VCS3_INTR_MASK)); + + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) + seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS4_VCS5_INTR_MASK)); + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) + seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS6_VCS7_INTR_MASK)); + + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VECS0_VECS1_INTR_MASK)); + + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) + seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VECS2_VECS3_INTR_MASK)); + + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_MASK)); + seq_printf(m, "Crypto Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_MASK)); + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_MASK)); + + } else if (GRAPHICS_VER(i915) >= 6) { + for_each_engine(engine, gt, id) { + seq_printf(m, + "Graphics Interrupt mask (%s): %08x\n", + engine->name, ENGINE_READ(engine, RING_IMR)); + } + } + + intel_runtime_pm_put(uncore->rpm, wakeref); + + return 0; +} +DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info); + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "interrupt_info", &interrupt_info_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h new file mode 100644 index 000000000000..95e519705001 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef INTEL_GT_IRQ_DEBUGFS_H +#define INTEL_GT_IRQ_DEBUGFS_H + +struct intel_gt; +struct dentry; + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root); + +#endif /* INTEL_GT_IRQ_DEBUGFS_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 5f84ad602642..c75af6f97e7e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -19,6 +19,36 @@ #include "intel_sideband.h" #include "intel_uncore.h" +static int forcewake_user_open(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + atomic_inc(>->user_wakeref); + intel_gt_pm_get(gt); + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_get(gt->uncore); + + return 0; +} + +static int forcewake_user_release(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_put(gt->uncore); + intel_gt_pm_put(gt); + atomic_dec(>->user_wakeref); + + return 0; +} + +static const struct file_operations forcewake_user_fops = { + .owner = THIS_MODULE, + .open = forcewake_user_open, + .release = forcewake_user_release, +}; + static int fw_domains_show(struct seq_file *m, void *data) { struct intel_gt *gt = m->private; @@ -627,6 +657,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) { "drpc", &drpc_fops, NULL }, { "frequency", &frequency_fops, NULL }, { "forcewake", &fw_domains_fops, NULL }, + { "forcewake_user", &forcewake_user_fops, NULL}, { "llc", &llc_fops, llc_eval }, { "rps_boost", &rps_boost_fops, rps_eval }, }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt @ 2021-10-07 23:09 ` Andi Shyti 0 siblings, 0 replies; 11+ messages in thread From: Andi Shyti @ 2021-10-07 23:09 UTC (permalink / raw) To: Intel GFX, DRI Devel Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti From: Andi Shyti <andi.shyti@intel.com> The following interfaces: i915_wedged i915_forcewake_user i915_gem_interrupt are dependent on gt values. Put them inside gt/ and drop the "i915_" prefix name. This would be the new structure: dri/0/gt | +-- forcewake_user | +-- interrupt_info | \-- reset For backwards compatibility with existing igt (and the slight semantic difference between operating on the i915 abi entry points and the deep gt info): dri/0 | +-- i915_wedged | \-- i915_forcewake_user remain at the top level. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- Hi, I am reproposing this patch exactly as it was proposed initially where the original interfaces are kept where they have been originally placed. It might generate some duplicated code but, well, it's debugfs and I don't see any issue. In the future we can transform the upper interfaces to act upon all the GTs and provide information from all the GTs. This is, for example, how the sysfs interfaces will act. The reason I removed them in V1 is because igt as only user is not a strong reason to keep duplicated code, but as Chris suggested offline: "It's debugfs, igt is the primary consumer. CI has to be bridged over changes to the interfaces it is using in any case, as you want comparable results before/after the patches land. For i915_forcewake_user, it's not just igt testing, but part of the tools/ packaged up by distro. That makes it a very strong candidate to be moved out of debugfs into sysfs/gt." I, therefore, repropose this patch with the idea of improving the behavior of the upper level interfaces as described above. Thanks, Andi Changelog: ---------- v1 -> v2: * keep the original interfaces intact (thanks Chris). drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++- .../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++ drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++ 5 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index cdc244bbbfc1..e92984954ba8 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -98,6 +98,7 @@ gt-y += \ gt/intel_gt_debugfs.o \ gt/intel_gt_engines_debugfs.o \ gt/intel_gt_irq.o \ + gt/intel_gt_irq_debugfs.o \ gt/intel_gt_pm.o \ gt/intel_gt_pm_debugfs.o \ gt/intel_gt_pm_irq.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index 1fe19ccd2794..d3075c138585 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -8,11 +8,54 @@ #include "i915_drv.h" #include "intel_gt_debugfs.h" #include "intel_gt_engines_debugfs.h" +#include "intel_gt_irq_debugfs.h" +#include "intel_gt_pm.h" #include "intel_gt_pm_debugfs.h" +#include "intel_gt_requests.h" #include "intel_sseu_debugfs.h" #include "pxp/intel_pxp_debugfs.h" #include "uc/intel_uc_debugfs.h" +static int reset_show(void *data, u64 *val) +{ + struct intel_gt *gt = data; + int ret = intel_gt_terminally_wedged(gt); + + switch (ret) { + case -EIO: + *val = 1; + return 0; + case 0: + *val = 0; + return 0; + default: + return ret; + } +} + +static int reset_store(void *data, u64 val) +{ + struct intel_gt *gt = data; + + /* Flush any previous reset before applying for a new one */ + wait_event(gt->reset.queue, + !test_bit(I915_RESET_BACKOFF, >->reset.flags)); + + intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE, + "Manually reset engine mask to %llx", val); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n"); + +static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "reset", &reset_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} + void intel_gt_debugfs_register(struct intel_gt *gt) { struct dentry *root; @@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt) if (IS_ERR(root)) return; + gt_debugfs_register(gt, root); + intel_gt_engines_debugfs_register(gt, root); intel_gt_pm_debugfs_register(gt, root); + intel_gt_irq_debugfs_register(gt, root); intel_sseu_debugfs_register(gt, root); - intel_uc_debugfs_register(>->uc, root); intel_pxp_debugfs_register(>->pxp, root); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c new file mode 100644 index 000000000000..3cf9ae8437e5 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: MIT + +/* + * Copyright © 2020 Intel Corporation + */ + +#include "i915_drv.h" +#include "intel_gt_debugfs.h" +#include "intel_gt_irq_debugfs.h" + +static int interrupt_info_show(struct seq_file *m, void *data) +{ + struct intel_gt *gt = m->private; + struct drm_i915_private *i915 = gt->i915; + struct intel_uncore *uncore = gt->uncore; + struct intel_engine_cs *engine; + enum intel_engine_id id; + intel_wakeref_t wakeref; + int i; + + wakeref = intel_runtime_pm_get(uncore->rpm); + + if (IS_CHERRYVIEW(i915)) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "Master Interrupt Control: %08x\n", + intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ)); + + seq_printf(m, "Render/Copy Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_RENDER_COPY_INTR_ENABLE)); + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_VCS_VECS_INTR_ENABLE)); + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_ENABLE)); + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_ENABLE)); + seq_printf(m, "Crypto Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_ENABLE)); + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_ENABLE)); + + } else if (GRAPHICS_VER(i915) >= 8) { + seq_printf(m, "Master Interrupt Control:\t%08x\n", + intel_uncore_read(uncore, GEN8_MASTER_IRQ)); + + for (i = 0; i < 4; i++) { + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IMR(i))); + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IIR(i))); + seq_printf(m, "GT Interrupt IER %d:\t%08x\n", + i, intel_uncore_read(uncore, + GEN8_GT_IER(i))); + } + + } else if (IS_VALLEYVIEW(i915)) { + seq_printf(m, "Master IER:\t%08x\n", + intel_uncore_read(uncore, VLV_MASTER_IER)); + + seq_printf(m, "Render IER:\t%08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Render IIR:\t%08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Render IMR:\t%08x\n", + intel_uncore_read(uncore, GTIMR)); + + seq_printf(m, "PM IER:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIER)); + seq_printf(m, "PM IIR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIIR)); + seq_printf(m, "PM IMR:\t\t%08x\n", + intel_uncore_read(uncore, GEN6_PMIMR)); + + } else if (!HAS_PCH_SPLIT(i915)) { + seq_printf(m, "Interrupt enable: %08x\n", + intel_uncore_read(uncore, GEN2_IER)); + seq_printf(m, "Interrupt identity: %08x\n", + intel_uncore_read(uncore, GEN2_IIR)); + seq_printf(m, "Interrupt mask: %08x\n", + intel_uncore_read(uncore, GEN2_IMR)); + } else { + seq_printf(m, "Graphics Interrupt enable: %08x\n", + intel_uncore_read(uncore, GTIER)); + seq_printf(m, "Graphics Interrupt identity: %08x\n", + intel_uncore_read(uncore, GTIIR)); + seq_printf(m, "Graphics Interrupt mask: %08x\n", + intel_uncore_read(uncore, GTIMR)); + } + + if (GRAPHICS_VER(i915) >= 11) { + seq_printf(m, "RCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_RCS0_RSVD_INTR_MASK)); + seq_printf(m, "BCS Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_BCS_RSVD_INTR_MASK)); + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VCS2_VCS3_INTR_MASK)); + + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) + seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS4_VCS5_INTR_MASK)); + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) + seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VCS6_VCS7_INTR_MASK)); + + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_VECS0_VECS1_INTR_MASK)); + + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) + seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN12_VECS2_VECS3_INTR_MASK)); + + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", + intel_uncore_read(uncore, + GEN11_GPM_WGBOXPERF_INTR_MASK)); + seq_printf(m, "Crypto Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_CRYPTO_RSVD_INTR_MASK)); + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", + intel_uncore_read(uncore, + GEN11_GUNIT_CSME_INTR_MASK)); + + } else if (GRAPHICS_VER(i915) >= 6) { + for_each_engine(engine, gt, id) { + seq_printf(m, + "Graphics Interrupt mask (%s): %08x\n", + engine->name, ENGINE_READ(engine, RING_IMR)); + } + } + + intel_runtime_pm_put(uncore->rpm, wakeref); + + return 0; +} +DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info); + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root) +{ + static const struct intel_gt_debugfs_file files[] = { + { "interrupt_info", &interrupt_info_fops, NULL }, + }; + + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h new file mode 100644 index 000000000000..95e519705001 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef INTEL_GT_IRQ_DEBUGFS_H +#define INTEL_GT_IRQ_DEBUGFS_H + +struct intel_gt; +struct dentry; + +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root); + +#endif /* INTEL_GT_IRQ_DEBUGFS_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 5f84ad602642..c75af6f97e7e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -19,6 +19,36 @@ #include "intel_sideband.h" #include "intel_uncore.h" +static int forcewake_user_open(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + atomic_inc(>->user_wakeref); + intel_gt_pm_get(gt); + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_get(gt->uncore); + + return 0; +} + +static int forcewake_user_release(struct inode *inode, struct file *file) +{ + struct intel_gt *gt = inode->i_private; + + if (GRAPHICS_VER(gt->i915) >= 6) + intel_uncore_forcewake_user_put(gt->uncore); + intel_gt_pm_put(gt); + atomic_dec(>->user_wakeref); + + return 0; +} + +static const struct file_operations forcewake_user_fops = { + .owner = THIS_MODULE, + .open = forcewake_user_open, + .release = forcewake_user_release, +}; + static int fw_domains_show(struct seq_file *m, void *data) { struct intel_gt *gt = m->private; @@ -627,6 +657,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root) { "drpc", &drpc_fops, NULL }, { "frequency", &frequency_fops, NULL }, { "forcewake", &fw_domains_fops, NULL }, + { "forcewake_user", &forcewake_user_fops, NULL}, { "llc", &llc_fops, llc_eval }, { "rps_boost", &rps_boost_fops, rps_eval }, }; -- 2.27.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev8) 2021-10-07 23:09 ` [Intel-gfx] " Andi Shyti (?) @ 2021-10-08 2:14 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-10-08 2:14 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev8) URL : https://patchwork.freedesktop.org/series/75333/ State : warning == Summary == $ dim checkpatch origin/drm-tip 81673b413127 drm/i915/gt: move remaining debugfs interfaces into gt -:125: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #125: new file mode 100644 -:258: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #258: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:129: + intel_uncore_read(uncore, + GEN12_VCS4_VCS5_INTR_MASK)); -:262: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #262: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:133: + intel_uncore_read(uncore, + GEN12_VCS6_VCS7_INTR_MASK)); -:271: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #271: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:142: + intel_uncore_read(uncore, + GEN12_VECS2_VECS3_INTR_MASK)); total: 0 errors, 1 warnings, 3 checks, 310 lines checked ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev8) 2021-10-07 23:09 ` [Intel-gfx] " Andi Shyti (?) (?) @ 2021-10-08 2:47 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-10-08 2:47 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5611 bytes --] == Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev8) URL : https://patchwork.freedesktop.org/series/75333/ State : success == Summary == CI Bug Log - changes from CI_DRM_10696 -> Patchwork_21288 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/index.html Known issues ------------ Here are the changes found in Patchwork_21288 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +5 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html * igt@gem_huc_copy@huc-copy: - fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1372]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6700k2: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][10] ([i915#1888]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][12] ([i915#1888]) -> [PASS][13] +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html - fi-skl-6700k2: [INCOMPLETE][14] ([i915#146] / [i915#198]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-r: [DMESG-FAIL][16] ([i915#2291] / [i915#541]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [INCOMPLETE][18] ([i915#3921]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10696 -> Patchwork_21288 CI-20190529: 20190529 CI_DRM_10696: 58a206ae5bf2f81a11e4408d10a3e1b445d6eebb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6237: 910b5caac6625d2bf0b6c1dde502451431bd0159 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21288: 81673b41312795ac70b02e762c5c9605a3072181 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 81673b413127 drm/i915/gt: move remaining debugfs interfaces into gt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/index.html [-- Attachment #2: Type: text/html, Size: 6827 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev8) 2021-10-07 23:09 ` [Intel-gfx] " Andi Shyti ` (2 preceding siblings ...) (?) @ 2021-10-08 3:57 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2021-10-08 3:57 UTC (permalink / raw) To: Andi Shyti; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30284 bytes --] == Series Details == Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev8) URL : https://patchwork.freedesktop.org/series/75333/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10696_full -> Patchwork_21288_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21288_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21288_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21288_full: ### IGT changes ### #### Possible regressions #### * igt@kms_cursor_crc@pipe-d-cursor-64x21-random: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-64x21-random.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-64x21-random.html * igt@kms_invalid_mode@clock-too-high: - shard-tglb: NOTRUN -> [SKIP][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@kms_invalid_mode@clock-too-high.html Known issues ------------ Here are the changes found in Patchwork_21288_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@chamelium: - shard-tglb: NOTRUN -> [SKIP][4] ([fdo#111827]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@feature_discovery@chamelium.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html * igt@gem_ctx_sseu@invalid-args: - shard-tglb: NOTRUN -> [SKIP][8] ([i915#280]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@gem_ctx_sseu@invalid-args.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#3063] / [i915#3648]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@gem_eio@unwedge-stress.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@gem_eio@unwedge-stress.html - shard-skl: [PASS][11] -> [TIMEOUT][12] ([i915#2369] / [i915#3063]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl3/igt@gem_eio@unwedge-stress.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl7/igt@gem_eio@unwedge-stress.html - shard-snb: NOTRUN -> [FAIL][13] ([i915#3354]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: NOTRUN -> [FAIL][16] ([i915#2842]) +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_suspend@basic-s3: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl1/igt@gem_exec_suspend@basic-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl1/igt@gem_exec_suspend@basic-s3.html * igt@gem_huc_copy@huc-copy: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#2190]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl1/igt@gem_huc_copy@huc-copy.html * igt@gem_pread@exhaustion: - shard-snb: NOTRUN -> [WARN][22] ([i915#2658]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb2/igt@gem_pread@exhaustion.html - shard-skl: NOTRUN -> [WARN][23] ([i915#2658]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl7/igt@gem_pread@exhaustion.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][24] ([i915#2658]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@gem_pwrite@basic-exhaustion.html * igt@gem_pxp@protected-encrypted-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][25] ([i915#4270]) +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html * igt@gem_softpin@evict-snoop-interruptible: - shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109312]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-tglb: NOTRUN -> [SKIP][27] ([i915#3297]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb3/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@input-checking: - shard-snb: NOTRUN -> [DMESG-WARN][28] ([i915#3002]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb6/igt@gem_userptr_blits@input-checking.html * igt@gen3_render_linear_blits: - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#109289]) +5 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@gen3_render_linear_blits.html * igt@gen9_exec_parse@bb-start-param: - shard-tglb: NOTRUN -> [SKIP][30] ([i915#2856]) +3 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@gen9_exec_parse@bb-start-param.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-iclb: NOTRUN -> [SKIP][31] ([i915#2856]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb3/igt@gen9_exec_parse@cmd-crossing-page.html * igt@i915_module_load@reload-with-fault-injection: - shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@i915_module_load@reload-with-fault-injection.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl5/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc6-dpms: - shard-tglb: NOTRUN -> [FAIL][34] ([i915#454]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_rpm@modeset-non-lpsp: - shard-tglb: NOTRUN -> [SKIP][35] ([fdo#111644] / [i915#1397] / [i915#2411]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@i915_pm_rpm@modeset-non-lpsp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109506] / [i915#2411]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_query@query-topology-unsupported: - shard-tglb: NOTRUN -> [SKIP][37] ([fdo#109302]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@i915_query@query-topology-unsupported.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#198]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@i915_suspend@sysfs-reader.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl1/igt@i915_suspend@sysfs-reader.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: NOTRUN -> [FAIL][40] ([i915#2521]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111614]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][44] ([fdo#110723]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111615]) +8 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +3 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][47] ([i915#3689]) +12 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs: - shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271]) +392 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +3 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689] / [i915#3886]) +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: - shard-snb: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +15 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +10 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_color_chamelium@pipe-b-ctm-0-25: - shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-0-25.html * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue: - shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +10 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html * igt@kms_content_protection@atomic-dpms: - shard-tglb: NOTRUN -> [SKIP][56] ([fdo#111828]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@kms_content_protection@atomic-dpms.html * igt@kms_content_protection@srm: - shard-kbl: NOTRUN -> [TIMEOUT][57] ([i915#1319]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_content_protection@srm.html * igt@kms_content_protection@uevent: - shard-apl: NOTRUN -> [FAIL][58] ([i915#2105]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen: - shard-tglb: NOTRUN -> [SKIP][59] ([i915#3359]) +3 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-random: - shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109279] / [i915#3359]) +3 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding: - shard-tglb: NOTRUN -> [SKIP][61] ([i915#3319]) +5 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic: - shard-tglb: NOTRUN -> [SKIP][62] ([fdo#111825]) +45 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle: - shard-tglb: NOTRUN -> [SKIP][63] ([i915#4103]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html * igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a: - shard-tglb: NOTRUN -> [SKIP][64] ([i915#3788]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: NOTRUN -> [INCOMPLETE][65] ([i915#180] / [i915#1982]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html - shard-kbl: NOTRUN -> [INCOMPLETE][66] ([i915#180] / [i915#636]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1: - shard-tglb: [PASS][67] -> [FAIL][68] ([i915#79]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-edp1.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][69] -> [FAIL][70] ([i915#79]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate@a-edp1: - shard-skl: [PASS][71] -> [FAIL][72] ([i915#2122]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt: - shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271]) +23 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271]) +66 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265]) +2 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][77] -> [FAIL][78] ([fdo#108145] / [i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1: - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) +2 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2: - shard-tglb: NOTRUN -> [SKIP][81] ([i915#2920]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-tglb: NOTRUN -> [FAIL][82] ([i915#132] / [i915#3467]) +2 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][83] -> [SKIP][84] ([fdo#109441]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb6/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][85] -> [DMESG-WARN][86] ([i915#180] / [i915#295]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_writeback@writeback-pixel-formats: - shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2437]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html * igt@nouveau_crc@pipe-c-source-outp-complete: - shard-tglb: NOTRUN -> [SKIP][88] ([i915#2530]) +2 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@nouveau_crc@pipe-c-source-outp-complete.html * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name: - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271]) +159 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html * igt@prime_nv_pcopy@test3_1: - shard-tglb: NOTRUN -> [SKIP][90] ([fdo#109291]) +4 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@prime_nv_pcopy@test3_1.html * igt@prime_vgem@fence-read-hang: - shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109295]) +2 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@prime_vgem@fence-read-hang.html * igt@sysfs_clients@create: - shard-tglb: NOTRUN -> [SKIP][92] ([i915#2994]) +2 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@sysfs_clients@create.html - shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994]) +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl1/igt@sysfs_clients@create.html #### Possible fixes #### * igt@gem_exec_fair@basic-deadline: - shard-kbl: [FAIL][94] ([i915#2846]) -> [PASS][95] [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl6/igt@gem_exec_fair@basic-deadline.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl4/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [FAIL][96] ([i915#2842]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [FAIL][98] ([i915#2842]) -> [PASS][99] +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][100] ([i915#2842]) -> [PASS][101] +2 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][102] ([i915#2849]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_softpin@noreloc-s3: - shard-apl: [DMESG-WARN][104] ([i915#180]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl8/igt@gem_softpin@noreloc-s3.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-apl3/igt@gem_softpin@noreloc-s3.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [FAIL][106] ([i915#4275]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html * igt@i915_selftest@live@hangcheck: - shard-snb: [INCOMPLETE][108] ([i915#3921]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-snb2/igt@i915_selftest@live@hangcheck.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-snb5/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@forcewake: - shard-tglb: [INCOMPLETE][110] ([i915#2411] / [i915#456]) -> [PASS][111] +1 similar issue [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@i915_suspend@forcewake.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@i915_suspend@forcewake.html * igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a: - shard-skl: [DMESG-WARN][112] ([i915#1982]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl6/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-glk: [DMESG-WARN][114] ([i915#118]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-tglb: [INCOMPLETE][116] ([i915#2411] / [i915#4211]) -> [PASS][117] [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [FAIL][118] ([i915#79]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-suspend@a-edp1: - shard-tglb: [INCOMPLETE][120] ([i915#456]) -> [PASS][121] +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb6/igt@kms_flip@flip-vs-suspend@a-edp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1: - shard-skl: [FAIL][122] ([i915#2122]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][124] ([i915#1188]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-tglb: [INCOMPLETE][126] ([i915#4182]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-kbl: [DMESG-WARN][128] ([i915#180]) -> [PASS][129] +3 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][130] ([fdo#108145] / [i915#265]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][132] ([fdo#109441]) -> [PASS][133] +1 similar issue [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html * igt@perf@short-reads: - shard-skl: [FAIL][134] ([i915#51]) -> [PASS][135] [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl9/igt@perf@short-reads.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-skl10/igt@perf@short-reads.html #### Warnings #### * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-iclb: [SKIP][136] ([i915#2920]) -> [SKIP][137] ([i915#658]) +1 similar issue [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/shard-iclb7/igt@kms_psr2_sf@overlay-plane-u == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21288/index.html [-- Attachment #2: Type: text/html, Size: 33612 bytes --] ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt 2021-10-07 23:09 ` [Intel-gfx] " Andi Shyti @ 2021-10-08 6:47 ` Lucas De Marchi -1 siblings, 0 replies; 11+ messages in thread From: Lucas De Marchi @ 2021-10-08 6:47 UTC (permalink / raw) To: Andi Shyti Cc: Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Joonas Lahtinen On Thu, Oct 7, 2021 at 5:27 PM Andi Shyti <andi@etezian.org> wrote: > > From: Andi Shyti <andi.shyti@intel.com> > > The following interfaces: > > i915_wedged > i915_forcewake_user > i915_gem_interrupt > > are dependent on gt values. Put them inside gt/ and drop the > "i915_" prefix name. This would be the new structure: > > dri/0/gt > | > +-- forcewake_user > | > +-- interrupt_info > | > \-- reset > > For backwards compatibility with existing igt (and the slight > semantic difference between operating on the i915 abi entry > points and the deep gt info): > > dri/0 > | > +-- i915_wedged > | > \-- i915_forcewake_user > > remain at the top level. > > Signed-off-by: Andi Shyti <andi.shyti@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > Hi, > > I am reproposing this patch exactly as it was proposed initially > where the original interfaces are kept where they have been > originally placed. It might generate some duplicated code but, > well, it's debugfs and I don't see any issue. In the future we > can transform the upper interfaces to act upon all the GTs and > provide information from all the GTs. This is, for example, how > the sysfs interfaces will act. NACK. We've made this mistake in the past for other debugfs files. We don't want to do it again just to maintain 2 separate places for one year and then finally realize we want to merge them. > > The reason I removed them in V1 is because igt as only user is > not a strong reason to keep duplicated code, but as Chris > suggested offline: > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > changes to the interfaces it is using in any case, as you want > comparable results before/after the patches land. That doesn't mean you have to copy and paste it. It may mean you do the implementation in one of them and the other calls that implementation. See how I did the deduplication in commit d0c560316d6f ("drm/i915: deduplicate frequency dump on debugfs") Alternative would be to prepare igt already and then add a Test-with: in this patch series.... But I think it makes more sense to support both locations for some time and then later remove the previous one. Thanks Lucas De Marchi ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt @ 2021-10-08 6:47 ` Lucas De Marchi 0 siblings, 0 replies; 11+ messages in thread From: Lucas De Marchi @ 2021-10-08 6:47 UTC (permalink / raw) To: Andi Shyti Cc: Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Joonas Lahtinen On Thu, Oct 7, 2021 at 5:27 PM Andi Shyti <andi@etezian.org> wrote: > > From: Andi Shyti <andi.shyti@intel.com> > > The following interfaces: > > i915_wedged > i915_forcewake_user > i915_gem_interrupt > > are dependent on gt values. Put them inside gt/ and drop the > "i915_" prefix name. This would be the new structure: > > dri/0/gt > | > +-- forcewake_user > | > +-- interrupt_info > | > \-- reset > > For backwards compatibility with existing igt (and the slight > semantic difference between operating on the i915 abi entry > points and the deep gt info): > > dri/0 > | > +-- i915_wedged > | > \-- i915_forcewake_user > > remain at the top level. > > Signed-off-by: Andi Shyti <andi.shyti@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > Hi, > > I am reproposing this patch exactly as it was proposed initially > where the original interfaces are kept where they have been > originally placed. It might generate some duplicated code but, > well, it's debugfs and I don't see any issue. In the future we > can transform the upper interfaces to act upon all the GTs and > provide information from all the GTs. This is, for example, how > the sysfs interfaces will act. NACK. We've made this mistake in the past for other debugfs files. We don't want to do it again just to maintain 2 separate places for one year and then finally realize we want to merge them. > > The reason I removed them in V1 is because igt as only user is > not a strong reason to keep duplicated code, but as Chris > suggested offline: > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > changes to the interfaces it is using in any case, as you want > comparable results before/after the patches land. That doesn't mean you have to copy and paste it. It may mean you do the implementation in one of them and the other calls that implementation. See how I did the deduplication in commit d0c560316d6f ("drm/i915: deduplicate frequency dump on debugfs") Alternative would be to prepare igt already and then add a Test-with: in this patch series.... But I think it makes more sense to support both locations for some time and then later remove the previous one. Thanks Lucas De Marchi ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt 2021-10-08 6:47 ` [Intel-gfx] " Lucas De Marchi @ 2021-10-08 10:14 ` Andi Shyti -1 siblings, 0 replies; 11+ messages in thread From: Andi Shyti @ 2021-10-08 10:14 UTC (permalink / raw) To: Lucas De Marchi Cc: Andi Shyti, Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Joonas Lahtinen Hi Lucas, > > I am reproposing this patch exactly as it was proposed initially > > where the original interfaces are kept where they have been > > originally placed. It might generate some duplicated code but, > > well, it's debugfs and I don't see any issue. In the future we > > can transform the upper interfaces to act upon all the GTs and > > provide information from all the GTs. This is, for example, how > > the sysfs interfaces will act. > > NACK. We've made this mistake in the past for other debugfs files. > We don't want to do it again just to maintain 2 separate places for > one year and then finally realize we want to merge them. In my opinion it's all about what mistake you like the most because until we will have multi-gt support in upstream all the patches come with the "promise" of a follow-up and maintenance cost. > > The reason I removed them in V1 is because igt as only user is > > not a strong reason to keep duplicated code, but as Chris > > suggested offline: > > > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > > changes to the interfaces it is using in any case, as you want > > comparable results before/after the patches land. > > That doesn't mean you have to copy and paste it. It may mean you > do the implementation in one of them and the other calls that implementation. > See how I did the deduplication in commit d0c560316d6f ("drm/i915: > deduplicate frequency dump on debugfs") In this case, from a user perspective, which gt is the interface affecting? is it affecting all the system? or gt 0, 1...? Does the user know? The maintenance cost is that later you will need to use for_each_gt and make all those interfaces multitile, and this would be your "promise". How are you going to do it then? Will every interface iterate and perform its own action? When you read, whad do you read? all the gt values in 'or'? in 'and'? Is there any common strategy? Or will we have inconsistent behaviors? In sysfs (where we are left with the same questions) some times ago I proposoed a common solution for all the upper level files in order to provide the user with a consistent interface all along the GTs. This is my "promise" and until then it's just a matter of what promise and what mistake you like the most. > Alternative would be to prepare igt already and then add a Test-with: > in this patch > series.... But I think it makes more sense to support both locations > for some time and then later > remove the previous one. Anyway, I can sure do something similar to how you did it, it might look prettier but it doesn't exclude a follow-up improvement. Thanks for the review, Andi ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt @ 2021-10-08 10:14 ` Andi Shyti 0 siblings, 0 replies; 11+ messages in thread From: Andi Shyti @ 2021-10-08 10:14 UTC (permalink / raw) To: Lucas De Marchi Cc: Andi Shyti, Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Joonas Lahtinen Hi Lucas, > > I am reproposing this patch exactly as it was proposed initially > > where the original interfaces are kept where they have been > > originally placed. It might generate some duplicated code but, > > well, it's debugfs and I don't see any issue. In the future we > > can transform the upper interfaces to act upon all the GTs and > > provide information from all the GTs. This is, for example, how > > the sysfs interfaces will act. > > NACK. We've made this mistake in the past for other debugfs files. > We don't want to do it again just to maintain 2 separate places for > one year and then finally realize we want to merge them. In my opinion it's all about what mistake you like the most because until we will have multi-gt support in upstream all the patches come with the "promise" of a follow-up and maintenance cost. > > The reason I removed them in V1 is because igt as only user is > > not a strong reason to keep duplicated code, but as Chris > > suggested offline: > > > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > > changes to the interfaces it is using in any case, as you want > > comparable results before/after the patches land. > > That doesn't mean you have to copy and paste it. It may mean you > do the implementation in one of them and the other calls that implementation. > See how I did the deduplication in commit d0c560316d6f ("drm/i915: > deduplicate frequency dump on debugfs") In this case, from a user perspective, which gt is the interface affecting? is it affecting all the system? or gt 0, 1...? Does the user know? The maintenance cost is that later you will need to use for_each_gt and make all those interfaces multitile, and this would be your "promise". How are you going to do it then? Will every interface iterate and perform its own action? When you read, whad do you read? all the gt values in 'or'? in 'and'? Is there any common strategy? Or will we have inconsistent behaviors? In sysfs (where we are left with the same questions) some times ago I proposoed a common solution for all the upper level files in order to provide the user with a consistent interface all along the GTs. This is my "promise" and until then it's just a matter of what promise and what mistake you like the most. > Alternative would be to prepare igt already and then add a Test-with: > in this patch > series.... But I think it makes more sense to support both locations > for some time and then later > remove the previous one. Anyway, I can sure do something similar to how you did it, it might look prettier but it doesn't exclude a follow-up improvement. Thanks for the review, Andi ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt 2021-10-08 10:14 ` [Intel-gfx] " Andi Shyti @ 2021-10-08 23:51 ` Lucas De Marchi -1 siblings, 0 replies; 11+ messages in thread From: Lucas De Marchi @ 2021-10-08 23:51 UTC (permalink / raw) To: Andi Shyti Cc: Andi Shyti, Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Joonas Lahtinen On Fri, Oct 8, 2021 at 3:14 AM Andi Shyti <andi.shyti@intel.com> wrote: > > Hi Lucas, > > > > I am reproposing this patch exactly as it was proposed initially > > > where the original interfaces are kept where they have been > > > originally placed. It might generate some duplicated code but, > > > well, it's debugfs and I don't see any issue. In the future we > > > can transform the upper interfaces to act upon all the GTs and > > > provide information from all the GTs. This is, for example, how > > > the sysfs interfaces will act. > > > > NACK. We've made this mistake in the past for other debugfs files. > > We don't want to do it again just to maintain 2 separate places for > > one year and then finally realize we want to merge them. > > In my opinion it's all about what mistake you like the most > because until we will have multi-gt support in upstream all the > patches come with the "promise" of a follow-up and maintenance > cost. no. If you put the implementation in a single place, later you only have the decision on what to do with the per-device entrypoint: - should we remove it once igt is converted? - should we make it iterate all gts? - should we make it mean root tile? Then you take the action that is needed and decide it per interface. Here you are leaving behind a lot of code that we will need to maintain until there is support for such a thing. It already happened once: we needed to maintain that duplicated code for over a year with multiple patches changing them (or failing to do so). > > > > The reason I removed them in V1 is because igt as only user is > > > not a strong reason to keep duplicated code, but as Chris > > > suggested offline: > > > > > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > > > changes to the interfaces it is using in any case, as you want > > > comparable results before/after the patches land. > > > > That doesn't mean you have to copy and paste it. It may mean you > > do the implementation in one of them and the other calls that implementation. > > See how I did the deduplication in commit d0c560316d6f ("drm/i915: > > deduplicate frequency dump on debugfs") > > In this case, from a user perspective, which gt is the interface > affecting? is it affecting all the system? or gt 0, 1...? Does > the user know? The maintenance cost is that later you will need > to use for_each_gt and make all those interfaces multitile, and > this would be your "promise". multi-gt is irrelevant here. This patch without any "promise" should do what the commit message says: *move*. The only reason to keep the old entrypoint around is because it's missing the igt conversion. If you are going to support a per-device entrypoint and do for_each_gt(), or do a symlink to the root tile, or whatever, it isn't very relevant to this patch. Right now we have just a single directory, gt. Lucas De Marchi ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt @ 2021-10-08 23:51 ` Lucas De Marchi 0 siblings, 0 replies; 11+ messages in thread From: Lucas De Marchi @ 2021-10-08 23:51 UTC (permalink / raw) To: Andi Shyti Cc: Andi Shyti, Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Joonas Lahtinen On Fri, Oct 8, 2021 at 3:14 AM Andi Shyti <andi.shyti@intel.com> wrote: > > Hi Lucas, > > > > I am reproposing this patch exactly as it was proposed initially > > > where the original interfaces are kept where they have been > > > originally placed. It might generate some duplicated code but, > > > well, it's debugfs and I don't see any issue. In the future we > > > can transform the upper interfaces to act upon all the GTs and > > > provide information from all the GTs. This is, for example, how > > > the sysfs interfaces will act. > > > > NACK. We've made this mistake in the past for other debugfs files. > > We don't want to do it again just to maintain 2 separate places for > > one year and then finally realize we want to merge them. > > In my opinion it's all about what mistake you like the most > because until we will have multi-gt support in upstream all the > patches come with the "promise" of a follow-up and maintenance > cost. no. If you put the implementation in a single place, later you only have the decision on what to do with the per-device entrypoint: - should we remove it once igt is converted? - should we make it iterate all gts? - should we make it mean root tile? Then you take the action that is needed and decide it per interface. Here you are leaving behind a lot of code that we will need to maintain until there is support for such a thing. It already happened once: we needed to maintain that duplicated code for over a year with multiple patches changing them (or failing to do so). > > > > The reason I removed them in V1 is because igt as only user is > > > not a strong reason to keep duplicated code, but as Chris > > > suggested offline: > > > > > > "It's debugfs, igt is the primary consumer. CI has to be bridged over > > > changes to the interfaces it is using in any case, as you want > > > comparable results before/after the patches land. > > > > That doesn't mean you have to copy and paste it. It may mean you > > do the implementation in one of them and the other calls that implementation. > > See how I did the deduplication in commit d0c560316d6f ("drm/i915: > > deduplicate frequency dump on debugfs") > > In this case, from a user perspective, which gt is the interface > affecting? is it affecting all the system? or gt 0, 1...? Does > the user know? The maintenance cost is that later you will need > to use for_each_gt and make all those interfaces multitile, and > this would be your "promise". multi-gt is irrelevant here. This patch without any "promise" should do what the commit message says: *move*. The only reason to keep the old entrypoint around is because it's missing the igt conversion. If you are going to support a per-device entrypoint and do for_each_gt(), or do a symlink to the root tile, or whatever, it isn't very relevant to this patch. Right now we have just a single directory, gt. Lucas De Marchi ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-10-08 23:51 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-07 23:09 [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt Andi Shyti 2021-10-07 23:09 ` [Intel-gfx] " Andi Shyti 2021-10-08 2:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev8) Patchwork 2021-10-08 2:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-10-08 3:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2021-10-08 6:47 ` [PATCH v2] drm/i915/gt: move remaining debugfs interfaces into gt Lucas De Marchi 2021-10-08 6:47 ` [Intel-gfx] " Lucas De Marchi 2021-10-08 10:14 ` Andi Shyti 2021-10-08 10:14 ` [Intel-gfx] " Andi Shyti 2021-10-08 23:51 ` Lucas De Marchi 2021-10-08 23:51 ` Lucas De Marchi
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