* [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
@ 2021-10-08 11:27 ` Andi Shyti
0 siblings, 0 replies; 7+ messages in thread
From: Andi Shyti @ 2021-10-08 11:27 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti
From: Andi Shyti <andi.shyti@intel.com>
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):
dri/0
|
+-- i915_wedged
|
\-- i915_forcewake_user
remain at the top level.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
Hi Lucas and Chris,
this third version tries to remove duplicated code, but roughly
the amount of code removed is equal to the amount of code added.
In my opinion it doesn't improve much the code. Amongst the three
versions I still prefer the v2.
Changelog:
----------
v2 -> v3: https://patchwork.freedesktop.org/patch/458108/
* keep the original interfaces as they were (thanks Chris) but
implement the functionality inside the gt. The upper level
files will call the gt functions (thanks Lucas).
v1 -> v2: https://patchwork.freedesktop.org/patch/456652/
* keep the original interfaces intact (thanks Chris).
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h | 4 +
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 41 ++++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 4 +
drivers/gpu/drm/i915/i915_debugfs.c | 43 +----
8 files changed, 296 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cdc244bbbfc1..e92984954ba8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -98,6 +98,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 1fe19ccd2794..0d651c33110d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,11 +8,54 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >->reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", &reset_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>->uc, root);
intel_pxp_debugfs_register(>->pxp, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
index 8b6fca09897c..6bc4f044c23f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
@@ -35,4 +35,8 @@ void intel_gt_debugfs_register_files(struct dentry *root,
const struct intel_gt_debugfs_file *files,
unsigned long count, void *data);
+/* functions that need to be accessed by the upper level non-gt interfaces */
+int reset_show(void *data, u64 *val);
+int reset_store(void *data, u64 val);
+
#endif /* INTEL_GT_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
new file mode 100644
index 000000000000..3cf9ae8437e5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+
+static int interrupt_info_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ int i;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ if (IS_CHERRYVIEW(i915)) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "Master Interrupt Control: %08x\n",
+ intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
+
+ seq_printf(m, "Render/Copy Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RENDER_COPY_INTR_ENABLE));
+ seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS_VECS_INTR_ENABLE));
+ seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_ENABLE));
+ seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+ seq_printf(m, "Crypto Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_ENABLE));
+ seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_ENABLE));
+
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (IS_VALLEYVIEW(i915)) {
+ seq_printf(m, "Master IER:\t%08x\n",
+ intel_uncore_read(uncore, VLV_MASTER_IER));
+
+ seq_printf(m, "Render IER:\t%08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Render IIR:\t%08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Render IMR:\t%08x\n",
+ intel_uncore_read(uncore, GTIMR));
+
+ seq_printf(m, "PM IER:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIER));
+ seq_printf(m, "PM IIR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIIR));
+ seq_printf(m, "PM IMR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIMR));
+
+ } else if (!HAS_PCH_SPLIT(i915)) {
+ seq_printf(m, "Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GEN2_IER));
+ seq_printf(m, "Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GEN2_IIR));
+ seq_printf(m, "Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GEN2_IMR));
+ } else {
+ seq_printf(m, "Graphics Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Graphics Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Graphics Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GTIMR));
+ }
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "RCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RCS0_RSVD_INTR_MASK));
+ seq_printf(m, "BCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_BCS_RSVD_INTR_MASK));
+ seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS0_VCS1_INTR_MASK));
+ seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS2_VCS3_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
+ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
+ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
+
+ seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VECS0_VECS1_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
+ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
+
+ seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_MASK));
+ seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_MASK));
+ seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_MASK));
+ seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_MASK));
+
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ for_each_engine(engine, gt, id) {
+ seq_printf(m,
+ "Graphics Interrupt mask (%s): %08x\n",
+ engine->name, ENGINE_READ(engine, RING_IMR));
+ }
+ }
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return 0;
+}
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "interrupt_info", &interrupt_info_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
new file mode 100644
index 000000000000..95e519705001
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef INTEL_GT_IRQ_DEBUGFS_H
+#define INTEL_GT_IRQ_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_IRQ_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5f84ad602642..712c91d588eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -19,6 +19,46 @@
#include "intel_sideband.h"
#include "intel_uncore.h"
+int __forcewake_user_open(struct intel_gt *gt)
+{
+ atomic_inc(>->user_wakeref);
+ intel_gt_pm_get(gt);
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
+
+ return 0;
+}
+
+int __forcewake_user_release(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_put(gt->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>->user_wakeref);
+
+ return 0;
+}
+
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ return __forcewake_user_open(gt);
+}
+
+static int forcewake_user_release(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ return __forcewake_user_release(gt);
+}
+
+static const struct file_operations forcewake_user_fops = {
+ .owner = THIS_MODULE,
+ .open = forcewake_user_open,
+ .release = forcewake_user_release,
+};
+
static int fw_domains_show(struct seq_file *m, void *data)
{
struct intel_gt *gt = m->private;
@@ -627,6 +667,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{ "drpc", &drpc_fops, NULL },
{ "frequency", &frequency_fops, NULL },
{ "forcewake", &fw_domains_fops, NULL },
+ { "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
};
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
index 2b824289582b..fe306412b996 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
@@ -13,4 +13,8 @@ struct drm_printer;
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root);
void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m);
+/* functions that need to be accessed by the upper level non-gt interfaces */
+int __forcewake_user_open(struct intel_gt *gt);
+int __forcewake_user_release(struct intel_gt *gt);
+
#endif /* INTEL_GT_PM_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..fd7f5bd5f304 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -35,6 +35,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_debugfs.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_pm_debugfs.h"
#include "gt/intel_gt_requests.h"
@@ -554,36 +555,18 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
return 0;
}
-static int
-i915_wedged_get(void *data, u64 *val)
+static int i915_wedged_get(void *data, u64 *val)
{
struct drm_i915_private *i915 = data;
- int ret = intel_gt_terminally_wedged(&i915->gt);
- switch (ret) {
- case -EIO:
- *val = 1;
- return 0;
- case 0:
- *val = 0;
- return 0;
- default:
- return ret;
- }
+ return reset_show(&i915->gt, val);
}
-static int
-i915_wedged_set(void *data, u64 val)
+static int i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- /* Flush any previous reset before applying for a new one */
- wait_event(i915->gt.reset.queue,
- !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
-
- intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
- "Manually set wedged engine mask = %llx", val);
- return 0;
+ return reset_store(&i915->gt, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
@@ -728,27 +711,15 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- atomic_inc(>->user_wakeref);
- intel_gt_pm_get(gt);
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_get(gt->uncore);
- return 0;
+ return __forcewake_user_open(&i915->gt);
}
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_put(&i915->uncore);
- intel_gt_pm_put(gt);
- atomic_dec(>->user_wakeref);
-
- return 0;
+ return __forcewake_user_release(&i915->gt);
}
static const struct file_operations i915_forcewake_fops = {
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
@ 2021-10-08 11:27 ` Andi Shyti
0 siblings, 0 replies; 7+ messages in thread
From: Andi Shyti @ 2021-10-08 11:27 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Tvrtko Ursulin, Chris Wilson, Lucas De Marchi, Andi Shyti, Andi Shyti
From: Andi Shyti <andi.shyti@intel.com>
The following interfaces:
i915_wedged
i915_forcewake_user
i915_gem_interrupt
are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:
dri/0/gt
|
+-- forcewake_user
|
+-- interrupt_info
|
\-- reset
For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):
dri/0
|
+-- i915_wedged
|
\-- i915_forcewake_user
remain at the top level.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
Hi Lucas and Chris,
this third version tries to remove duplicated code, but roughly
the amount of code removed is equal to the amount of code added.
In my opinion it doesn't improve much the code. Amongst the three
versions I still prefer the v2.
Changelog:
----------
v2 -> v3: https://patchwork.freedesktop.org/patch/458108/
* keep the original interfaces as they were (thanks Chris) but
implement the functionality inside the gt. The upper level
files will call the gt functions (thanks Lucas).
v1 -> v2: https://patchwork.freedesktop.org/patch/456652/
* keep the original interfaces intact (thanks Chris).
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 47 ++++-
drivers/gpu/drm/i915/gt/intel_gt_debugfs.h | 4 +
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.c | 178 ++++++++++++++++++
.../gpu/drm/i915/gt/intel_gt_irq_debugfs.h | 15 ++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 41 ++++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 4 +
drivers/gpu/drm/i915/i915_debugfs.c | 43 +----
8 files changed, 296 insertions(+), 37 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index cdc244bbbfc1..e92984954ba8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -98,6 +98,7 @@ gt-y += \
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
gt/intel_gt_irq.o \
+ gt/intel_gt_irq_debugfs.o \
gt/intel_gt_pm.o \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 1fe19ccd2794..0d651c33110d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -8,11 +8,54 @@
#include "i915_drv.h"
#include "intel_gt_debugfs.h"
#include "intel_gt_engines_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+#include "intel_gt_pm.h"
#include "intel_gt_pm_debugfs.h"
+#include "intel_gt_requests.h"
#include "intel_sseu_debugfs.h"
#include "pxp/intel_pxp_debugfs.h"
#include "uc/intel_uc_debugfs.h"
+int reset_show(void *data, u64 *val)
+{
+ struct intel_gt *gt = data;
+ int ret = intel_gt_terminally_wedged(gt);
+
+ switch (ret) {
+ case -EIO:
+ *val = 1;
+ return 0;
+ case 0:
+ *val = 0;
+ return 0;
+ default:
+ return ret;
+ }
+}
+
+int reset_store(void *data, u64 val)
+{
+ struct intel_gt *gt = data;
+
+ /* Flush any previous reset before applying for a new one */
+ wait_event(gt->reset.queue,
+ !test_bit(I915_RESET_BACKOFF, >->reset.flags));
+
+ intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+ "Manually reset engine mask to %llx", val);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "reset", &reset_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
+
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
@@ -24,10 +67,12 @@ void intel_gt_debugfs_register(struct intel_gt *gt)
if (IS_ERR(root))
return;
+ gt_debugfs_register(gt, root);
+
intel_gt_engines_debugfs_register(gt, root);
intel_gt_pm_debugfs_register(gt, root);
+ intel_gt_irq_debugfs_register(gt, root);
intel_sseu_debugfs_register(gt, root);
-
intel_uc_debugfs_register(>->uc, root);
intel_pxp_debugfs_register(>->pxp, root);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
index 8b6fca09897c..6bc4f044c23f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
@@ -35,4 +35,8 @@ void intel_gt_debugfs_register_files(struct dentry *root,
const struct intel_gt_debugfs_file *files,
unsigned long count, void *data);
+/* functions that need to be accessed by the upper level non-gt interfaces */
+int reset_show(void *data, u64 *val);
+int reset_store(void *data, u64 val);
+
#endif /* INTEL_GT_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
new file mode 100644
index 000000000000..3cf9ae8437e5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt_debugfs.h"
+#include "intel_gt_irq_debugfs.h"
+
+static int interrupt_info_show(struct seq_file *m, void *data)
+{
+ struct intel_gt *gt = m->private;
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore = gt->uncore;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ int i;
+
+ wakeref = intel_runtime_pm_get(uncore->rpm);
+
+ if (IS_CHERRYVIEW(i915)) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "Master Interrupt Control: %08x\n",
+ intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
+
+ seq_printf(m, "Render/Copy Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RENDER_COPY_INTR_ENABLE));
+ seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS_VECS_INTR_ENABLE));
+ seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_ENABLE));
+ seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+ seq_printf(m, "Crypto Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_ENABLE));
+ seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_ENABLE));
+
+ } else if (GRAPHICS_VER(i915) >= 8) {
+ seq_printf(m, "Master Interrupt Control:\t%08x\n",
+ intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+ for (i = 0; i < 4; i++) {
+ seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IMR(i)));
+ seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IIR(i)));
+ seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+ i, intel_uncore_read(uncore,
+ GEN8_GT_IER(i)));
+ }
+
+ } else if (IS_VALLEYVIEW(i915)) {
+ seq_printf(m, "Master IER:\t%08x\n",
+ intel_uncore_read(uncore, VLV_MASTER_IER));
+
+ seq_printf(m, "Render IER:\t%08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Render IIR:\t%08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Render IMR:\t%08x\n",
+ intel_uncore_read(uncore, GTIMR));
+
+ seq_printf(m, "PM IER:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIER));
+ seq_printf(m, "PM IIR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIIR));
+ seq_printf(m, "PM IMR:\t\t%08x\n",
+ intel_uncore_read(uncore, GEN6_PMIMR));
+
+ } else if (!HAS_PCH_SPLIT(i915)) {
+ seq_printf(m, "Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GEN2_IER));
+ seq_printf(m, "Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GEN2_IIR));
+ seq_printf(m, "Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GEN2_IMR));
+ } else {
+ seq_printf(m, "Graphics Interrupt enable: %08x\n",
+ intel_uncore_read(uncore, GTIER));
+ seq_printf(m, "Graphics Interrupt identity: %08x\n",
+ intel_uncore_read(uncore, GTIIR));
+ seq_printf(m, "Graphics Interrupt mask: %08x\n",
+ intel_uncore_read(uncore, GTIMR));
+ }
+
+ if (GRAPHICS_VER(i915) >= 11) {
+ seq_printf(m, "RCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_RCS0_RSVD_INTR_MASK));
+ seq_printf(m, "BCS Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_BCS_RSVD_INTR_MASK));
+ seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS0_VCS1_INTR_MASK));
+ seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VCS2_VCS3_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
+ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
+ if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
+ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
+
+ seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_VECS0_VECS1_INTR_MASK));
+
+ if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
+ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
+
+ seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUC_SG_INTR_MASK));
+ seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GPM_WGBOXPERF_INTR_MASK));
+ seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_CRYPTO_RSVD_INTR_MASK));
+ seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+ intel_uncore_read(uncore,
+ GEN11_GUNIT_CSME_INTR_MASK));
+
+ } else if (GRAPHICS_VER(i915) >= 6) {
+ for_each_engine(engine, gt, id) {
+ seq_printf(m,
+ "Graphics Interrupt mask (%s): %08x\n",
+ engine->name, ENGINE_READ(engine, RING_IMR));
+ }
+ }
+
+ intel_runtime_pm_put(uncore->rpm, wakeref);
+
+ return 0;
+}
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root)
+{
+ static const struct intel_gt_debugfs_file files[] = {
+ { "interrupt_info", &interrupt_info_fops, NULL },
+ };
+
+ intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
new file mode 100644
index 000000000000..95e519705001
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef INTEL_GT_IRQ_DEBUGFS_H
+#define INTEL_GT_IRQ_DEBUGFS_H
+
+struct intel_gt;
+struct dentry;
+
+void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root);
+
+#endif /* INTEL_GT_IRQ_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5f84ad602642..712c91d588eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -19,6 +19,46 @@
#include "intel_sideband.h"
#include "intel_uncore.h"
+int __forcewake_user_open(struct intel_gt *gt)
+{
+ atomic_inc(>->user_wakeref);
+ intel_gt_pm_get(gt);
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_get(gt->uncore);
+
+ return 0;
+}
+
+int __forcewake_user_release(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) >= 6)
+ intel_uncore_forcewake_user_put(gt->uncore);
+ intel_gt_pm_put(gt);
+ atomic_dec(>->user_wakeref);
+
+ return 0;
+}
+
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ return __forcewake_user_open(gt);
+}
+
+static int forcewake_user_release(struct inode *inode, struct file *file)
+{
+ struct intel_gt *gt = inode->i_private;
+
+ return __forcewake_user_release(gt);
+}
+
+static const struct file_operations forcewake_user_fops = {
+ .owner = THIS_MODULE,
+ .open = forcewake_user_open,
+ .release = forcewake_user_release,
+};
+
static int fw_domains_show(struct seq_file *m, void *data)
{
struct intel_gt *gt = m->private;
@@ -627,6 +667,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
{ "drpc", &drpc_fops, NULL },
{ "frequency", &frequency_fops, NULL },
{ "forcewake", &fw_domains_fops, NULL },
+ { "forcewake_user", &forcewake_user_fops, NULL},
{ "llc", &llc_fops, llc_eval },
{ "rps_boost", &rps_boost_fops, rps_eval },
};
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
index 2b824289582b..fe306412b996 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
@@ -13,4 +13,8 @@ struct drm_printer;
void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root);
void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m);
+/* functions that need to be accessed by the upper level non-gt interfaces */
+int __forcewake_user_open(struct intel_gt *gt);
+int __forcewake_user_release(struct intel_gt *gt);
+
#endif /* INTEL_GT_PM_DEBUGFS_H */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..fd7f5bd5f304 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -35,6 +35,7 @@
#include "gt/intel_gt.h"
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_debugfs.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_pm_debugfs.h"
#include "gt/intel_gt_requests.h"
@@ -554,36 +555,18 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
return 0;
}
-static int
-i915_wedged_get(void *data, u64 *val)
+static int i915_wedged_get(void *data, u64 *val)
{
struct drm_i915_private *i915 = data;
- int ret = intel_gt_terminally_wedged(&i915->gt);
- switch (ret) {
- case -EIO:
- *val = 1;
- return 0;
- case 0:
- *val = 0;
- return 0;
- default:
- return ret;
- }
+ return reset_show(&i915->gt, val);
}
-static int
-i915_wedged_set(void *data, u64 val)
+static int i915_wedged_set(void *data, u64 val)
{
struct drm_i915_private *i915 = data;
- /* Flush any previous reset before applying for a new one */
- wait_event(i915->gt.reset.queue,
- !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
-
- intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
- "Manually set wedged engine mask = %llx", val);
- return 0;
+ return reset_store(&i915->gt, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
@@ -728,27 +711,15 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
-
- atomic_inc(>->user_wakeref);
- intel_gt_pm_get(gt);
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_get(gt->uncore);
- return 0;
+ return __forcewake_user_open(&i915->gt);
}
static int i915_forcewake_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- struct intel_gt *gt = &i915->gt;
- if (GRAPHICS_VER(i915) >= 6)
- intel_uncore_forcewake_user_put(&i915->uncore);
- intel_gt_pm_put(gt);
- atomic_dec(>->user_wakeref);
-
- return 0;
+ return __forcewake_user_release(&i915->gt);
}
static const struct file_operations i915_forcewake_fops = {
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
2021-10-08 11:27 ` Andi Shyti
(?)
@ 2021-10-08 16:24 ` Patchwork
-1 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-10-08 16:24 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
997777b302f7 drm/i915/gt: move remaining debugfs interfaces into gt
-:138: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#138:
new file mode 100644
-:271: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#271: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:129:
+ intel_uncore_read(uncore,
+ GEN12_VCS4_VCS5_INTR_MASK));
-:275: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#275: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:133:
+ intel_uncore_read(uncore,
+ GEN12_VCS6_VCS7_INTR_MASK));
-:284: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#284: FILE: drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.c:142:
+ intel_uncore_read(uncore,
+ GEN12_VECS2_VECS3_INTR_MASK));
total: 0 errors, 1 warnings, 3 checks, 412 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
2021-10-08 11:27 ` Andi Shyti
(?)
(?)
@ 2021-10-08 16:42 ` Ville Syrjälä
2021-10-08 20:46 ` Andi Shyti
-1 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjälä @ 2021-10-08 16:42 UTC (permalink / raw)
To: Andi Shyti
Cc: Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson,
Lucas De Marchi, Andi Shyti
On Fri, Oct 08, 2021 at 01:27:33PM +0200, Andi Shyti wrote:
> +
> + if (IS_CHERRYVIEW(i915)) {
> + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> + intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> +
> + for (i = 0; i < 4; i++) {
> + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IMR(i)));
> + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IIR(i)));
> + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IER(i)));
> + }
> +
Why does chv get its own block? Looks identical to the bdw block.
> + } else if (GRAPHICS_VER(i915) >= 11) {
> + seq_printf(m, "Master Interrupt Control: %08x\n",
> + intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
> +
> + seq_printf(m, "Render/Copy Intr Enable: %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_RENDER_COPY_INTR_ENABLE));
> + seq_printf(m, "VCS/VECS Intr Enable: %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_VCS_VECS_INTR_ENABLE));
> + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GUC_SG_INTR_ENABLE));
> + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GPM_WGBOXPERF_INTR_ENABLE));
> + seq_printf(m, "Crypto Intr Enable:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_CRYPTO_RSVD_INTR_ENABLE));
> + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GUNIT_CSME_INTR_ENABLE));
> +
> + } else if (GRAPHICS_VER(i915) >= 8) {
> + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> + intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> +
> + for (i = 0; i < 4; i++) {
> + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IMR(i)));
> + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IIR(i)));
> + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> + i, intel_uncore_read(uncore,
> + GEN8_GT_IER(i)));
> + }
> +
> + } else if (IS_VALLEYVIEW(i915)) {
> + seq_printf(m, "Master IER:\t%08x\n",
> + intel_uncore_read(uncore, VLV_MASTER_IER));
> +
> + seq_printf(m, "Render IER:\t%08x\n",
> + intel_uncore_read(uncore, GTIER));
> + seq_printf(m, "Render IIR:\t%08x\n",
> + intel_uncore_read(uncore, GTIIR));
> + seq_printf(m, "Render IMR:\t%08x\n",
> + intel_uncore_read(uncore, GTIMR));
> +
> + seq_printf(m, "PM IER:\t\t%08x\n",
> + intel_uncore_read(uncore, GEN6_PMIER));
> + seq_printf(m, "PM IIR:\t\t%08x\n",
> + intel_uncore_read(uncore, GEN6_PMIIR));
> + seq_printf(m, "PM IMR:\t\t%08x\n",
> + intel_uncore_read(uncore, GEN6_PMIMR));
> +
> + } else if (!HAS_PCH_SPLIT(i915)) {
HAS_PCH_SPLIT in gt code looks a bit out of place.
> + seq_printf(m, "Interrupt enable: %08x\n",
> + intel_uncore_read(uncore, GEN2_IER));
> + seq_printf(m, "Interrupt identity: %08x\n",
> + intel_uncore_read(uncore, GEN2_IIR));
> + seq_printf(m, "Interrupt mask: %08x\n",
> + intel_uncore_read(uncore, GEN2_IMR));
Technically on gen2 these are 16 bits, on gen3+ 32 bits. I don't
quite remember now what happens when you read them as 32bit on gen2.
Might be the msbs just come out all zeroes.
> + } else {
> + seq_printf(m, "Graphics Interrupt enable: %08x\n",
> + intel_uncore_read(uncore, GTIER));
> + seq_printf(m, "Graphics Interrupt identity: %08x\n",
> + intel_uncore_read(uncore, GTIIR));
> + seq_printf(m, "Graphics Interrupt mask: %08x\n",
> + intel_uncore_read(uncore, GTIMR));
Probably this should be before the previous block to keep things in
order. Also missing GEN6_PM stuff for snb+, and the master interrupt
stuff for ilk+.
> + }
> +
> + if (GRAPHICS_VER(i915) >= 11) {
> + seq_printf(m, "RCS Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_RCS0_RSVD_INTR_MASK));
> + seq_printf(m, "BCS Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_BCS_RSVD_INTR_MASK));
> + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_VCS0_VCS1_INTR_MASK));
> + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_VCS2_VCS3_INTR_MASK));
> +
> + if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
> + seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN12_VCS4_VCS5_INTR_MASK));
> + if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
> + seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN12_VCS6_VCS7_INTR_MASK));
> +
> + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_VECS0_VECS1_INTR_MASK));
> +
> + if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
> + seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN12_VECS2_VECS3_INTR_MASK));
> +
> + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GUC_SG_INTR_MASK));
> + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GPM_WGBOXPERF_INTR_MASK));
> + seq_printf(m, "Crypto Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_CRYPTO_RSVD_INTR_MASK));
> + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
> + intel_uncore_read(uncore,
> + GEN11_GUNIT_CSME_INTR_MASK));
> +
> + } else if (GRAPHICS_VER(i915) >= 6) {
> + for_each_engine(engine, gt, id) {
> + seq_printf(m,
> + "Graphics Interrupt mask (%s): %08x\n",
> + engine->name, ENGINE_READ(engine, RING_IMR));
> + }
> + }
> +
> + intel_runtime_pm_put(uncore->rpm, wakeref);
> +
> + return 0;
> +}
> +DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
> +
> +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root)
> +{
> + static const struct intel_gt_debugfs_file files[] = {
> + { "interrupt_info", &interrupt_info_fops, NULL },
> + };
> +
> + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
> new file mode 100644
> index 000000000000..95e519705001
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq_debugfs.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#ifndef INTEL_GT_IRQ_DEBUGFS_H
> +#define INTEL_GT_IRQ_DEBUGFS_H
> +
> +struct intel_gt;
> +struct dentry;
> +
> +void intel_gt_irq_debugfs_register(struct intel_gt *gt, struct dentry *root);
> +
> +#endif /* INTEL_GT_IRQ_DEBUGFS_H */
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 5f84ad602642..712c91d588eb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -19,6 +19,46 @@
> #include "intel_sideband.h"
> #include "intel_uncore.h"
>
> +int __forcewake_user_open(struct intel_gt *gt)
> +{
> + atomic_inc(>->user_wakeref);
> + intel_gt_pm_get(gt);
> + if (GRAPHICS_VER(gt->i915) >= 6)
> + intel_uncore_forcewake_user_get(gt->uncore);
> +
> + return 0;
> +}
> +
> +int __forcewake_user_release(struct intel_gt *gt)
> +{
> + if (GRAPHICS_VER(gt->i915) >= 6)
> + intel_uncore_forcewake_user_put(gt->uncore);
> + intel_gt_pm_put(gt);
> + atomic_dec(>->user_wakeref);
> +
> + return 0;
> +}
> +
> +static int forcewake_user_open(struct inode *inode, struct file *file)
> +{
> + struct intel_gt *gt = inode->i_private;
> +
> + return __forcewake_user_open(gt);
> +}
> +
> +static int forcewake_user_release(struct inode *inode, struct file *file)
> +{
> + struct intel_gt *gt = inode->i_private;
> +
> + return __forcewake_user_release(gt);
> +}
> +
> +static const struct file_operations forcewake_user_fops = {
> + .owner = THIS_MODULE,
> + .open = forcewake_user_open,
> + .release = forcewake_user_release,
> +};
> +
> static int fw_domains_show(struct seq_file *m, void *data)
> {
> struct intel_gt *gt = m->private;
> @@ -627,6 +667,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
> { "drpc", &drpc_fops, NULL },
> { "frequency", &frequency_fops, NULL },
> { "forcewake", &fw_domains_fops, NULL },
> + { "forcewake_user", &forcewake_user_fops, NULL},
> { "llc", &llc_fops, llc_eval },
> { "rps_boost", &rps_boost_fops, rps_eval },
> };
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> index 2b824289582b..fe306412b996 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
> @@ -13,4 +13,8 @@ struct drm_printer;
> void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root);
> void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *m);
>
> +/* functions that need to be accessed by the upper level non-gt interfaces */
> +int __forcewake_user_open(struct intel_gt *gt);
> +int __forcewake_user_release(struct intel_gt *gt);
> +
> #endif /* INTEL_GT_PM_DEBUGFS_H */
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fdbd46ff59e0..fd7f5bd5f304 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -35,6 +35,7 @@
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_gt_clock_utils.h"
> +#include "gt/intel_gt_debugfs.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_gt_pm_debugfs.h"
> #include "gt/intel_gt_requests.h"
> @@ -554,36 +555,18 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
> return 0;
> }
>
> -static int
> -i915_wedged_get(void *data, u64 *val)
> +static int i915_wedged_get(void *data, u64 *val)
> {
> struct drm_i915_private *i915 = data;
> - int ret = intel_gt_terminally_wedged(&i915->gt);
>
> - switch (ret) {
> - case -EIO:
> - *val = 1;
> - return 0;
> - case 0:
> - *val = 0;
> - return 0;
> - default:
> - return ret;
> - }
> + return reset_show(&i915->gt, val);
> }
>
> -static int
> -i915_wedged_set(void *data, u64 val)
> +static int i915_wedged_set(void *data, u64 val)
> {
> struct drm_i915_private *i915 = data;
>
> - /* Flush any previous reset before applying for a new one */
> - wait_event(i915->gt.reset.queue,
> - !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
> -
> - intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
> - "Manually set wedged engine mask = %llx", val);
> - return 0;
> + return reset_store(&i915->gt, val);
> }
>
> DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
> @@ -728,27 +711,15 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
> static int i915_forcewake_open(struct inode *inode, struct file *file)
> {
> struct drm_i915_private *i915 = inode->i_private;
> - struct intel_gt *gt = &i915->gt;
> -
> - atomic_inc(>->user_wakeref);
> - intel_gt_pm_get(gt);
> - if (GRAPHICS_VER(i915) >= 6)
> - intel_uncore_forcewake_user_get(gt->uncore);
>
> - return 0;
> + return __forcewake_user_open(&i915->gt);
> }
>
> static int i915_forcewake_release(struct inode *inode, struct file *file)
> {
> struct drm_i915_private *i915 = inode->i_private;
> - struct intel_gt *gt = &i915->gt;
>
> - if (GRAPHICS_VER(i915) >= 6)
> - intel_uncore_forcewake_user_put(&i915->uncore);
> - intel_gt_pm_put(gt);
> - atomic_dec(>->user_wakeref);
> -
> - return 0;
> + return __forcewake_user_release(&i915->gt);
> }
>
> static const struct file_operations i915_forcewake_fops = {
> --
> 2.27.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
2021-10-08 11:27 ` Andi Shyti
` (2 preceding siblings ...)
(?)
@ 2021-10-08 16:55 ` Patchwork
-1 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-10-08 16:55 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3887 bytes --]
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10700 -> Patchwork_21292
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/index.html
Known issues
------------
Here are the changes found in Patchwork_21292 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: [PASS][4] -> [FAIL][5] ([i915#3239])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#541])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][8] ([i915#3921]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- {fi-tgl-dsi}: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/fi-tgl-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/fi-tgl-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3239]: https://gitlab.freedesktop.org/drm/intel/issues/3239
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 37)
------------------------------
Missing (3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10700 -> Patchwork_21292
CI-20190529: 20190529
CI_DRM_10700: 6ecdd5e29c83cd8fc191f8cce5c283eefb53c97e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6240: b232a092b9e1b10a8be13601acaa440903b226bc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21292: 997777b302f7d8af14c5640e6d9c73cabddd273b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
997777b302f7 drm/i915/gt: move remaining debugfs interfaces into gt
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/index.html
[-- Attachment #2: Type: text/html, Size: 4644 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt
2021-10-08 16:42 ` [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Ville Syrjälä
@ 2021-10-08 20:46 ` Andi Shyti
0 siblings, 0 replies; 7+ messages in thread
From: Andi Shyti @ 2021-10-08 20:46 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Andi Shyti, Intel GFX, DRI Devel, Tvrtko Ursulin, Chris Wilson,
Lucas De Marchi, Andi Shyti
Hi Ville,
> > + if (IS_CHERRYVIEW(i915)) {
> > + seq_printf(m, "Master Interrupt Control:\t%08x\n",
> > + intel_uncore_read(uncore, GEN8_MASTER_IRQ));
> > +
> > + for (i = 0; i < 4; i++) {
> > + seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IMR(i)));
> > + seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IIR(i)));
> > + seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
> > + i, intel_uncore_read(uncore,
> > + GEN8_GT_IER(i)));
> > + }
> > +
>
> Why does chv get its own block? Looks identical to the bdw block.
[...]
> > + } else if (!HAS_PCH_SPLIT(i915)) {
>
> HAS_PCH_SPLIT in gt code looks a bit out of place.
>
> > + seq_printf(m, "Interrupt enable: %08x\n",
> > + intel_uncore_read(uncore, GEN2_IER));
> > + seq_printf(m, "Interrupt identity: %08x\n",
> > + intel_uncore_read(uncore, GEN2_IIR));
> > + seq_printf(m, "Interrupt mask: %08x\n",
> > + intel_uncore_read(uncore, GEN2_IMR));
>
> Technically on gen2 these are 16 bits, on gen3+ 32 bits. I don't
> quite remember now what happens when you read them as 32bit on gen2.
> Might be the msbs just come out all zeroes.
>
> > + } else {
> > + seq_printf(m, "Graphics Interrupt enable: %08x\n",
> > + intel_uncore_read(uncore, GTIER));
> > + seq_printf(m, "Graphics Interrupt identity: %08x\n",
> > + intel_uncore_read(uncore, GTIIR));
> > + seq_printf(m, "Graphics Interrupt mask: %08x\n",
> > + intel_uncore_read(uncore, GTIMR));
>
> Probably this should be before the previous block to keep things in
> order. Also missing GEN6_PM stuff for snb+, and the master interrupt
> stuff for ilk+.
[...]
thanks for your input. Actually I'm not even sure this part of
the patch is required anymore. It was originally a copy paste of
the parts of the 'i915_interrupt_info' functions in the
'i915_gem_interrupt' debugfs file.
This file was removed here by Chris:
cf977e18610e6 ("drm/i915/gem: Spring clean debugfs")
I have reproposed it in this patch seeking for comments because I
wanted to understand after all this time it might be needed or
not. If not I was going to remove it in my last version.
I haven't received any comments and therefore I am going to
remove it in v4.
Thank you,
Andi
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
2021-10-08 11:27 ` Andi Shyti
` (3 preceding siblings ...)
(?)
@ 2021-10-08 22:09 ` Patchwork
-1 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2021-10-08 22:09 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30285 bytes --]
== Series Details ==
Series: drm/i915/gt: move remaining debugfs interfaces into gt (rev10)
URL : https://patchwork.freedesktop.org/series/75333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10700_full -> Patchwork_21292_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21292_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21292_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21292_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb2/igt@i915_pm_dc@dc9-dpms.html
Known issues
------------
Here are the changes found in Patchwork_21292_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb2/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2410])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb8/igt@gem_eio@in-flight-contexts-immediate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb8/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [TIMEOUT][8] ([i915#2369] / [i915#3063] / [i915#3648])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb2/igt@gem_eio@unwedge-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][9] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-apl: [PASS][12] -> [SKIP][13] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl8/igt@gem_exec_fair@basic-none-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842] / [i915#3468])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@gem_huc_copy@huc-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb5/igt@gem_pwrite@basic-exhaustion.html
- shard-glk: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4270])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +36 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([i915#180])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-apl6/igt@gem_softpin@noreloc-s3.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@gem_softpin@noreloc-s3.html
* igt@gem_sync@basic-many-each:
- shard-kbl: [PASS][24] -> [INCOMPLETE][25] ([i915#4274])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl2/igt@gem_sync@basic-many-each.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl1/igt@gem_sync@basic-many-each.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3323])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#2856])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][28] -> [INCOMPLETE][29] ([i915#198])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl6/igt@i915_pm_backlight@fade_with_suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl8/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#1937])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl1/igt@i915_suspend@forcewake.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl6/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: NOTRUN -> [DMESG-WARN][33] ([i915#118])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][34] ([fdo#110725] / [fdo#111614])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271]) +248 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +16 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271]) +364 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3886]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +23 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl7/igt@kms_color@pipe-a-ctm-0-5.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl5/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +16 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-c-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@kms_color_chamelium@pipe-c-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled:
- shard-snb: [PASS][51] -> [SKIP][52] ([fdo#109271])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-snb6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-snb6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
- shard-glk: [PASS][53] -> [FAIL][54] ([i915#79])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [PASS][55] -> [INCOMPLETE][56] ([i915#146] / [i915#198])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][57] ([i915#180]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][58] -> [FAIL][59] ([i915#2122]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [PASS][60] -> [SKIP][61] ([i915#3701])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-skl: NOTRUN -> [INCOMPLETE][62] ([i915#3699])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109280])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#1188]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [PASS][68] -> [INCOMPLETE][69] ([i915#198] / [i915#2828])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271]) +86 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][72] -> [FAIL][73] ([fdo#108145] / [i915#265])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][75] ([i915#265])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +4 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr@cursor_plane_onoff:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271]) +46 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl1/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +4 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-skl: NOTRUN -> [WARN][83] ([i915#2100])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_vblank@pipe-c-accuracy-idle:
- shard-skl: [PASS][84] -> [FAIL][85] ([i915#43])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl2/igt@kms_vblank@pipe-c-accuracy-idle.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl3/igt@kms_vblank@pipe-c-accuracy-idle.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-apl7/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@recycle:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@recycle-many:
- shard-glk: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk6/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@split-50:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-1us:
- shard-iclb: [TIMEOUT][90] ([i915#3070]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb8/igt@gem_eio@in-flight-contexts-1us.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb6/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][92] ([i915#2842]) -> [PASS][93] +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
- shard-glk: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk7/igt@gem_exec_fair@basic-flow@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl3/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [SKIP][98] ([fdo#109271]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][100] ([i915#2842]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb6/igt@gem_exec_fair@basic-pace@vecs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][102] ([i915#2849]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][104] ([i915#1436] / [i915#716]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl8/igt@gen9_exec_parse@allowed-single.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][106] ([i915#454]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][108] ([i915#2521]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl8/igt@kms_async_flips@alternate-sync-async-flip.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl8/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-glk: [DMESG-WARN][110] ([i915#118]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk8/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][114] ([i915#79]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [FAIL][116] ([i915#2122]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb1/igt@kms_psr@psr2_primary_mmap_gtt.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][122] ([i915#1542]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-glk5/igt@perf@polling-parameterized.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-glk7/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][124] ([i915#1804] / [i915#2684]) -> [WARN][125] ([i915#2684])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][126] ([i915#2684]) -> [WARN][127] ([i915#1804] / [i915#2684])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][128] ([i915#2920]) -> [SKIP][129] ([i915#658]) +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][130] ([i915#658]) -> [SKIP][131] ([i915#2920]) +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#3363])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10700/shard-kbl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl6/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl6/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl7/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl2/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][148], [FAIL][149], [FAIL][150]) ([fdo#10
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21292/index.html
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-- links below jump to the message on this page --
2021-10-08 11:27 [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Andi Shyti
2021-10-08 11:27 ` Andi Shyti
2021-10-08 16:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: move remaining debugfs interfaces into gt (rev10) Patchwork
2021-10-08 16:42 ` [Intel-gfx] [PATCH v3] drm/i915/gt: move remaining debugfs interfaces into gt Ville Syrjälä
2021-10-08 20:46 ` Andi Shyti
2021-10-08 16:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: move remaining debugfs interfaces into gt (rev10) Patchwork
2021-10-08 22:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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