[PATCH 0/2] Hexagon (target/hexagon) cleanup and bug fix

[PATCH 0/2] Hexagon (target/hexagon) cleanup and bug fix

[Taylor Simpson]

Followup to replace more tcg_const_* with tcg_constant_tl*
Fix bug to delay writes to USR until packet commit

Taylor Simpson (2):
  Hexagon (target/hexagon) more tcg_constant_*
  Hexagon (target/hexagon) put writes to USR into temp until commit

 target/hexagon/gen_tcg.h          |   9 ++--
 target/hexagon/macros.h           |   9 ++--
 target/hexagon/attribs_def.h.inc  |   1 +
 target/hexagon/translate.c        |  12 +++--
 tests/tcg/hexagon/overflow.c      | 107 ++++++++++++++++++++++++++++++++++++++
 target/hexagon/gen_tcg_funcs.py   |  11 +---
 target/hexagon/hex_common.py      |   2 +
 tests/tcg/hexagon/Makefile.target |   1 +
 8 files changed, 129 insertions(+), 23 deletions(-)
 create mode 100644 tests/tcg/hexagon/overflow.c

-- 
2.7.4

[PATCH 1/2] Hexagon (target/hexagon) more tcg_constant_*

[Taylor Simpson]

Change additional tcg_const_tl to tcg_constant_tl

Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.
However, it is not constant throughout, so we initialize it with
tcg_temp_new and replace the first use with the constant value.

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Inspired-by: Philippe Mathieu-Daud<C3><A9> <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/gen_tcg.h        |  9 +++------
 target/hexagon/macros.h         |  7 +++----
 target/hexagon/translate.c      |  3 +--
 target/hexagon/gen_tcg_funcs.py | 11 ++---------
 4 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 0361564..c6f0879 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -66,11 +66,10 @@
     } while (0)
 #define GET_EA_pci \
     do { \
-        TCGv tcgv_siV = tcg_const_tl(siV); \
+        TCGv tcgv_siV = tcg_constant_tl(siV); \
         tcg_gen_mov_tl(EA, RxV); \
         gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \
                             hex_gpr[HEX_REG_CS0 + MuN]); \
-        tcg_temp_free(tcgv_siV); \
     } while (0)
 #define GET_EA_pcr(SHIFT) \
     do { \
@@ -557,7 +556,7 @@
 #define fGEN_TCG_A4_addp_c(SHORTCODE) \
     do { \
         TCGv_i64 carry = tcg_temp_new_i64(); \
-        TCGv_i64 zero = tcg_const_i64(0); \
+        TCGv_i64 zero = tcg_constant_i64(0); \
         tcg_gen_extu_i32_i64(carry, PxV); \
         tcg_gen_andi_i64(carry, carry, 1); \
         tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \
@@ -565,14 +564,13 @@
         tcg_gen_extrl_i64_i32(PxV, carry); \
         gen_8bitsof(PxV, PxV); \
         tcg_temp_free_i64(carry); \
-        tcg_temp_free_i64(zero); \
     } while (0)
 
 /* r5:4 = sub(r1:0, r3:2, p1):carry */
 #define fGEN_TCG_A4_subp_c(SHORTCODE) \
     do { \
         TCGv_i64 carry = tcg_temp_new_i64(); \
-        TCGv_i64 zero = tcg_const_i64(0); \
+        TCGv_i64 zero = tcg_constant_i64(0); \
         TCGv_i64 not_RttV = tcg_temp_new_i64(); \
         tcg_gen_extu_i32_i64(carry, PxV); \
         tcg_gen_andi_i64(carry, carry, 1); \
@@ -582,7 +580,6 @@
         tcg_gen_extrl_i64_i32(PxV, carry); \
         gen_8bitsof(PxV, PxV); \
         tcg_temp_free_i64(carry); \
-        tcg_temp_free_i64(zero); \
         tcg_temp_free_i64(not_RttV); \
     } while (0)
 
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 44e9b85..5c19cde 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -187,10 +187,10 @@
 #ifdef QEMU_GENERATE
 static inline void gen_pred_cancel(TCGv pred, int slot_num)
  {
-    TCGv slot_mask = tcg_const_tl(1 << slot_num);
+    TCGv slot_mask = tcg_temp_new();
     TCGv tmp = tcg_temp_new();
     TCGv zero = tcg_constant_tl(0);
-    tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask);
+    tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num);
     tcg_gen_andi_tl(tmp, pred, 1);
     tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
                        slot_mask, hex_slot_cancelled);
@@ -498,10 +498,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 #define fPM_CIRI(REG, IMM, MVAL) \
     do { \
-        TCGv tcgv_siV = tcg_const_tl(siV); \
+        TCGv tcgv_siV = tcg_constant_tl(siV); \
         gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
                             hex_gpr[HEX_REG_CS0 + MuN]); \
-        tcg_temp_free(tcgv_siV); \
     } while (0)
 #else
 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 4f05ce3..e065092 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -491,9 +491,8 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
          * process_store_log will execute the slot 1 store first,
          * so we only have to probe the store in slot 0
          */
-        TCGv mem_idx = tcg_const_tl(ctx->mem_idx);
+        TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
         gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
-        tcg_temp_free(mem_idx);
     }
 
     process_store_log(ctx, pkt);
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index ca8a801..e3d59dd 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -279,15 +279,12 @@ def gen_helper_call_opn(f, tag, regtype, regid, toss, numregs, i):
         print("Bad register parse: ",regtype,regid,toss,numregs)
 
 def gen_helper_decl_imm(f,immlett):
-    f.write("    TCGv tcgv_%s = tcg_const_tl(%s);\n" % \
+    f.write("    TCGv tcgv_%s = tcg_constant_tl(%s);\n" % \
         (hex_common.imm_name(immlett), hex_common.imm_name(immlett)))
 
 def gen_helper_call_imm(f,immlett):
     f.write(", tcgv_%s" % hex_common.imm_name(immlett))
 
-def gen_helper_free_imm(f,immlett):
-    f.write("    tcg_temp_free(tcgv_%s);\n" % hex_common.imm_name(immlett))
-
 def genptr_dst_write_pair(f, tag, regtype, regid):
     if ('A_CONDEXEC' in hex_common.attribdict[tag]):
         f.write("    gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn->slot);\n" % \
@@ -401,7 +398,7 @@ def gen_tcg_func(f, tag, regs, imms):
         for immlett,bits,immshift in imms:
             gen_helper_decl_imm(f,immlett)
         if hex_common.need_part1(tag):
-            f.write("    TCGv part1 = tcg_const_tl(insn->part1);\n")
+            f.write("    TCGv part1 = tcg_constant_tl(insn->part1);\n")
         if hex_common.need_slot(tag):
             f.write("    TCGv slot = tcg_constant_tl(insn->slot);\n")
         f.write("    gen_helper_%s(" % (tag))
@@ -424,10 +421,6 @@ def gen_tcg_func(f, tag, regs, imms):
         if hex_common.need_slot(tag): f.write(", slot")
         if hex_common.need_part1(tag): f.write(", part1" )
         f.write(");\n")
-        if hex_common.need_part1(tag):
-            f.write("    tcg_temp_free(part1);\n")
-        for immlett,bits,immshift in imms:
-            gen_helper_free_imm(f,immlett)
 
     ## Write all the outputs
     for regtype,regid,toss,numregs in regs:
-- 
2.7.4

[PATCH] Hexagon (target/hexagon) put writes to USR into temp until commit

[Taylor Simpson]

Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
of hex_gpr[HEX_REG_USR].

Then, we need code to mark the instructions that can set implicitly
set USR
- Macros added to hex_common.py
- A_FPOP added in translate.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/macros.h          | 2 +-
 target/hexagon/attribs_def.h.inc | 1 +
 target/hexagon/translate.c       | 9 ++++++++-
 target/hexagon/hex_common.py     | 2 ++
 4 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 094b8da..c0e2d7c 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -62,7 +62,7 @@
                    reg_field_info[FIELD].offset)
 
 #define SET_USR_FIELD(FIELD, VAL) \
-    fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
+    fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
                  reg_field_info[FIELD].offset, (VAL))
 #endif
 
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 3815509..e44a7ea 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
 DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
 DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
 DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
+DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
 DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
 
 DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 6fb4e68..2c9081a 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -210,7 +210,12 @@ static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
                                     int attrib, int rnum)
 {
     if (GET_ATTRIB(insn->opcode, attrib)) {
-        bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
+        /*
+         * USR is used to set overflow and FP exceptions,
+         * so treat it as conditional
+         */
+        bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) ||
+                             rnum == HEX_REG_USR;
         if (is_predicated && !is_preloaded(ctx, rnum)) {
             tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
         }
@@ -236,6 +241,8 @@ static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
+    mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
+    mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR);
 }
 
 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index b3b5340..a84b003 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -73,6 +73,8 @@ def calculate_attribs():
     add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
     add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
     add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
+    add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
+    add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
 
     # Recurse down macros, find attributes from sub-macros
     macroValues = list(macros.values())
-- 
2.7.4

[PATCH 2/2] Hexagon (target/hexagon) put writes to USR into temp until commit

[Taylor Simpson]

Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
of hex_gpr[HEX_REG_USR].

Then, we need code to mark the instructions that can set implicitly
set USR
- Macros added to hex_common.py
- A_FPOP added in translate.c

Test case added in tests/tcg/hexagon/overflow.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/macros.h           |   2 +-
 target/hexagon/attribs_def.h.inc  |   1 +
 target/hexagon/translate.c        |   9 +++-
 tests/tcg/hexagon/overflow.c      | 107 ++++++++++++++++++++++++++++++++++++++
 target/hexagon/hex_common.py      |   2 +
 tests/tcg/hexagon/Makefile.target |   1 +
 6 files changed, 120 insertions(+), 2 deletions(-)
 create mode 100644 tests/tcg/hexagon/overflow.c

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 5c19cde..13e957b 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -62,7 +62,7 @@
                    reg_field_info[FIELD].offset)
 
 #define SET_USR_FIELD(FIELD, VAL) \
-    fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
+    fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
                  reg_field_info[FIELD].offset, (VAL))
 #endif
 
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index 3815509..e44a7ea 100644
--- a/target/hexagon/attribs_def.h.inc
+++ b/target/hexagon/attribs_def.h.inc
@@ -64,6 +64,7 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "", "UREG.P1")
 DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2")
 DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3")
 DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "")
+DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "")
 DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "")
 
 DEF_ATTRIB(CRSLOT23, "Can execute in slot 2 or slot 3 (CR)", "", "")
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index e065092..f1760ce 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -208,7 +208,12 @@ static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
                                     int attrib, int rnum)
 {
     if (GET_ATTRIB(insn->opcode, attrib)) {
-        bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
+        /*
+         * USR is used to set overflow and FP exceptions,
+         * so treat it as conditional
+         */
+        bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) ||
+                             rnum == HEX_REG_USR;
         if (is_predicated && !is_preloaded(ctx, rnum)) {
             tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
         }
@@ -234,6 +239,8 @@ static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
+    mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR);
+    mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR);
 }
 
 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
diff --git a/tests/tcg/hexagon/overflow.c b/tests/tcg/hexagon/overflow.c
new file mode 100644
index 0000000..196fcf7
--- /dev/null
+++ b/tests/tcg/hexagon/overflow.c
@@ -0,0 +1,107 @@
+/*
+ *  Copyright(c) 2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <setjmp.h>
+#include <signal.h>
+
+
+int err;
+
+static void __check(const char *filename, int line, int x, int expect)
+{
+    if (x != expect) {
+        printf("ERROR %s:%d - %d != %d\n",
+               filename, line, x, expect);
+        err++;
+    }
+}
+
+#define check(x, expect) __check(__FILE__, __LINE__, (x), (expect))
+
+static int satub(int src, int *p, int *ovf_result)
+{
+    int result;
+    int usr;
+
+    /*
+     * This instruction can set bit 0 (OVF/overflow) in usr
+     * Clear the bit first, then return that bit to the caller
+     *
+     * We also store the src into *p in the same packet, so we
+     * can ensure the overflow doesn't get set when an exception
+     * is generated.
+     */
+    asm volatile("r2 = usr\n\t"
+                 "r2 = clrbit(r2, #0)\n\t"        /* clear overflow bit */
+                 "usr = r2\n\t"
+                 "{\n\t"
+                 "    %0 = satub(%2)\n\t"
+                 "    memw(%3) = %2\n\t"
+                 "}\n\t"
+                 "%1 = usr\n\t"
+                 : "=r"(result), "=r"(usr)
+                 : "r"(src), "r"(p)
+                 : "r2", "usr", "memory");
+  *ovf_result = (usr & 1);
+  return result;
+}
+
+int read_usr_overflow(void)
+{
+    int result;
+    asm volatile("%0 = usr\n\t" : "=r"(result));
+    return result & 1;
+}
+
+
+jmp_buf jmp_env;
+int usr_overflow;
+
+static void sig_segv(int sig, siginfo_t *info, void *puc)
+{
+    usr_overflow = read_usr_overflow();
+    longjmp(jmp_env, 1);
+}
+
+int main()
+{
+    struct sigaction act;
+    int ovf;
+
+    /* SIGSEGV test */
+    act.sa_sigaction = sig_segv;
+    sigemptyset(&act.sa_mask);
+    act.sa_flags = SA_SIGINFO;
+    sigaction(SIGSEGV, &act, NULL);
+    if (setjmp(jmp_env) == 0) {
+        satub(300, 0, &ovf);
+    }
+
+    act.sa_handler = SIG_DFL;
+    sigemptyset(&act.sa_mask);
+    act.sa_flags = 0;
+
+    check(usr_overflow, 0);
+
+    puts(err ? "FAIL" : "PASS");
+    return err ? EXIT_FAILURE : EXIT_SUCCESS;
+}
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index b3b5340..a84b003 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -73,6 +73,8 @@ def calculate_attribs():
     add_qemu_macro_attrib('fWRITE_P1', 'A_WRITES_PRED_REG')
     add_qemu_macro_attrib('fWRITE_P2', 'A_WRITES_PRED_REG')
     add_qemu_macro_attrib('fWRITE_P3', 'A_WRITES_PRED_REG')
+    add_qemu_macro_attrib('fSET_OVERFLOW', 'A_IMPLICIT_WRITES_USR')
+    add_qemu_macro_attrib('fSET_LPCFG', 'A_IMPLICIT_WRITES_USR')
 
     # Recurse down macros, find attributes from sub-macros
     macroValues = list(macros.values())
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index c1e1650..8b07a28 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -40,5 +40,6 @@ HEX_TESTS += load_unpack
 HEX_TESTS += load_align
 HEX_TESTS += atomics
 HEX_TESTS += fpstuff
+HEX_TESTS += overflow
 
 TESTS += $(HEX_TESTS)
-- 
2.7.4

Re: [PATCH 1/2] Hexagon (target/hexagon) more tcg_constant_*

[Richard Henderson]

On 10/12/21 2:31 AM, Taylor Simpson wrote:
> Change additional tcg_const_tl to tcg_constant_tl
> 
> Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.
> However, it is not constant throughout, so we initialize it with
> tcg_temp_new and replace the first use with the constant value.
> 
> Inspired-by: Richard Henderson<richard.henderson@linaro.org>
> Inspired-by: Philippe Mathieu-Daud<C3><A9><f4bug@amsat.org>
> Signed-off-by: Taylor Simpson<tsimpson@quicinc.com>
> ---
>   target/hexagon/gen_tcg.h        |  9 +++------
>   target/hexagon/macros.h         |  7 +++----
>   target/hexagon/translate.c      |  3 +--
>   target/hexagon/gen_tcg_funcs.py | 11 ++---------
>   4 files changed, 9 insertions(+), 21 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 2/2] Hexagon (target/hexagon) put writes to USR into temp until commit

[Richard Henderson]

On 10/12/21 2:31 AM, Taylor Simpson wrote:
> Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
> of hex_gpr[HEX_REG_USR].
> 
> Then, we need code to mark the instructions that can set implicitly
> set USR
> - Macros added to hex_common.py
> - A_FPOP added in translate.c
> 
> Test case added in tests/tcg/hexagon/overflow.c
> 
> Signed-off-by: Taylor Simpson<tsimpson@quicinc.com>
> ---

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 1/2] Hexagon (target/hexagon) more tcg_constant_*

[Philippe Mathieu-Daudé]

On 10/12/21 11:31, Taylor Simpson wrote:
> Change additional tcg_const_tl to tcg_constant_tl
> 
> Note that gen_pred_cancal had slot_mask initialized with tcg_const_tl.
> However, it is not constant throughout, so we initialize it with
> tcg_temp_new and replace the first use with the constant value.
> 
> Inspired-by: Richard Henderson <richard.henderson@linaro.org>
> Inspired-by: Philippe Mathieu-Daud<C3><A9> <f4bug@amsat.org>

UTF-8 copy/paste mojibake, otherwise:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>  target/hexagon/gen_tcg.h        |  9 +++------
>  target/hexagon/macros.h         |  7 +++----
>  target/hexagon/translate.c      |  3 +--
>  target/hexagon/gen_tcg_funcs.py | 11 ++---------
>  4 files changed, 9 insertions(+), 21 deletions(-)

Re: [PATCH] Hexagon (target/hexagon) put writes to USR into temp until commit

[Philippe Mathieu-Daudé]

On 10/12/21 11:31, Taylor Simpson wrote:
> Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead
> of hex_gpr[HEX_REG_USR].
> 
> Then, we need code to mark the instructions that can set implicitly
> set USR
> - Macros added to hex_common.py
> - A_FPOP added in translate.c
> 
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>  target/hexagon/macros.h          | 2 +-
>  target/hexagon/attribs_def.h.inc | 1 +
>  target/hexagon/translate.c       | 9 ++++++++-
>  target/hexagon/hex_common.py     | 2 ++
>  4 files changed, 12 insertions(+), 2 deletions(-)

This is stale v1. git-publish helps to avoid this workflow
mistakes ;) https://github.com/stefanha/git-publish