* [PATCH 1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
@ 2021-10-19 16:13 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2021-10-19 16:13 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: jani.nikula, ville.syrjala
Add a helper for getting the DP PHY name. In the interest of caller
simplicity and to avoid allocations and passing in of buffers, duplicate
the const strings to return. It's a minor penalty to pay for simplicity
in all the call sites.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 21 +++++++++++++++++++++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ada0a1ff262d..2c36fad88781 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -314,6 +314,27 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
+{
+ static const char * const phy_names[] = {
+ [DP_PHY_DPRX] = "DPRX",
+ [DP_PHY_LTTPR1] = "LTTPR 1",
+ [DP_PHY_LTTPR2] = "LTTPR 2",
+ [DP_PHY_LTTPR3] = "LTTPR 3",
+ [DP_PHY_LTTPR4] = "LTTPR 4",
+ [DP_PHY_LTTPR5] = "LTTPR 5",
+ [DP_PHY_LTTPR6] = "LTTPR 6",
+ [DP_PHY_LTTPR7] = "LTTPR 7",
+ [DP_PHY_LTTPR8] = "LTTPR 8",
+ };
+
+ if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names))
+ return "<INVALID DP PHY>";
+
+ return phy_names[dp_phy];
+}
+EXPORT_SYMBOL(drm_dp_phy_name);
+
void drm_dp_lttpr_link_train_clock_recovery_delay(void)
{
usleep_range(100, 200);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index afdf7f4183f9..39a249d99a51 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -2132,6 +2132,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
const struct drm_dp_desc *desc);
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
+
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
--
2.30.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
@ 2021-10-19 16:13 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2021-10-19 16:13 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: jani.nikula, ville.syrjala
Add a helper for getting the DP PHY name. In the interest of caller
simplicity and to avoid allocations and passing in of buffers, duplicate
the const strings to return. It's a minor penalty to pay for simplicity
in all the call sites.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 21 +++++++++++++++++++++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ada0a1ff262d..2c36fad88781 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -314,6 +314,27 @@ void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
+{
+ static const char * const phy_names[] = {
+ [DP_PHY_DPRX] = "DPRX",
+ [DP_PHY_LTTPR1] = "LTTPR 1",
+ [DP_PHY_LTTPR2] = "LTTPR 2",
+ [DP_PHY_LTTPR3] = "LTTPR 3",
+ [DP_PHY_LTTPR4] = "LTTPR 4",
+ [DP_PHY_LTTPR5] = "LTTPR 5",
+ [DP_PHY_LTTPR6] = "LTTPR 6",
+ [DP_PHY_LTTPR7] = "LTTPR 7",
+ [DP_PHY_LTTPR8] = "LTTPR 8",
+ };
+
+ if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names))
+ return "<INVALID DP PHY>";
+
+ return phy_names[dp_phy];
+}
+EXPORT_SYMBOL(drm_dp_phy_name);
+
void drm_dp_lttpr_link_train_clock_recovery_delay(void)
{
usleep_range(100, 200);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index afdf7f4183f9..39a249d99a51 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -2132,6 +2132,8 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
const struct drm_dp_desc *desc);
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
+const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
+
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
--
2.30.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915/dp: use drm_dp_phy_name() for logging
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
@ 2021-10-19 16:13 ` Jani Nikula
-1 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2021-10-19 16:13 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: jani.nikula, ville.syrjala
Drop the local intel_dp_phy_name() function, and replace with
drm_dp_phy_name(). This lets us drop a number of local buffers.
v2: Rebase
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 83 ++++++++-----------
1 file changed, 36 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a72f2dc93718..81f93733fcc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -37,17 +37,6 @@ static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
}
-static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
- char *buf, size_t buf_size)
-{
- if (dp_phy == DP_PHY_DPRX)
- snprintf(buf, buf_size, "DPRX");
- else
- snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
-
- return buf;
-}
-
static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
@@ -59,20 +48,19 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
- char phy_name[10];
-
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return;
}
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
- encoder->base.base.id, encoder->base.name, phy_name,
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy),
(int)sizeof(intel_dp->lttpr_phy_caps[0]),
phy_caps);
}
@@ -406,14 +394,13 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
int lane;
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, "
"TX FFE request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_TX_FFE_ARGS(link_status));
} else {
@@ -421,7 +408,7 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
"vswing request: " TRAIN_REQ_FMT ", "
"pre-emphasis request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_VSWING_ARGS(link_status),
TRAIN_REQ_PREEMPH_ARGS(link_status));
@@ -486,13 +473,12 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
- char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
@@ -529,13 +515,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, "
"TX FFE presets: " TRAIN_SET_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
} else {
@@ -543,7 +528,7 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
"vswing levels: " TRAIN_SET_FMT ", "
"pre-emphasis levels: " TRAIN_SET_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
@@ -715,12 +700,11 @@ intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
link_status[0], link_status[1], link_status[2],
link_status[3], link_status[4], link_status[5]);
}
@@ -740,21 +724,19 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
int voltage_tries, cr_tries, max_cr_tries;
u8 link_status[DP_LINK_STATUS_SIZE];
bool max_vswing_reached = false;
- char phy_name[10];
int delay_us;
delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
intel_dp->dpcd, dp_phy,
intel_dp_is_uhbr(crtc_state));
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
-
/* clock recovery */
if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
DP_TRAINING_PATTERN_1 |
DP_LINK_SCRAMBLING_DISABLE)) {
drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -778,14 +760,16 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
link_status) < 0) {
drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Clock recovery OK\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return true;
}
@@ -793,7 +777,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -801,7 +786,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -811,7 +797,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to update link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -829,7 +816,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
- encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy), max_cr_tries);
return false;
}
@@ -907,15 +895,12 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
u32 training_pattern;
u8 link_status[DP_LINK_STATUS_SIZE];
bool channel_eq = false;
- char phy_name[10];
int delay_us;
delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
intel_dp->dpcd, dp_phy,
intel_dp_is_uhbr(crtc_state));
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
-
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
if (training_pattern != DP_TRAINING_PATTERN_4)
@@ -927,7 +912,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to start channel equalization\n",
encoder->base.base.id, encoder->base.name,
- phy_name);
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -938,7 +923,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
link_status) < 0) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to get link status\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -949,7 +935,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Clock recovery check failed, cannot "
"continue channel equalization\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -958,7 +945,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
channel_eq = true;
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -968,7 +956,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to update link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
}
@@ -978,7 +967,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
}
return channel_eq;
@@ -1026,7 +1016,6 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
{
struct intel_connector *connector = intel_dp->attached_connector;
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- char phy_name[10];
bool ret = false;
if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
@@ -1042,7 +1031,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n",
connector->base.base.id, connector->base.name,
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
ret ? "passed" : "failed",
crtc_state->port_clock, crtc_state->lane_count);
--
2.30.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/dp: use drm_dp_phy_name() for logging
@ 2021-10-19 16:13 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2021-10-19 16:13 UTC (permalink / raw)
To: dri-devel, intel-gfx; +Cc: jani.nikula, ville.syrjala
Drop the local intel_dp_phy_name() function, and replace with
drm_dp_phy_name(). This lets us drop a number of local buffers.
v2: Rebase
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_dp_link_training.c | 83 ++++++++-----------
1 file changed, 36 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a72f2dc93718..81f93733fcc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -37,17 +37,6 @@ static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
}
-static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
- char *buf, size_t buf_size)
-{
- if (dp_phy == DP_PHY_DPRX)
- snprintf(buf, buf_size, "DPRX");
- else
- snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
-
- return buf;
-}
-
static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
enum drm_dp_phy dp_phy)
{
@@ -59,20 +48,19 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
- char phy_name[10];
-
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return;
}
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n",
- encoder->base.base.id, encoder->base.name, phy_name,
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy),
(int)sizeof(intel_dp->lttpr_phy_caps[0]),
phy_caps);
}
@@ -406,14 +394,13 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
int lane;
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, "
"TX FFE request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_TX_FFE_ARGS(link_status));
} else {
@@ -421,7 +408,7 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
"vswing request: " TRAIN_REQ_FMT ", "
"pre-emphasis request: " TRAIN_REQ_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_REQ_VSWING_ARGS(link_status),
TRAIN_REQ_PREEMPH_ARGS(link_status));
@@ -486,13 +473,12 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
- char phy_name[10];
if (train_pat != DP_TRAINING_PATTERN_DISABLE)
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
dp_training_pattern_name(train_pat));
intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
@@ -529,13 +515,12 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
if (intel_dp_is_uhbr(crtc_state)) {
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, "
"TX FFE presets: " TRAIN_SET_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
} else {
@@ -543,7 +528,7 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
"vswing levels: " TRAIN_SET_FMT ", "
"pre-emphasis levels: " TRAIN_SET_FMT "\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
crtc_state->lane_count,
TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
@@ -715,12 +700,11 @@ intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- char phy_name[10];
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
link_status[0], link_status[1], link_status[2],
link_status[3], link_status[4], link_status[5]);
}
@@ -740,21 +724,19 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
int voltage_tries, cr_tries, max_cr_tries;
u8 link_status[DP_LINK_STATUS_SIZE];
bool max_vswing_reached = false;
- char phy_name[10];
int delay_us;
delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
intel_dp->dpcd, dp_phy,
intel_dp_is_uhbr(crtc_state));
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
-
/* clock recovery */
if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
DP_TRAINING_PATTERN_1 |
DP_LINK_SCRAMBLING_DISABLE)) {
drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -778,14 +760,16 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
link_status) < 0) {
drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Clock recovery OK\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return true;
}
@@ -793,7 +777,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Same voltage tried 5 times\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -801,7 +786,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Max Voltage Swing reached\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -811,7 +797,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to update link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -829,7 +816,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n",
- encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy), max_cr_tries);
return false;
}
@@ -907,15 +895,12 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
u32 training_pattern;
u8 link_status[DP_LINK_STATUS_SIZE];
bool channel_eq = false;
- char phy_name[10];
int delay_us;
delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
intel_dp->dpcd, dp_phy,
intel_dp_is_uhbr(crtc_state));
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
-
training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
if (training_pattern != DP_TRAINING_PATTERN_4)
@@ -927,7 +912,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to start channel equalization\n",
encoder->base.base.id, encoder->base.name,
- phy_name);
+ drm_dp_phy_name(dp_phy));
return false;
}
@@ -938,7 +923,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
link_status) < 0) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to get link status\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -949,7 +935,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Clock recovery check failed, cannot "
"continue channel equalization\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -958,7 +945,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
channel_eq = true;
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
@@ -968,7 +956,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
drm_err(&i915->drm,
"[ENCODER:%d:%s][%s] Failed to update link training\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
break;
}
}
@@ -978,7 +967,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n",
- encoder->base.base.id, encoder->base.name, phy_name);
+ encoder->base.base.id, encoder->base.name,
+ drm_dp_phy_name(dp_phy));
}
return channel_eq;
@@ -1026,7 +1016,6 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
{
struct intel_connector *connector = intel_dp->attached_connector;
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
- char phy_name[10];
bool ret = false;
if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
@@ -1042,7 +1031,7 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n",
connector->base.base.id, connector->base.name,
encoder->base.base.id, encoder->base.name,
- intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)),
+ drm_dp_phy_name(dp_phy),
ret ? "passed" : "failed",
crtc_state->port_clock, crtc_state->lane_count);
--
2.30.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
(?)
(?)
@ 2021-10-19 19:12 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-10-19 19:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
URL : https://patchwork.freedesktop.org/series/96017/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:318:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1416:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1416:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1416:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1417:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1417:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1417:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1476:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1476:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1476:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:355:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:355:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:355:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4481:31: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4481:31: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4481:31: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:33: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:33: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:33: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:117:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:314:49: error: static assertion faile
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
` (2 preceding siblings ...)
(?)
@ 2021-10-19 19:41 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-10-19 19:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6250 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
URL : https://patchwork.freedesktop.org/series/96017/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10762 -> Patchwork_21383
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/index.html
Known issues
------------
Here are the changes found in Patchwork_21383 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-ilk-650: NOTRUN -> [SKIP][1] ([fdo#109271]) +35 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-ilk-650/igt@amdgpu/amd_basic@query-info.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: NOTRUN -> [FAIL][4] ([i915#1888])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#3301])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][15] ([i915#4269]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@runner@aborted:
- fi-icl-u2: [FAIL][17] ([i915#3363]) -> [FAIL][18] ([i915#3363] / [i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/fi-icl-u2/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/fi-icl-u2/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
Participating hosts (36 -> 36)
------------------------------
Additional (2): fi-tgl-1115g4 fi-ilk-650
Missing (2): fi-bsw-cyan bat-dg1-6
Build changes
-------------
* Linux: CI_DRM_10762 -> Patchwork_21383
CI-20190529: 20190529
CI_DRM_10762: 448b23374caeafa59d2a057fdc1a7c069b934960 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6255: 9b0881254557edeaf273b2196309fc4e22ea0312 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21383: 910a553f5101834de5c9e6fd769c5e91e31dedff @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
910a553f5101 drm/i915/dp: use drm_dp_phy_name() for logging
51c8d47e86c3 drm/dp: add drm_dp_phy_name() for getting DP PHY name
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/index.html
[-- Attachment #2: Type: text/html, Size: 7480 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
` (3 preceding siblings ...)
(?)
@ 2021-10-20 0:30 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-10-20 0:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30303 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
URL : https://patchwork.freedesktop.org/series/96017/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10762_full -> Patchwork_21383_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21383_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21383_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21383_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-tglb: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
Known issues
------------
Here are the changes found in Patchwork_21383_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglb: NOTRUN -> [SKIP][4] ([i915#280]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb2/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][7] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][12] -> [SKIP][13] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@gem_pread@exhaustion.html
- shard-kbl: NOTRUN -> [WARN][16] ([i915#2658])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-regular-context-1:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@gem_pxp@create-regular-context-1.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][19] ([i915#2724])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-start-out:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@gen9_exec_parse@bb-start-out.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][21] ([i915#4272])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl8/igt@kms_async_flips@crc.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][23] ([i915#3743]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3777])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_bw@linear-tiling-1-displays-3840x2160p:
- shard-tglb: NOTRUN -> [FAIL][25] ([i915#1385])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-apl: NOTRUN -> [DMESG-FAIL][26] ([i915#4298])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl2/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-3-displays-2560x1440p:
- shard-snb: NOTRUN -> [FAIL][27] ([i915#4299])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +9 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109278] / [i915#3886])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271]) +423 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#3689]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +4 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +25 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +20 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color@pipe-a-ctm-blue-to-red:
- shard-skl: [PASS][38] -> [DMESG-WARN][39] ([i915#1982]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl7/igt@kms_color@pipe-a-ctm-blue-to-red.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl6/igt@kms_color@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111828])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109279] / [i915#3359])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3359]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271]) +46 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][46] -> [DMESG-WARN][47] ([i915#180]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][50] -> [FAIL][51] ([i915#72])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][52] -> [DMESG-WARN][53] ([i915#180])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][54] -> [FAIL][55] ([i915#2122])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2672])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271]) +250 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-snb: [PASS][58] -> [SKIP][59] ([fdo#109271]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-snb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#111825]) +9 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109280])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271]) +88 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#533])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([fdo#108145] / [i915#265]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][67] ([i915#265]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][68] -> [FAIL][69] ([fdo#108145] / [i915#265])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][73] -> [SKIP][74] ([fdo#109441])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2437])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl8/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2437]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl2/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#2530])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][78] -> [FAIL][79] ([i915#1722])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl9/igt@perf@polling-small-buf.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl2/igt@perf@polling-small-buf.html
* igt@perf@short-reads:
- shard-skl: [PASS][80] -> [FAIL][81] ([i915#51])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl8/igt@perf@short-reads.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl4/igt@perf@short-reads.html
* igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
- shard-tglb: NOTRUN -> [SKIP][82] ([fdo#109291])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109291]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb7/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2994])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-10:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2994])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl7/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][87] ([i915#2994])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb6/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][88] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb7/igt@gem_eio@unwedge-stress.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb7/igt@gem_eio@unwedge-stress.html
- shard-iclb: [TIMEOUT][90] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@gem_eio@unwedge-stress.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][92] ([i915#2842]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][98] ([i915#2842]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_whisper@basic-queues-priority:
- shard-iclb: [INCOMPLETE][100] ([i915#1895]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html
* igt@gem_spin_batch@resubmit-new-all@vecs0:
- shard-skl: [DMESG-WARN][102] ([i915#1982]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@gem_spin_batch@resubmit-new-all@vecs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl3/igt@gem_spin_batch@resubmit-new-all@vecs0.html
* igt@gem_workarounds@suspend-resume:
- shard-skl: [INCOMPLETE][104] ([i915#198]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl2/igt@gem_workarounds@suspend-resume.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl8/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][106] ([i915#1436] / [i915#716]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@gen9_exec_parse@allowed-single.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl10/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@perf@region:
- shard-iclb: [INCOMPLETE][108] -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb4/igt@i915_selftest@perf@region.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb1/igt@i915_selftest@perf@region.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
- shard-snb: [SKIP][110] ([fdo#109271]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-snb7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-snb6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
- shard-tglb: [INCOMPLETE][114] ([i915#2411] / [i915#456]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][116] ([i915#2346] / [i915#533]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][118] ([i915#2122]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][122] ([i915#180]) -> [PASS][123] +4 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [FAIL][124] ([i915#2122]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][126] ([i915#1188]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-skl4/igt@kms_hdr@bpc-switch.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-skl4/igt@kms_hdr@bpc-switch.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][128] ([fdo#109441]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][130] ([i915#1542]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-glk8/igt@perf@polling-parameterized.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-glk6/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][132] ([i915#2920]) -> [SKIP][133] ([i915#658])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][134] ([i915#658]) -> [SKIP][135] ([i915#2920]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10762/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [FAIL][136] ([i915#4148]) -> [SKIP][137] ([fdo#109642] / [fdo#111068] / [i915#658])
[136]: https://intel-gfx-ci.01.org/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21383/index.html
[-- Attachment #2: Type: text/html, Size: 33589 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-05 12:22 ` Jani Nikula
@ 2021-10-05 12:38 ` Sarvela, Tomi P
0 siblings, 0 replies; 10+ messages in thread
From: Sarvela, Tomi P @ 2021-10-05 12:38 UTC (permalink / raw)
To: Nikula, Jani, Patchwork, Latvala, Petri; +Cc: intel-gfx
There was an issue with fd.o expired root cert, and that caused some issues
during the weekend and yesterday, mostly with git fetches. I wonder if this
is related. Can you re-test the patchset and see if the issue persists?
Other patchsets nearby timewise seem to be unaffected by spurious sparses.
Tomi
> From: Nikula, Jani <jani.nikula@intel.com>
>
>
> I wonder what's going on here?!
>
> BR,
> Jani.
>
>
> On Tue, 05 Oct 2021, Patchwork <patchwork@emeril.freedesktop.org>
> wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for
> getting DP PHY name
> > URL : https://patchwork.freedesktop.org/series/95447/
> > State : warning
> >
> > == Summary ==
> >
> > $ dim sparse --fast origin/drm-tip
> > Sparse version: v0.6.2
> > Fast mode used, each commit won't be checked separately.
> > -
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> > +
> > +
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > + #def
> >
> >
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-05 11:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork
@ 2021-10-05 12:22 ` Jani Nikula
2021-10-05 12:38 ` Sarvela, Tomi P
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2021-10-05 12:22 UTC (permalink / raw)
To: Patchwork, Sarvela, Tomi P, Petri Latvala; +Cc: intel-gfx
I wonder what's going on here?!
BR,
Jani.
On Tue, 05 Oct 2021, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
> URL : https://patchwork.freedesktop.org/series/95447/
> State : warning
>
> == Summary ==
>
> $ dim sparse --fast origin/drm-tip
> Sparse version: v0.6.2
> Fast mode used, each commit won't be checked separately.
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> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> + #def
>
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
2021-10-05 8:10 [PATCH 1/2] " Jani Nikula
@ 2021-10-05 11:15 ` Patchwork
2021-10-05 12:22 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Patchwork @ 2021-10-05 11:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name
URL : https://patchwork.freedesktop.org/series/95447/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
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+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #def
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-10-20 0:30 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-19 16:13 [PATCH 1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name Jani Nikula
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
2021-10-19 16:13 ` [PATCH 2/2] drm/i915/dp: use drm_dp_phy_name() for logging Jani Nikula
2021-10-19 16:13 ` [Intel-gfx] " Jani Nikula
2021-10-19 19:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/dp: add drm_dp_phy_name() for getting DP PHY name Patchwork
2021-10-19 19:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-20 0:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-10-05 8:10 [PATCH 1/2] " Jani Nikula
2021-10-05 11:15 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] " Patchwork
2021-10-05 12:22 ` Jani Nikula
2021-10-05 12:38 ` Sarvela, Tomi P
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