* [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
@ 2021-10-27 15:46 Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Stanislav Lisovskiy @ 2021-10-27 15:46 UTC (permalink / raw)
To: intel-gfx
Cc: Stanislav.Lisovskiy, jani.saarinen, matthew.d.roper,
ramalingam.c, ville.syrjala
TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.
v2: - Fixed wrong case condition(Jani Nikula)
- Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
v3: - s/I915_TILING_F/TILING_4/g
- s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
- Removed unneeded fencing code
v4: - Rebased, fixed merge conflict with new table-oriented
format modifier checking(Stan)
- Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_plane_initial.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
include/uapi/drm/drm_fourcc.h | 8 ++++++++
11 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 79cd158503b3..9b3913d73213 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 9ce1d273dc7e..d3dec51285f7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
.modifier = I915_FORMAT_MOD_Yf_TILED,
.display_ver = { 9, 11 },
.tiling = I915_TILING_NONE,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED,
+ .display_ver = { 12, 13 },
+ .tiling = I915_TILING_NONE,
}, {
.modifier = I915_FORMAT_MOD_Y_TILED,
.display_ver = { 9, 13 },
@@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
return 128;
else
return 512;
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+ * Each 4K tile consists of 64B(8*8) subtiles, with
+ * same shape as Y Tile(i.e 4*16B OWords)
+ */
+ return 128;
case I915_FORMAT_MOD_Y_TILED_CCS:
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return 128;
@@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Yf_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1f66de77a6b1..f079a771f802 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_4_TILED:
return DISPLAY_VER(dev_priv) >= 9;
case I915_FORMAT_MOD_X_TILED:
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..d80855ee9b96 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
break;
default:
drm_dbg(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 69fd56de83a7..aeca96925feb 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_X;
case I915_FORMAT_MOD_Y_TILED:
return PLANE_CTL_TILED_Y;
+ case I915_FORMAT_MOD_4_TILED:
+ return PLANE_CTL_TILED_4;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_Y216:
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
- if (modifier == DRM_FORMAT_MOD_LINEAR ||
- modifier == I915_FORMAT_MOD_X_TILED ||
- modifier == I915_FORMAT_MOD_Y_TILED)
+ if (!intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
default:
@@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
else
fb->modifier = I915_FORMAT_MOD_Y_TILED;
break;
- case PLANE_CTL_TILED_YF:
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
- fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
- else
- fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ fb->modifier = I915_FORMAT_MOD_4_TILED;
+ } else {
+ if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+ else
+ fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+ }
break;
default:
MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19e6700a4315..0a32ce800677 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 169837de395d..8831b1885934 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
.display.has_cdclk_crawl = 1,
.display.has_modular_fia = 1,
.display.has_psr_hw_tracking = 0,
+ .has_4tile = 1, \
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c97bc352497..b70b72b032ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7195,6 +7195,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_TILED_4 (5 << 10)
#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8e6f48d1eb7b..6c543a152250 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
func(has_64bit_reloc); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
+ func(has_4tile); \
func(has_global_mocs); \
func(has_gt_uc); \
func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cffb3df35a63..1ac1af0a7f2d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
}
wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_4_TILED ||
modifier == I915_FORMAT_MOD_Yf_TILED ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 45a914850be0..982b0a9fa78b 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -558,6 +558,14 @@ extern "C" {
* pitch is required to be a multiple of 4 tile widths.
*/
#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
@ 2021-10-27 16:56 ` Imre Deak
2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-27 17:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Imre Deak @ 2021-10-27 16:56 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
Is it supported on all D13 or only on DG2? Could you point to the bspec
page describing this?
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 79cd158503b3..9b3913d73213 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 9ce1d273dc7e..d3dec51285f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_Yf_TILED,
> .display_ver = { 9, 11 },
> .tiling = I915_TILING_NONE,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 12, 13 },
From display_ver 13.
> + .tiling = I915_TILING_NONE,
> }, {
> .modifier = I915_FORMAT_MOD_Y_TILED,
> .display_ver = { 9, 13 },
> @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f66de77a6b1..f079a771f802 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 69fd56de83a7..aeca96925feb 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19e6700a4315..0a32ce800677 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..8831b1885934 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> + .has_4tile = 1, \
If it's only on DG2 then it should be added there.
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c97bc352497..b70b72b032ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7195,6 +7195,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8e6f48d1eb7b..6c543a152250 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cffb3df35a63..1ac1af0a7f2d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..982b0a9fa78b 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev2)
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
@ 2021-10-27 17:35 ` Patchwork
2021-10-27 18:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-10-27 17:35 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b258619cd9e1 drm/i915/dg2: Tile 4 plane format support
-:168: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#168: FILE: drivers/gpu/drm/i915/i915_pci.c:975:
+ .has_4tile = 1, \
total: 0 errors, 1 warnings, 0 checks, 137 lines checked
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Tile 4 plane format support (rev2)
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
2021-10-27 17:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
@ 2021-10-27 18:07 ` Patchwork
2021-10-27 20:33 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Ramalingam C
2021-10-28 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-10-27 18:07 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3281 bytes --]
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10797 -> Patchwork_21465
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/index.html
Participating hosts (38 -> 33)
------------------------------
Missing (5): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_21465 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] ([i915#146])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][3] -> [FAIL][4] ([i915#579])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][5] ([i915#4269]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@runner@aborted:
- fi-bsw-kefka: [FAIL][7] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#3428] / [i915#4312]) -> [FAIL][8] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/fi-bsw-kefka/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/fi-bsw-kefka/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Build changes
-------------
* Linux: CI_DRM_10797 -> Patchwork_21465
CI-20190529: 20190529
CI_DRM_10797: 048d1b5b865500e0aad21924985e32a48920b75a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6262: d1c793b26e31cc6ae3f9fa3239805a9bbcc749fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21465: b258619cd9e1d57334811f62cc0670e424a4fa15 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b258619cd9e1 drm/i915/dg2: Tile 4 plane format support
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/index.html
[-- Attachment #2: Type: text/html, Size: 4212 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
` (2 preceding siblings ...)
2021-10-27 18:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-27 20:33 ` Ramalingam C
2021-10-28 7:02 ` Lisovskiy, Stanislav
2021-10-28 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
4 siblings, 1 reply; 12+ messages in thread
From: Ramalingam C @ 2021-10-27 20:33 UTC (permalink / raw)
To: Stanislav Lisovskiy
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ville.syrjala
On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Fixed wrong case condition(Jani Nikula)
> - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
>
> v3: - s/I915_TILING_F/TILING_4/g
> - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> - Removed unneeded fencing code
>
> v4: - Rebased, fixed merge conflict with new table-oriented
> format modifier checking(Stan)
> - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> .../drm/i915/display/intel_plane_initial.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> include/uapi/drm/drm_fourcc.h | 8 ++++++++
> 11 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 79cd158503b3..9b3913d73213 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 9ce1d273dc7e..d3dec51285f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> .modifier = I915_FORMAT_MOD_Yf_TILED,
> .display_ver = { 9, 11 },
> .tiling = I915_TILING_NONE,
> + }, {
> + .modifier = I915_FORMAT_MOD_4_TILED,
> + .display_ver = { 12, 13 },
> + .tiling = I915_TILING_NONE,
> }, {
> .modifier = I915_FORMAT_MOD_Y_TILED,
> .display_ver = { 9, 13 },
> @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> return 128;
> else
> return 512;
> + case I915_FORMAT_MOD_4_TILED:
> + /*
> + * Each 4K tile consists of 64B(8*8) subtiles, with
> + * same shape as Y Tile(i.e 4*16B OWords)
> + */
> + return 128;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> return 128;
> @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> return 1 * 1024 * 1024;
> default:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 1f66de77a6b1..f079a771f802 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_Y_TILED:
> case I915_FORMAT_MOD_Yf_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> return DISPLAY_VER(dev_priv) >= 9;
> case I915_FORMAT_MOD_X_TILED:
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..d80855ee9b96 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> case DRM_FORMAT_MOD_LINEAR:
> case I915_FORMAT_MOD_X_TILED:
> case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> break;
> default:
> drm_dbg(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 69fd56de83a7..aeca96925feb 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> return PLANE_CTL_TILED_X;
> case I915_FORMAT_MOD_Y_TILED:
> return PLANE_CTL_TILED_Y;
> + case I915_FORMAT_MOD_4_TILED:
> + return PLANE_CTL_TILED_4;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_Y216:
> case DRM_FORMAT_XVYU12_16161616:
> case DRM_FORMAT_XVYU16161616:
> - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> - modifier == I915_FORMAT_MOD_X_TILED ||
> - modifier == I915_FORMAT_MOD_Y_TILED)
> + if (!intel_fb_is_ccs_modifier(modifier))
> return true;
> fallthrough;
> default:
> @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> else
> fb->modifier = I915_FORMAT_MOD_Y_TILED;
> break;
> - case PLANE_CTL_TILED_YF:
> - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> - else
> - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + fb->modifier = I915_FORMAT_MOD_4_TILED;
> + } else {
> + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> + else
> + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> + }
> break;
> default:
> MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 19e6700a4315..0a32ce800677 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>
> #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 169837de395d..8831b1885934 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> .display.has_cdclk_crawl = 1,
> .display.has_modular_fia = 1,
> .display.has_psr_hw_tracking = 0,
> + .has_4tile = 1, \
This is applied in wrong place. fixed as part of the series i am preparing.
Ram
> .platform_engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> .ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7c97bc352497..b70b72b032ef 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7195,6 +7195,7 @@ enum {
> #define PLANE_CTL_TILED_X (1 << 10)
> #define PLANE_CTL_TILED_Y (4 << 10)
> #define PLANE_CTL_TILED_YF (5 << 10)
> +#define PLANE_CTL_TILED_4 (5 << 10)
> #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 8e6f48d1eb7b..6c543a152250 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> func(has_64bit_reloc); \
> func(gpu_reset_clobbers_display); \
> func(has_reset_engine); \
> + func(has_4tile); \
> func(has_global_mocs); \
> func(has_gt_uc); \
> func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cffb3df35a63..1ac1af0a7f2d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> }
>
> wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> + modifier == I915_FORMAT_MOD_4_TILED ||
> modifier == I915_FORMAT_MOD_Yf_TILED ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..982b0a9fa78b 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
> * pitch is required to be a multiple of 4 tile widths.
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
>
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> --
> 2.24.1.485.gad05a3d8e5
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Tile 4 plane format support (rev2)
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
` (3 preceding siblings ...)
2021-10-27 20:33 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Ramalingam C
@ 2021-10-28 0:02 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2021-10-28 0:02 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30271 bytes --]
== Series Details ==
Series: drm/i915/dg2: Tile 4 plane format support (rev2)
URL : https://patchwork.freedesktop.org/series/95715/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10797_full -> Patchwork_21465_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21465_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21465_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21465_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
- shard-tglb: [PASS][1] -> [FAIL][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb8/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb8/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_sequence@queue-idle:
- shard-skl: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl9/igt@kms_sequence@queue-idle.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl4/igt@kms_sequence@queue-idle.html
Known issues
------------
Here are the changes found in Patchwork_21465_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56]) ([i915#4338])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb4/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb4/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb2/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb2/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb2/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb7/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb4/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb4/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb4/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb4/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb2/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb2/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb2/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb2/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][57] -> [FAIL][58] ([i915#2842]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-kbl: [PASS][59] -> [FAIL][60] ([i915#2842]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][61] -> [FAIL][62] ([i915#2842])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-glk: [PASS][63] -> [DMESG-WARN][64] ([i915#118])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/igt@gem_exec_whisper@basic-fds-forked.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2190])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#3323])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@gem_userptr_blits@dmabuf-sync.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#1937])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][68] -> [INCOMPLETE][69] ([i915#3921])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb5/igt@i915_selftest@live@hangcheck.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][70] -> [FAIL][71] ([i915#2521])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][72] ([i915#3743]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3777])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3777])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271]) +84 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3777])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271]) +77 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3886]) +4 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +4 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][86] ([i915#1319]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> [TIMEOUT][87] ([i915#1319])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl1/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][88] ([i915#180]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [PASS][89] -> [FAIL][90] ([i915#2346])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][91] -> [INCOMPLETE][92] ([i915#180] / [i915#1982])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
- shard-kbl: [PASS][93] -> [INCOMPLETE][94] ([i915#180] / [i915#636])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271]) +93 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][96] -> [FAIL][97] ([i915#79])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-glk: NOTRUN -> [SKIP][98] ([fdo#109271]) +40 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][99] -> [DMESG-WARN][100] ([i915#180]) +4 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
- shard-apl: [PASS][101] -> [DMESG-WARN][102] ([i915#180]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-apl3/igt@kms_hdr@bpc-switch-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl3/igt@kms_hdr@bpc-switch-suspend.html
- shard-skl: NOTRUN -> [FAIL][103] ([i915#1188])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#533])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][106] -> [FAIL][107] ([fdo#108145] / [i915#265]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][109] ([fdo#108145] / [i915#265])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][110] ([i915#265])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2733])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#658])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658]) +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][114] -> [SKIP][115] ([fdo#109441]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@invalid:
- shard-snb: [PASS][116] -> [SKIP][117] ([fdo#109271]) +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-snb6/igt@kms_vblank@invalid.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-snb7/igt@kms_vblank@invalid.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][118] -> [INCOMPLETE][119] ([i915#198])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#533]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2437])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2437])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@blocking:
- shard-skl: [PASS][123] -> [FAIL][124] ([i915#1542])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl7/igt@perf@blocking.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl8/igt@perf@blocking.html
* igt@sysfs_clients@fair-1:
- shard-skl: NOTRUN -> [SKIP][125] ([fdo#109271] / [i915#2994])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl7/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@pidname:
- shard-kbl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2994])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl6/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#2994]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl1/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@drm_mm@all@insert:
- shard-skl: [INCOMPLETE][128] ([i915#2485]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@drm_mm@all@insert.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl6/igt@drm_mm@all@insert.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [DMESG-WARN][130] ([i915#180]) -> [PASS][131] +6 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][132] ([i915#2410]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [TIMEOUT][134] ([i915#3063]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb5/igt@gem_eio@in-flight-contexts-immediate.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][136] ([i915#2842]) -> [PASS][137] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [FAIL][138] ([i915#2842]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-tglb7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-iclb: [FAIL][140] ([i915#2842]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb7/igt@gem_exec_fair@basic-pace@vcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb8/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][142] ([i915#2842]) -> [PASS][143] +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][144] ([i915#180]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-skl: [DMESG-WARN][146] ([i915#1982]) -> [PASS][147] +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl10/igt@kms_color@pipe-c-ctm-blue-to-red.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl2/igt@kms_color@pipe-c-ctm-blue-to-red.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][148] ([i915#72]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][150] ([i915#2346] / [i915#533]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [FAIL][152] ([i915#2346]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled:
- shard-glk: [DMESG-WARN][154] ([i915#118]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-glk5/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1:
- shard-skl: [FAIL][156] ([i915#2122]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl2/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl10/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][158] ([i915#79]) -> [PASS][159] +1 similar issue
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: [INCOMPLETE][160] ([i915#198]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][162] ([i915#1188]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][164] ([fdo#109441]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][166] ([i915#1804] / [i915#2684]) -> [WARN][167] ([i915#2684])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10797/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/shard-iclb2/igt@i915_
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21465/index.html
[-- Attachment #2: Type: text/html, Size: 33359 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 16:56 ` Imre Deak
@ 2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-28 7:39 ` Imre Deak
0 siblings, 1 reply; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 6:58 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
>
> Is it supported on all D13 or only on DG2? Could you point to the bspec
> page describing this?
Yes, it is supported on all D13 to my undertanding.
Check with BSpec 44917
Stan
>
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 39 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 79cd158503b3..9b3913d73213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 9ce1d273dc7e..d3dec51285f7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > .display_ver = { 9, 11 },
> > .tiling = I915_TILING_NONE,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 12, 13 },
>
> From display_ver 13.
>
> > + .tiling = I915_TILING_NONE,
> > }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED,
> > .display_ver = { 9, 13 },
> > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return 1 * 1024 * 1024;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f66de77a6b1..f079a771f802 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > return DISPLAY_VER(dev_priv) >= 9;
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 69fd56de83a7..aeca96925feb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > + if (DISPLAY_VER(dev_priv) >= 13) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 19e6700a4315..0a32ce800677 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 169837de395d..8831b1885934 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > .display.has_cdclk_crawl = 1,
> > .display.has_modular_fia = 1,
> > .display.has_psr_hw_tracking = 0,
> > + .has_4tile = 1, \
>
> If it's only on DG2 then it should be added there.
>
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > .ppgtt_size = 48,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7c97bc352497..b70b72b032ef 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7195,6 +7195,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 8e6f48d1eb7b..6c543a152250 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cffb3df35a63..1ac1af0a7f2d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 45a914850be0..982b0a9fa78b 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -558,6 +558,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-27 20:33 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Ramalingam C
@ 2021-10-28 7:02 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:02 UTC (permalink / raw)
To: Ramalingam C; +Cc: intel-gfx, jani.saarinen, matthew.d.roper, ville.syrjala
On Thu, Oct 28, 2021 at 02:03:49AM +0530, Ramalingam C wrote:
> On 2021-10-27 at 18:46:53 +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> >
> > v2: - Fixed wrong case condition(Jani Nikula)
> > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> >
> > v3: - s/I915_TILING_F/TILING_4/g
> > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > - Removed unneeded fencing code
> >
> > v4: - Rebased, fixed merge conflict with new table-oriented
> > format modifier checking(Stan)
> > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > .../drm/i915/display/intel_plane_initial.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > 11 files changed, 39 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 79cd158503b3..9b3913d73213 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 9ce1d273dc7e..d3dec51285f7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > .display_ver = { 9, 11 },
> > .tiling = I915_TILING_NONE,
> > + }, {
> > + .modifier = I915_FORMAT_MOD_4_TILED,
> > + .display_ver = { 12, 13 },
> > + .tiling = I915_TILING_NONE,
> > }, {
> > .modifier = I915_FORMAT_MOD_Y_TILED,
> > .display_ver = { 9, 13 },
> > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > return 128;
> > else
> > return 512;
> > + case I915_FORMAT_MOD_4_TILED:
> > + /*
> > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > + * same shape as Y Tile(i.e 4*16B OWords)
> > + */
> > + return 128;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > return 128;
> > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > return 1 * 1024 * 1024;
> > default:
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f66de77a6b1..f079a771f802 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_Y_TILED:
> > case I915_FORMAT_MOD_Yf_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > return DISPLAY_VER(dev_priv) >= 9;
> > case I915_FORMAT_MOD_X_TILED:
> > return true;
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index dcd698a02da2..d80855ee9b96 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > case DRM_FORMAT_MOD_LINEAR:
> > case I915_FORMAT_MOD_X_TILED:
> > case I915_FORMAT_MOD_Y_TILED:
> > + case I915_FORMAT_MOD_4_TILED:
> > break;
> > default:
> > drm_dbg(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 69fd56de83a7..aeca96925feb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > return PLANE_CTL_TILED_X;
> > case I915_FORMAT_MOD_Y_TILED:
> > return PLANE_CTL_TILED_Y;
> > + case I915_FORMAT_MOD_4_TILED:
> > + return PLANE_CTL_TILED_4;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > case DRM_FORMAT_Y216:
> > case DRM_FORMAT_XVYU12_16161616:
> > case DRM_FORMAT_XVYU16161616:
> > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > - modifier == I915_FORMAT_MOD_X_TILED ||
> > - modifier == I915_FORMAT_MOD_Y_TILED)
> > + if (!intel_fb_is_ccs_modifier(modifier))
> > return true;
> > fallthrough;
> > default:
> > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > else
> > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > break;
> > - case PLANE_CTL_TILED_YF:
> > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > - else
> > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > + if (DISPLAY_VER(dev_priv) >= 13) {
> > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > + } else {
> > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > + else
> > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > + }
> > break;
> > default:
> > MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 19e6700a4315..0a32ce800677 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >
> > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 169837de395d..8831b1885934 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > .display.has_cdclk_crawl = 1,
> > .display.has_modular_fia = 1,
> > .display.has_psr_hw_tracking = 0,
> > + .has_4tile = 1, \
> This is applied in wrong place. fixed as part of the series i am preparing.
>
> Ram
I think the structure is still adl_p_info in your patch, do you mean it should be inserted
in other place?
Stan
> > .platform_engine_mask =
> > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > .ppgtt_size = 48,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7c97bc352497..b70b72b032ef 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7195,6 +7195,7 @@ enum {
> > #define PLANE_CTL_TILED_X (1 << 10)
> > #define PLANE_CTL_TILED_Y (4 << 10)
> > #define PLANE_CTL_TILED_YF (5 << 10)
> > +#define PLANE_CTL_TILED_4 (5 << 10)
> > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 8e6f48d1eb7b..6c543a152250 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > func(has_64bit_reloc); \
> > func(gpu_reset_clobbers_display); \
> > func(has_reset_engine); \
> > + func(has_4tile); \
> > func(has_global_mocs); \
> > func(has_gt_uc); \
> > func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cffb3df35a63..1ac1af0a7f2d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > }
> >
> > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > + modifier == I915_FORMAT_MOD_4_TILED ||
> > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 45a914850be0..982b0a9fa78b 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -558,6 +558,14 @@ extern "C" {
> > * pitch is required to be a multiple of 4 tile widths.
> > */
> > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
> > + */
> > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> >
> > /*
> > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > --
> > 2.24.1.485.gad05a3d8e5
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 6:58 ` Lisovskiy, Stanislav
@ 2021-10-28 7:39 ` Imre Deak
2021-10-28 7:49 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 12+ messages in thread
From: Imre Deak @ 2021-10-28 7:39 UTC (permalink / raw)
To: Lisovskiy, Stanislav
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > 64B subtiles with same basic shape as for legacy TileY
> > > which will be supported by Display13.
> >
> > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > page describing this?
>
> Yes, it is supported on all D13 to my undertanding.
> Check with BSpec 44917
Thanks.
Based on that page it's only supported on DG2 (and that's how the driver
worked so far in the internal tree).
> Stan
>
> >
> > >
> > > v2: - Fixed wrong case condition(Jani Nikula)
> > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > >
> > > v3: - s/I915_TILING_F/TILING_4/g
> > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > - Removed unneeded fencing code
> > >
> > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > format modifier checking(Stan)
> > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 79cd158503b3..9b3913d73213 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg_kms(&i915->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > .display_ver = { 9, 11 },
> > > .tiling = I915_TILING_NONE,
> > > + }, {
> > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > + .display_ver = { 12, 13 },
> >
> > From display_ver 13.
> >
> > > + .tiling = I915_TILING_NONE,
> > > }, {
> > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > .display_ver = { 9, 13 },
> > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > return 128;
> > > else
> > > return 512;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + /*
> > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > + */
> > > + return 128;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > return 128;
> > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > return 1 * 1024 * 1024;
> > > default:
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index 1f66de77a6b1..f079a771f802 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > case DRM_FORMAT_MOD_LINEAR:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > return DISPLAY_VER(dev_priv) >= 9;
> > > case I915_FORMAT_MOD_X_TILED:
> > > return true;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > index dcd698a02da2..d80855ee9b96 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > case DRM_FORMAT_MOD_LINEAR:
> > > case I915_FORMAT_MOD_X_TILED:
> > > case I915_FORMAT_MOD_Y_TILED:
> > > + case I915_FORMAT_MOD_4_TILED:
> > > break;
> > > default:
> > > drm_dbg(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 69fd56de83a7..aeca96925feb 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > return PLANE_CTL_TILED_X;
> > > case I915_FORMAT_MOD_Y_TILED:
> > > return PLANE_CTL_TILED_Y;
> > > + case I915_FORMAT_MOD_4_TILED:
> > > + return PLANE_CTL_TILED_4;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > case DRM_FORMAT_Y216:
> > > case DRM_FORMAT_XVYU12_16161616:
> > > case DRM_FORMAT_XVYU16161616:
> > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > return true;
> > > fallthrough;
> > > default:
> > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > else
> > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > break;
> > > - case PLANE_CTL_TILED_YF:
> > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > - else
> > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > + } else {
> > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > + else
> > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > + }
> > > break;
> > > default:
> > > MISSING_CASE(tiling);
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 19e6700a4315..0a32ce800677 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > >
> > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > index 169837de395d..8831b1885934 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > .display.has_cdclk_crawl = 1,
> > > .display.has_modular_fia = 1,
> > > .display.has_psr_hw_tracking = 0,
> > > + .has_4tile = 1, \
> >
> > If it's only on DG2 then it should be added there.
> >
> > > .platform_engine_mask =
> > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > .ppgtt_size = 48,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 7c97bc352497..b70b72b032ef 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7195,6 +7195,7 @@ enum {
> > > #define PLANE_CTL_TILED_X (1 << 10)
> > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > index 8e6f48d1eb7b..6c543a152250 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > func(has_64bit_reloc); \
> > > func(gpu_reset_clobbers_display); \
> > > func(has_reset_engine); \
> > > + func(has_4tile); \
> > > func(has_global_mocs); \
> > > func(has_gt_uc); \
> > > func(has_l3_dpf); \
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > }
> > >
> > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > index 45a914850be0..982b0a9fa78b 100644
> > > --- a/include/uapi/drm/drm_fourcc.h
> > > +++ b/include/uapi/drm/drm_fourcc.h
> > > @@ -558,6 +558,14 @@ extern "C" {
> > > * pitch is required to be a multiple of 4 tile widths.
> > > */
> > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > +/*
> > > + * Intel F-tiling(aka Tile4) layout
> > > + *
> > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > + * (16 bytes) chunks column-major..
> > > + */
> > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > >
> > > /*
> > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > --
> > > 2.24.1.485.gad05a3d8e5
> > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:39 ` Imre Deak
@ 2021-10-28 7:49 ` Lisovskiy, Stanislav
2021-10-28 7:53 ` Imre Deak
0 siblings, 1 reply; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:49 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > 64B subtiles with same basic shape as for legacy TileY
> > > > which will be supported by Display13.
> > >
> > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > page describing this?
> >
> > Yes, it is supported on all D13 to my undertanding.
> > Check with BSpec 44917
>
> Thanks.
>
> Based on that page it's only supported on DG2 (and that's how the driver
> worked so far in the internal tree).
I think its supported on some other platforms as well - when you click the Tile 4
section, check platform names in the brackets.
Stan
>
> > Stan
> >
> > >
> > > >
> > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > >
> > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > - Removed unneeded fencing code
> > > >
> > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > format modifier checking(Stan)
> > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > >
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 79cd158503b3..9b3913d73213 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg_kms(&i915->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > .display_ver = { 9, 11 },
> > > > .tiling = I915_TILING_NONE,
> > > > + }, {
> > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > + .display_ver = { 12, 13 },
> > >
> > > From display_ver 13.
> > >
> > > > + .tiling = I915_TILING_NONE,
> > > > }, {
> > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > .display_ver = { 9, 13 },
> > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > return 128;
> > > > else
> > > > return 512;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + /*
> > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > + */
> > > > + return 128;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > return 128;
> > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > return 1 * 1024 * 1024;
> > > > default:
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index 1f66de77a6b1..f079a771f802 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > case DRM_FORMAT_MOD_LINEAR:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > return true;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > index dcd698a02da2..d80855ee9b96 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > case DRM_FORMAT_MOD_LINEAR:
> > > > case I915_FORMAT_MOD_X_TILED:
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > break;
> > > > default:
> > > > drm_dbg(&dev_priv->drm,
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > index 69fd56de83a7..aeca96925feb 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > return PLANE_CTL_TILED_X;
> > > > case I915_FORMAT_MOD_Y_TILED:
> > > > return PLANE_CTL_TILED_Y;
> > > > + case I915_FORMAT_MOD_4_TILED:
> > > > + return PLANE_CTL_TILED_4;
> > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > case DRM_FORMAT_Y216:
> > > > case DRM_FORMAT_XVYU12_16161616:
> > > > case DRM_FORMAT_XVYU16161616:
> > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > return true;
> > > > fallthrough;
> > > > default:
> > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > else
> > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > break;
> > > > - case PLANE_CTL_TILED_YF:
> > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > - else
> > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > + } else {
> > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > + else
> > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > + }
> > > > break;
> > > > default:
> > > > MISSING_CASE(tiling);
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 19e6700a4315..0a32ce800677 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > >
> > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > index 169837de395d..8831b1885934 100644
> > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > .display.has_cdclk_crawl = 1,
> > > > .display.has_modular_fia = 1,
> > > > .display.has_psr_hw_tracking = 0,
> > > > + .has_4tile = 1, \
> > >
> > > If it's only on DG2 then it should be added there.
> > >
> > > > .platform_engine_mask =
> > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > .ppgtt_size = 48,
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 7c97bc352497..b70b72b032ef 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7195,6 +7195,7 @@ enum {
> > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > func(has_64bit_reloc); \
> > > > func(gpu_reset_clobbers_display); \
> > > > func(has_reset_engine); \
> > > > + func(has_4tile); \
> > > > func(has_global_mocs); \
> > > > func(has_gt_uc); \
> > > > func(has_l3_dpf); \
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > }
> > > >
> > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > index 45a914850be0..982b0a9fa78b 100644
> > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > * pitch is required to be a multiple of 4 tile widths.
> > > > */
> > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > +/*
> > > > + * Intel F-tiling(aka Tile4) layout
> > > > + *
> > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > + * (16 bytes) chunks column-major..
> > > > + */
> > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > >
> > > > /*
> > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > --
> > > > 2.24.1.485.gad05a3d8e5
> > > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:49 ` Lisovskiy, Stanislav
@ 2021-10-28 7:53 ` Imre Deak
2021-10-28 7:57 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 12+ messages in thread
From: Imre Deak @ 2021-10-28 7:53 UTC (permalink / raw)
To: Lisovskiy, Stanislav
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:49:34AM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> > On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > which will be supported by Display13.
> > > >
> > > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > > page describing this?
> > >
> > > Yes, it is supported on all D13 to my undertanding.
> > > Check with BSpec 44917
> >
> > Thanks.
> >
> > Based on that page it's only supported on DG2 (and that's how the driver
> > worked so far in the internal tree).
>
> I think its supported on some other platforms as well - when you click the Tile 4
> section, check platform names in the brackets.
Right, but from Display 13 platforms it's only DG2 (and not ADL-P the
only other D13 platform).
>
> Stan
>
> >
> > > Stan
> > >
> > > >
> > > > >
> > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > >
> > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > - Removed unneeded fencing code
> > > > >
> > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > format modifier checking(Stan)
> > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > >
> > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 79cd158503b3..9b3913d73213 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg_kms(&i915->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > > .display_ver = { 9, 11 },
> > > > > .tiling = I915_TILING_NONE,
> > > > > + }, {
> > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > + .display_ver = { 12, 13 },
> > > >
> > > > From display_ver 13.
> > > >
> > > > > + .tiling = I915_TILING_NONE,
> > > > > }, {
> > > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > > .display_ver = { 9, 13 },
> > > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > > return 128;
> > > > > else
> > > > > return 512;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + /*
> > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > + */
> > > > > + return 128;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > return 128;
> > > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > return 1 * 1024 * 1024;
> > > > > default:
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > index 1f66de77a6b1..f079a771f802 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > return true;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > break;
> > > > > default:
> > > > > drm_dbg(&dev_priv->drm,
> > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > index 69fd56de83a7..aeca96925feb 100644
> > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > return PLANE_CTL_TILED_X;
> > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > return PLANE_CTL_TILED_Y;
> > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > + return PLANE_CTL_TILED_4;
> > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > case DRM_FORMAT_Y216:
> > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > case DRM_FORMAT_XVYU16161616:
> > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > return true;
> > > > > fallthrough;
> > > > > default:
> > > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > else
> > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > break;
> > > > > - case PLANE_CTL_TILED_YF:
> > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > - else
> > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > + } else {
> > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > + else
> > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > + }
> > > > > break;
> > > > > default:
> > > > > MISSING_CASE(tiling);
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index 19e6700a4315..0a32ce800677 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > > >
> > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > > index 169837de395d..8831b1885934 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > > .display.has_cdclk_crawl = 1,
> > > > > .display.has_modular_fia = 1,
> > > > > .display.has_psr_hw_tracking = 0,
> > > > > + .has_4tile = 1, \
> > > >
> > > > If it's only on DG2 then it should be added there.
> > > >
> > > > > .platform_engine_mask =
> > > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > > .ppgtt_size = 48,
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index 7c97bc352497..b70b72b032ef 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -7195,6 +7195,7 @@ enum {
> > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > func(has_64bit_reloc); \
> > > > > func(gpu_reset_clobbers_display); \
> > > > > func(has_reset_engine); \
> > > > > + func(has_4tile); \
> > > > > func(has_global_mocs); \
> > > > > func(has_gt_uc); \
> > > > > func(has_l3_dpf); \
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > > }
> > > > >
> > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > > index 45a914850be0..982b0a9fa78b 100644
> > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > */
> > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > > +/*
> > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > + *
> > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > + * (16 bytes) chunks column-major..
> > > > > + */
> > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > > >
> > > > > /*
> > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > --
> > > > > 2.24.1.485.gad05a3d8e5
> > > > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support
2021-10-28 7:53 ` Imre Deak
@ 2021-10-28 7:57 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 12+ messages in thread
From: Lisovskiy, Stanislav @ 2021-10-28 7:57 UTC (permalink / raw)
To: Imre Deak
Cc: intel-gfx, jani.saarinen, matthew.d.roper, ramalingam.c, ville.syrjala
On Thu, Oct 28, 2021 at 10:53:25AM +0300, Imre Deak wrote:
> On Thu, Oct 28, 2021 at 10:49:34AM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Oct 28, 2021 at 10:39:42AM +0300, Imre Deak wrote:
> > > On Thu, Oct 28, 2021 at 09:58:52AM +0300, Lisovskiy, Stanislav wrote:
> > > > On Wed, Oct 27, 2021 at 07:56:25PM +0300, Imre Deak wrote:
> > > > > On Wed, Oct 27, 2021 at 06:46:53PM +0300, Stanislav Lisovskiy wrote:
> > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > which will be supported by Display13.
> > > > >
> > > > > Is it supported on all D13 or only on DG2? Could you point to the bspec
> > > > > page describing this?
> > > >
> > > > Yes, it is supported on all D13 to my undertanding.
> > > > Check with BSpec 44917
> > >
> > > Thanks.
> > >
> > > Based on that page it's only supported on DG2 (and that's how the driver
> > > worked so far in the internal tree).
> >
> > I think its supported on some other platforms as well - when you click the Tile 4
> > section, check platform names in the brackets.
>
> Right, but from Display 13 platforms it's only DG2 (and not ADL-P the
> only other D13 platform).
True.
>
> >
> > Stan
> >
> > >
> > > > Stan
> > > >
> > > > >
> > > > > >
> > > > > > v2: - Fixed wrong case condition(Jani Nikula)
> > > > > > - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)
> > > > > >
> > > > > > v3: - s/I915_TILING_F/TILING_4/g
> > > > > > - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g
> > > > > > - Removed unneeded fencing code
> > > > > >
> > > > > > v4: - Rebased, fixed merge conflict with new table-oriented
> > > > > > format modifier checking(Stan)
> > > > > > - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan)
> > > > > >
> > > > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++++++
> > > > > > drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> > > > > > .../drm/i915/display/intel_plane_initial.c | 1 +
> > > > > > .../drm/i915/display/skl_universal_plane.c | 20 +++++++++++--------
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > > > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > > > > > drivers/gpu/drm/i915/intel_pm.c | 1 +
> > > > > > include/uapi/drm/drm_fourcc.h | 8 ++++++++
> > > > > > 11 files changed, 39 insertions(+), 8 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 79cd158503b3..9b3913d73213 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -7755,6 +7755,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg_kms(&i915->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > index 9ce1d273dc7e..d3dec51285f7 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > > @@ -188,6 +188,10 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> > > > > > .modifier = I915_FORMAT_MOD_Yf_TILED,
> > > > > > .display_ver = { 9, 11 },
> > > > > > .tiling = I915_TILING_NONE,
> > > > > > + }, {
> > > > > > + .modifier = I915_FORMAT_MOD_4_TILED,
> > > > > > + .display_ver = { 12, 13 },
> > > > >
> > > > > From display_ver 13.
> > > > >
> > > > > > + .tiling = I915_TILING_NONE,
> > > > > > }, {
> > > > > > .modifier = I915_FORMAT_MOD_Y_TILED,
> > > > > > .display_ver = { 9, 13 },
> > > > > > @@ -575,6 +579,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > > > > return 128;
> > > > > > else
> > > > > > return 512;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + /*
> > > > > > + * Each 4K tile consists of 64B(8*8) subtiles, with
> > > > > > + * same shape as Y Tile(i.e 4*16B OWords)
> > > > > > + */
> > > > > > + return 128;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> > > > > > return 128;
> > > > > > @@ -743,6 +753,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > return 1 * 1024 * 1024;
> > > > > > default:
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > index 1f66de77a6b1..f079a771f802 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > > > @@ -747,6 +747,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > case I915_FORMAT_MOD_Yf_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > return DISPLAY_VER(dev_priv) >= 9;
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > return true;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > index dcd698a02da2..d80855ee9b96 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > > > > > @@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> > > > > > case DRM_FORMAT_MOD_LINEAR:
> > > > > > case I915_FORMAT_MOD_X_TILED:
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > break;
> > > > > > default:
> > > > > > drm_dbg(&dev_priv->drm,
> > > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > index 69fd56de83a7..aeca96925feb 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > @@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > > > > > return PLANE_CTL_TILED_X;
> > > > > > case I915_FORMAT_MOD_Y_TILED:
> > > > > > return PLANE_CTL_TILED_Y;
> > > > > > + case I915_FORMAT_MOD_4_TILED:
> > > > > > + return PLANE_CTL_TILED_4;
> > > > > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > > > > case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > > > > > return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > > > > @@ -1930,9 +1932,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > > > > > case DRM_FORMAT_Y216:
> > > > > > case DRM_FORMAT_XVYU12_16161616:
> > > > > > case DRM_FORMAT_XVYU16161616:
> > > > > > - if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > > > > > - modifier == I915_FORMAT_MOD_X_TILED ||
> > > > > > - modifier == I915_FORMAT_MOD_Y_TILED)
> > > > > > + if (!intel_fb_is_ccs_modifier(modifier))
> > > > > > return true;
> > > > > > fallthrough;
> > > > > > default:
> > > > > > @@ -2241,11 +2241,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> > > > > > else
> > > > > > fb->modifier = I915_FORMAT_MOD_Y_TILED;
> > > > > > break;
> > > > > > - case PLANE_CTL_TILED_YF:
> > > > > > - if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > - else
> > > > > > - fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > > > > > + if (DISPLAY_VER(dev_priv) >= 13) {
> > > > > > + fb->modifier = I915_FORMAT_MOD_4_TILED;
> > > > > > + } else {
> > > > > > + if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > + else
> > > > > > + fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > > > > > + }
> > > > > > break;
> > > > > > default:
> > > > > > MISSING_CASE(tiling);
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > index 19e6700a4315..0a32ce800677 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > @@ -1627,6 +1627,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > > > #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> > > > > >
> > > > > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
> > > > > > +#define HAS_FTILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
> > > > > > #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
> > > > > > #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
> > > > > > #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > index 169837de395d..8831b1885934 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > > > > @@ -972,6 +972,7 @@ static const struct intel_device_info adl_p_info = {
> > > > > > .display.has_cdclk_crawl = 1,
> > > > > > .display.has_modular_fia = 1,
> > > > > > .display.has_psr_hw_tracking = 0,
> > > > > > + .has_4tile = 1, \
> > > > >
> > > > > If it's only on DG2 then it should be added there.
> > > > >
> > > > > > .platform_engine_mask =
> > > > > > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> > > > > > .ppgtt_size = 48,
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > index 7c97bc352497..b70b72b032ef 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > > @@ -7195,6 +7195,7 @@ enum {
> > > > > > #define PLANE_CTL_TILED_X (1 << 10)
> > > > > > #define PLANE_CTL_TILED_Y (4 << 10)
> > > > > > #define PLANE_CTL_TILED_YF (5 << 10)
> > > > > > +#define PLANE_CTL_TILED_4 (5 << 10)
> > > > > > #define PLANE_CTL_ASYNC_FLIP (1 << 9)
> > > > > > #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
> > > > > > #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > index 8e6f48d1eb7b..6c543a152250 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > > > > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> > > > > > func(has_64bit_reloc); \
> > > > > > func(gpu_reset_clobbers_display); \
> > > > > > func(has_reset_engine); \
> > > > > > + func(has_4tile); \
> > > > > > func(has_global_mocs); \
> > > > > > func(has_gt_uc); \
> > > > > > func(has_l3_dpf); \
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > index cffb3df35a63..1ac1af0a7f2d 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > > @@ -5378,6 +5378,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> > > > > > }
> > > > > >
> > > > > > wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > > > > > + modifier == I915_FORMAT_MOD_4_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED ||
> > > > > > modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > > > > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > > > > > index 45a914850be0..982b0a9fa78b 100644
> > > > > > --- a/include/uapi/drm/drm_fourcc.h
> > > > > > +++ b/include/uapi/drm/drm_fourcc.h
> > > > > > @@ -558,6 +558,14 @@ extern "C" {
> > > > > > * pitch is required to be a multiple of 4 tile widths.
> > > > > > */
> > > > > > #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > > > > > +/*
> > > > > > + * Intel F-tiling(aka Tile4) layout
> > > > > > + *
> > > > > > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > > > > > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > > > > > + * (16 bytes) chunks column-major..
> > > > > > + */
> > > > > > +#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 12)
> > > > > >
> > > > > > /*
> > > > > > * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > > > > > --
> > > > > > 2.24.1.485.gad05a3d8e5
> > > > > >
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-10-28 8:04 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-27 15:46 [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Stanislav Lisovskiy
2021-10-27 16:56 ` Imre Deak
2021-10-28 6:58 ` Lisovskiy, Stanislav
2021-10-28 7:39 ` Imre Deak
2021-10-28 7:49 ` Lisovskiy, Stanislav
2021-10-28 7:53 ` Imre Deak
2021-10-28 7:57 ` Lisovskiy, Stanislav
2021-10-27 17:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
2021-10-27 18:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-27 20:33 ` [Intel-gfx] [PATCH] drm/i915/dg2: Tile 4 plane format support Ramalingam C
2021-10-28 7:02 ` Lisovskiy, Stanislav
2021-10-28 0:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Tile 4 plane format support (rev2) Patchwork
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