* [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
@ 2021-10-27 18:48 José Roberto de Souza
2021-10-27 21:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: José Roberto de Souza @ 2021-10-27 18:48 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kahola, Jouni Hogander, José Roberto de Souza
Async flips are not supported by selective fetch and we had a check
for that but that check was only executed when doing modesets.
So moving this check to the page flip path, so it can be properly
handled.
This fix a failure in kms_async_flips@test-cursor.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Jouni Hogander <jouni.hogander@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8d08e3cf08c1f..ce6850ed72c60 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (crtc_state->uapi.async_flip) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR2 sel fetch not enabled, async flip enabled\n");
- return false;
- }
-
/* Wa_14010254185 Wa_14010103792 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
drm_dbg_kms(&dev_priv->drm,
@@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
{
if (crtc_state->scaler_state.scaler_id >= 0)
return false;
+ if (crtc_state->uapi.async_flip)
+ return false;
return true;
}
--
2.33.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr2: Do full fetches when doing async flips
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
@ 2021-10-27 21:31 ` Patchwork
2021-10-28 4:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-10-27 21:31 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2706 bytes --]
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips
URL : https://patchwork.freedesktop.org/series/96357/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10799 -> Patchwork_21468
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/index.html
Participating hosts (37 -> 34)
------------------------------
Additional (1): fi-pnv-d510
Missing (4): fi-bsw-cyan bat-adlp-4 bat-dg1-6 bat-dg1-5
Known issues
------------
Here are the changes found in Patchwork_21468 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@requests:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][1] ([i915#4140])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][2] ([fdo#109271]) +35 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][3] ([fdo#109271] / [i915#2403] / [i915#4312])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/fi-pnv-d510/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][4] ([i915#4269]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#4140]: https://gitlab.freedesktop.org/drm/intel/issues/4140
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
Build changes
-------------
* Linux: CI_DRM_10799 -> Patchwork_21468
CI-20190529: 20190529
CI_DRM_10799: 9f1a26b0a231c3e7991d70b8622e47e1041467f1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6262: d1c793b26e31cc6ae3f9fa3239805a9bbcc749fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21468: 87a46626faf65c5acd9c6aa68a63d8f8546083cf @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
87a46626faf6 drm/i915/psr2: Do full fetches when doing async flips
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/index.html
[-- Attachment #2: Type: text/html, Size: 3455 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr2: Do full fetches when doing async flips
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
2021-10-27 21:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-10-28 4:53 ` Patchwork
2021-10-28 5:59 ` [Intel-gfx] [PATCH] " Karthik B S
` (2 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-10-28 4:53 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30276 bytes --]
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips
URL : https://patchwork.freedesktop.org/series/96357/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10799_full -> Patchwork_21468_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21468_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21468_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21468_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_hdr@bpc-switch-dpms:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb7/igt@kms_hdr@bpc-switch-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb8/igt@kms_hdr@bpc-switch-dpms.html
Known issues
------------
Here are the changes found in Patchwork_21468_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [FAIL][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk8/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk5/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk5/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk3/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk5/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk5/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk2/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk2/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk3/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk9/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk9/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk8/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk8/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk7/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk7/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk7/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk6/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk6/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-skl: [PASS][53] -> [INCOMPLETE][54] ([i915#198])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][55] -> [TIMEOUT][56] ([i915#3063])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb8/igt@gem_eio@in-flight-contexts-1us.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb1/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][57] -> [TIMEOUT][58] ([i915#2369] / [i915#3063] / [i915#3648])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb1/igt@gem_eio@unwedge-stress.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][59] ([i915#2846])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][60] -> [FAIL][61] ([i915#2842]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb8/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][64] ([i915#2842])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][65] -> [FAIL][66] ([i915#2842]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-sync@rcs0:
- shard-kbl: [PASS][67] -> [SKIP][68] ([fdo#109271])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl7/igt@gem_exec_fair@basic-sync@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@gem_exec_fair@basic-sync@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][69] -> [FAIL][70] ([i915#2849])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][71] -> [DMESG-WARN][72] ([i915#180])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-iclb: [PASS][73] -> [INCOMPLETE][74] ([i915#1895])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb1/igt@gem_exec_whisper@basic-queues-forked-all.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb7/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][75] -> [SKIP][76] ([i915#2190])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][77] ([i915#3318])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume:
- shard-tglb: [PASS][78] -> [INCOMPLETE][79] ([i915#456]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb8/igt@gem_workarounds@suspend-resume.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb7/igt@gem_workarounds@suspend-resume.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3777])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3777])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3777]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][83] ([i915#3743]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271]) +129 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3886]) +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3886])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +12 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +7 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl2/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-audio-edid:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [fdo#111827]) +9 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_chamelium@hdmi-audio-edid.html
* igt@kms_chamelium@hdmi-hpd:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827]) +8 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl2/igt@kms_chamelium@vga-edid-read.html
* igt@kms_color@pipe-b-ctm-green-to-red:
- shard-skl: [PASS][92] -> [DMESG-WARN][93] ([i915#1982])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl1/igt@kms_color@pipe-b-ctm-green-to-red.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl7/igt@kms_color@pipe-b-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [fdo#111827]) +14 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][95] ([i915#1319])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl1/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][96] ([i915#1319]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl6/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][97] -> [DMESG-WARN][98] ([i915#180]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271]) +125 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][100] -> [FAIL][101] ([i915#79])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: NOTRUN -> [INCOMPLETE][102] ([i915#198])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2672])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][104] ([fdo#109271]) +158 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-glk: NOTRUN -> [SKIP][105] ([fdo#109271]) +34 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#1188])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#533])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#533])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#533])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-glk: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#533])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265]) +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][114] -> [FAIL][115] ([fdo#108145] / [i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#658])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#658])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658]) +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl9/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@frontbuffer:
- shard-kbl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl3/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][121] -> [SKIP][122] ([fdo#109441])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb5/igt@kms_psr@psr2_primary_blt.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][123] ([IGT#2])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl9/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [PASS][124] -> [INCOMPLETE][125] ([i915#198] / [i915#2828])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl8/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [PASS][126] -> [INCOMPLETE][127] ([i915#3896])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb6/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-busy-hang:
- shard-iclb: NOTRUN -> [SKIP][128] ([fdo#109278])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb5/igt@kms_vblank@pipe-d-wait-forked-busy-hang.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#2437])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@kms_writeback@writeback-check-output.html
* igt@perf@polling-parameterized:
- shard-skl: NOTRUN -> [FAIL][130] ([i915#1542])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl7/igt@perf@polling-parameterized.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][131] ([fdo#109295])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb5/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#2994]) +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl8/igt@sysfs_clients@busy.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#2994]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl1/igt@sysfs_clients@sema-50.html
- shard-apl: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#2994]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl1/igt@sysfs_clients@sema-50.html
* igt@sysfs_clients@split-50:
- shard-glk: NOTRUN -> [SKIP][135] ([fdo#109271] / [i915#2994])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk1/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [SKIP][136] ([fdo#109271]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][138] ([i915#2842]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb8/igt@gem_exec_fair@basic-pace@bcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-iclb5/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [SKIP][140] ([fdo#109271]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_userptr_blits@huge-split:
- shard-tglb: [FAIL][142] ([i915#3376]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb3/igt@gem_userptr_blits@huge-split.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb3/igt@gem_userptr_blits@huge-split.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][144] ([i915#180]) -> [PASS][145] +4 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][146] ([i915#2346]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][148] ([i915#180] / [i915#636]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][150] ([i915#79]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][152] ([i915#180]) -> [PASS][153] +7 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-tglb: [DMESG-WARN][154] ([i915#2411] / [i915#2867]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-tglb5/igt@kms_flip@flip-vs-suspend@c-edp1.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-tglb5/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][156] ([i915#1188]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl8/igt@kms_hdr@bpc-switch.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][158] ([i915#31]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl2/igt@kms_setmode@basic.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl4/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][160] ([i915#180] / [i915#295]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@blocking:
- shard-skl: [FAIL][162] ([i915#1542]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-skl7/igt@perf@blocking.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-skl6/igt@perf@blocking.html
* igt@perf@polling-parameterized:
- shard-apl: [FAIL][164] ([i915#1542]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-apl7/igt@perf@polling-parameterized.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/shard-apl4/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][166] ([i915#4281]) -> [FAIL][167] ([i915#4275])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10799/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21468/index.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
2021-10-27 21:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-28 4:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-10-28 5:59 ` Karthik B S
2021-10-28 13:32 ` Ville Syrjälä
2021-10-28 21:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/psr2: Do full fetches when doing async flips (rev3) Patchwork
4 siblings, 0 replies; 14+ messages in thread
From: Karthik B S @ 2021-10-28 5:59 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx; +Cc: Mika Kahola, Jouni Hogander
On 10/28/2021 12:18 AM, José Roberto de Souza wrote:
> Async flips are not supported by selective fetch and we had a check
> for that but that check was only executed when doing modesets.
> So moving this check to the page flip path, so it can be properly
> handled.
>
> This fix a failure in kms_async_flips@test-cursor.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Jouni Hogander <jouni.hogander@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8d08e3cf08c1f..ce6850ed72c60 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> - if (crtc_state->uapi.async_flip) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR2 sel fetch not enabled, async flip enabled\n");
> - return false;
> - }
> -
> /* Wa_14010254185 Wa_14010103792 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> drm_dbg_kms(&dev_priv->drm,
> @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> {
> if (crtc_state->scaler_state.scaler_id >= 0)
> return false;
> + if (crtc_state->uapi.async_flip)
> + return false;
>
> return true;
> }
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
` (2 preceding siblings ...)
2021-10-28 5:59 ` [Intel-gfx] [PATCH] " Karthik B S
@ 2021-10-28 13:32 ` Ville Syrjälä
2021-10-28 17:02 ` Souza, Jose
2021-10-28 21:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/psr2: Do full fetches when doing async flips (rev3) Patchwork
4 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2021-10-28 13:32 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Mika Kahola, Jouni Hogander
On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> Async flips are not supported by selective fetch and we had a check
> for that but that check was only executed when doing modesets.
> So moving this check to the page flip path, so it can be properly
> handled.
>
> This fix a failure in kms_async_flips@test-cursor.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Jouni Hogander <jouni.hogander@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8d08e3cf08c1f..ce6850ed72c60 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> - if (crtc_state->uapi.async_flip) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR2 sel fetch not enabled, async flip enabled\n");
> - return false;
> - }
> -
> /* Wa_14010254185 Wa_14010103792 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> drm_dbg_kms(&dev_priv->drm,
> @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> {
> if (crtc_state->scaler_state.scaler_id >= 0)
> return false;
> + if (crtc_state->uapi.async_flip)
> + return false;
This looks dodgy. Pretty sure we can't turn off this thing during
an async flip. So I think the correct short term fix is to not do
async flips with psr2 enabled. The longer term fix would involve
using the same approach Stan is preparing for the async flip
watermark tweaking, which is to convert the first async flip into
a sync flip.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 13:32 ` Ville Syrjälä
@ 2021-10-28 17:02 ` Souza, Jose
2021-10-28 17:38 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2021-10-28 17:02 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > Async flips are not supported by selective fetch and we had a check
> > for that but that check was only executed when doing modesets.
> > So moving this check to the page flip path, so it can be properly
> > handled.
> >
> > This fix a failure in kms_async_flips@test-cursor.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > return false;
> > }
> >
> > - if (crtc_state->uapi.async_flip) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > - return false;
> > - }
> > -
> > /* Wa_14010254185 Wa_14010103792 */
> > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > drm_dbg_kms(&dev_priv->drm,
> > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > {
> > if (crtc_state->scaler_state.scaler_id >= 0)
> > return false;
> > + if (crtc_state->uapi.async_flip)
> > + return false;
>
> This looks dodgy. Pretty sure we can't turn off this thing during
> an async flip. So I think the correct short term fix is to not do
> async flips with psr2 enabled. The longer term fix would involve
> using the same approach Stan is preparing for the async flip
> watermark tweaking, which is to convert the first async flip into
> a sync flip.
>
It is not turning PSR2 off, it is telling hardware to fetch the whole memory of all planes and send the whole screen to panel instead of fetching and
sending a smaller area for this frame, we also do that when a plane is moved to a negative coordinate.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 17:02 ` Souza, Jose
@ 2021-10-28 17:38 ` Ville Syrjälä
2021-10-28 17:43 ` Souza, Jose
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2021-10-28 17:38 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > Async flips are not supported by selective fetch and we had a check
> > > for that but that check was only executed when doing modesets.
> > > So moving this check to the page flip path, so it can be properly
> > > handled.
> > >
> > > This fix a failure in kms_async_flips@test-cursor.
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > return false;
> > > }
> > >
> > > - if (crtc_state->uapi.async_flip) {
> > > - drm_dbg_kms(&dev_priv->drm,
> > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > - return false;
> > > - }
> > > -
> > > /* Wa_14010254185 Wa_14010103792 */
> > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > drm_dbg_kms(&dev_priv->drm,
> > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > {
> > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > return false;
> > > + if (crtc_state->uapi.async_flip)
> > > + return false;
> >
> > This looks dodgy. Pretty sure we can't turn off this thing during
> > an async flip. So I think the correct short term fix is to not do
> > async flips with psr2 enabled. The longer term fix would involve
> > using the same approach Stan is preparing for the async flip
> > watermark tweaking, which is to convert the first async flip into
> > a sync flip.
> >
>
> It is not turning PSR2 off, it is telling hardware to fetch the whole memory of all planes and send the whole screen to panel instead of fetching and
> sending a smaller area for this frame, we also do that when a plane is moved to a negative coordinate.
Doesn't matter. Whatever register is rsponsible for this is presumably latched
at the next vblank which is after the async flip already happened.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 17:38 ` Ville Syrjälä
@ 2021-10-28 17:43 ` Souza, Jose
2021-10-28 17:46 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2021-10-28 17:43 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > Async flips are not supported by selective fetch and we had a check
> > > > for that but that check was only executed when doing modesets.
> > > > So moving this check to the page flip path, so it can be properly
> > > > handled.
> > > >
> > > > This fix a failure in kms_async_flips@test-cursor.
> > > >
> > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > return false;
> > > > }
> > > >
> > > > - if (crtc_state->uapi.async_flip) {
> > > > - drm_dbg_kms(&dev_priv->drm,
> > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > - return false;
> > > > - }
> > > > -
> > > > /* Wa_14010254185 Wa_14010103792 */
> > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > drm_dbg_kms(&dev_priv->drm,
> > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > {
> > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > return false;
> > > > + if (crtc_state->uapi.async_flip)
> > > > + return false;
> > >
> > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > an async flip. So I think the correct short term fix is to not do
> > > async flips with psr2 enabled. The longer term fix would involve
> > > using the same approach Stan is preparing for the async flip
> > > watermark tweaking, which is to convert the first async flip into
> > > a sync flip.
> > >
> >
> > It is not turning PSR2 off, it is telling hardware to fetch the whole memory of all planes and send the whole screen to panel instead of fetching and
> > sending a smaller area for this frame, we also do that when a plane is moved to a negative coordinate.
>
> Doesn't matter. Whatever register is rsponsible for this is presumably latched
> at the next vblank which is after the async flip already happened.
>
That is exactly what BSpec 55229 asks us to do:
Not supported with async flips. The plane size and position cannot be changed with async flips, so selective fetch cannot be used. Software must
output a full frame for async flips.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 17:43 ` Souza, Jose
@ 2021-10-28 17:46 ` Ville Syrjälä
2021-10-28 20:18 ` Souza, Jose
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2021-10-28 17:46 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, Oct 28, 2021 at 05:43:51PM +0000, Souza, Jose wrote:
> On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > > Async flips are not supported by selective fetch and we had a check
> > > > > for that but that check was only executed when doing modesets.
> > > > > So moving this check to the page flip path, so it can be properly
> > > > > handled.
> > > > >
> > > > > This fix a failure in kms_async_flips@test-cursor.
> > > > >
> > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > return false;
> > > > > }
> > > > >
> > > > > - if (crtc_state->uapi.async_flip) {
> > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > > - return false;
> > > > > - }
> > > > > -
> > > > > /* Wa_14010254185 Wa_14010103792 */
> > > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > > {
> > > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > return false;
> > > > > + if (crtc_state->uapi.async_flip)
> > > > > + return false;
> > > >
> > > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > > an async flip. So I think the correct short term fix is to not do
> > > > async flips with psr2 enabled. The longer term fix would involve
> > > > using the same approach Stan is preparing for the async flip
> > > > watermark tweaking, which is to convert the first async flip into
> > > > a sync flip.
> > > >
> > >
> > > It is not turning PSR2 off, it is telling hardware to fetch the whole memory of all planes and send the whole screen to panel instead of fetching and
> > > sending a smaller area for this frame, we also do that when a plane is moved to a negative coordinate.
> >
> > Doesn't matter. Whatever register is rsponsible for this is presumably latched
> > at the next vblank which is after the async flip already happened.
> >
>
> That is exactly what BSpec 55229 asks us to do:
>
> Not supported with async flips. The plane size and position cannot be changed with async flips, so selective fetch cannot be used. Software must
> output a full frame for async flips.
It doesn't tell us to do it wrong.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 17:46 ` Ville Syrjälä
@ 2021-10-28 20:18 ` Souza, Jose
2021-10-29 6:22 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2021-10-28 20:18 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 05:43:51PM +0000, Souza, Jose wrote:
> > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > > > Async flips are not supported by selective fetch and we had a check
> > > > > > for that but that check was only executed when doing modesets.
> > > > > > So moving this check to the page flip path, so it can be properly
> > > > > > handled.
> > > > > >
> > > > > > This fix a failure in kms_async_flips@test-cursor.
> > > > > >
> > > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > > return false;
> > > > > > }
> > > > > >
> > > > > > - if (crtc_state->uapi.async_flip) {
> > > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > > > - return false;
> > > > > > - }
> > > > > > -
> > > > > > /* Wa_14010254185 Wa_14010103792 */
> > > > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > > > {
> > > > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > return false;
> > > > > > + if (crtc_state->uapi.async_flip)
> > > > > > + return false;
> > > > >
> > > > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > > > an async flip. So I think the correct short term fix is to not do
> > > > > async flips with psr2 enabled. The longer term fix would involve
> > > > > using the same approach Stan is preparing for the async flip
> > > > > watermark tweaking, which is to convert the first async flip into
> > > > > a sync flip.
You mean do something like this?
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3b5a8e971343f..7d29f8c9de0da 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7710,7 +7710,8 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
static int intel_atomic_check_async(struct intel_atomic_state *state, struct intel_crtc *crtc)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
- const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ const struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
const struct intel_plane_state *new_plane_state, *old_plane_state;
struct intel_plane *plane;
int i;
@@ -7718,6 +7719,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ if (new_crtc_state->enable_psr2_sel_fetch) {
+ drm_dbg_kms(&i915->drm, "PSR2 selective fetch not compatible with async flip, doing a sync flip instead\n");
+ new_crtc_state->uapi.async_flip = false;
+ return 0;
+ }
+
if (intel_crtc_needs_modeset(new_crtc_state)) {
drm_dbg_kms(&i915->drm, "Modeset Required. Async flip not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ce6850ed72c60..00e69421b9648 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1586,8 +1586,6 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
{
if (crtc_state->scaler_state.scaler_id >= 0)
return false;
- if (crtc_state->uapi.async_flip)
- return false;
return true;
}
This is causing other kms_async_flips tests to fail, the ones that checks the async flip time interval.
> > > > >
> > > >
> > > > It is not turning PSR2 off, it is telling hardware to fetch the whole memory of all planes and send the whole screen to panel instead of fetching and
> > > > sending a smaller area for this frame, we also do that when a plane is moved to a negative coordinate.
> > >
> > > Doesn't matter. Whatever register is rsponsible for this is presumably latched
> > > at the next vblank which is after the async flip already happened.
> > >
> >
> > That is exactly what BSpec 55229 asks us to do:
> >
> > Not supported with async flips. The plane size and position cannot be changed with async flips, so selective fetch cannot be used. Software must
> > output a full frame for async flips.
>
> It doesn't tell us to do it wrong.
>
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/psr2: Do full fetches when doing async flips (rev3)
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
` (3 preceding siblings ...)
2021-10-28 13:32 ` Ville Syrjälä
@ 2021-10-28 21:40 ` Patchwork
4 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2021-10-28 21:40 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr2: Do full fetches when doing async flips (rev3)
URL : https://patchwork.freedesktop.org/series/96357/
State : failure
== Summary ==
Applying: drm/i915/psr2: Do full fetches when doing async flips
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/psr2: Do full fetches when doing async flips
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-28 20:18 ` Souza, Jose
@ 2021-10-29 6:22 ` Ville Syrjälä
2021-10-29 22:55 ` Souza, Jose
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2021-10-29 6:22 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Thu, Oct 28, 2021 at 08:18:48PM +0000, Souza, Jose wrote:
> On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 28, 2021 at 05:43:51PM +0000, Souza, Jose wrote:
> > > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > > > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > > > > Async flips are not supported by selective fetch and we had a check
> > > > > > > for that but that check was only executed when doing modesets.
> > > > > > > So moving this check to the page flip path, so it can be properly
> > > > > > > handled.
> > > > > > >
> > > > > > > This fix a failure in kms_async_flips@test-cursor.
> > > > > > >
> > > > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > > > return false;
> > > > > > > }
> > > > > > >
> > > > > > > - if (crtc_state->uapi.async_flip) {
> > > > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > > > > - return false;
> > > > > > > - }
> > > > > > > -
> > > > > > > /* Wa_14010254185 Wa_14010103792 */
> > > > > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > > > > {
> > > > > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > > return false;
> > > > > > > + if (crtc_state->uapi.async_flip)
> > > > > > > + return false;
> > > > > >
> > > > > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > > > > an async flip. So I think the correct short term fix is to not do
> > > > > > async flips with psr2 enabled. The longer term fix would involve
> > > > > > using the same approach Stan is preparing for the async flip
> > > > > > watermark tweaking, which is to convert the first async flip into
> > > > > > a sync flip.
>
> You mean do something like this?
>
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3b5a8e971343f..7d29f8c9de0da 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7710,7 +7710,8 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
> static int intel_atomic_check_async(struct intel_atomic_state *state, struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> - const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> + const struct intel_crtc_state *old_crtc_state;
> + struct intel_crtc_state *new_crtc_state;
> const struct intel_plane_state *new_plane_state, *old_plane_state;
> struct intel_plane *plane;
> int i;
> @@ -7718,6 +7719,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>
> + if (new_crtc_state->enable_psr2_sel_fetch) {
> + drm_dbg_kms(&i915->drm, "PSR2 selective fetch not compatible with async flip, doing a sync flip instead\n");
> + new_crtc_state->uapi.async_flip = false;
> + return 0;
> + }
It should just return -EINVAL here. And I'd put the somewhere after the
needs_modeset/hw.active checks to keep things in some kind of
reasonable order.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-29 6:22 ` Ville Syrjälä
@ 2021-10-29 22:55 ` Souza, Jose
2021-10-30 0:15 ` Souza, Jose
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2021-10-29 22:55 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Fri, 2021-10-29 at 09:22 +0300, Ville Syrjälä wrote:
> On Thu, Oct 28, 2021 at 08:18:48PM +0000, Souza, Jose wrote:
> > On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 28, 2021 at 05:43:51PM +0000, Souza, Jose wrote:
> > > > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > > > On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > > > > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > > > > > Async flips are not supported by selective fetch and we had a check
> > > > > > > > for that but that check was only executed when doing modesets.
> > > > > > > > So moving this check to the page flip path, so it can be properly
> > > > > > > > handled.
> > > > > > > >
> > > > > > > > This fix a failure in kms_async_flips@test-cursor.
> > > > > > > >
> > > > > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > > > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > > > > return false;
> > > > > > > > }
> > > > > > > >
> > > > > > > > - if (crtc_state->uapi.async_flip) {
> > > > > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > > > > > - return false;
> > > > > > > > - }
> > > > > > > > -
> > > > > > > > /* Wa_14010254185 Wa_14010103792 */
> > > > > > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > > > > > {
> > > > > > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > > > return false;
> > > > > > > > + if (crtc_state->uapi.async_flip)
> > > > > > > > + return false;
> > > > > > >
> > > > > > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > > > > > an async flip. So I think the correct short term fix is to not do
> > > > > > > async flips with psr2 enabled. The longer term fix would involve
> > > > > > > using the same approach Stan is preparing for the async flip
> > > > > > > watermark tweaking, which is to convert the first async flip into
> > > > > > > a sync flip.
> >
> > You mean do something like this?
> >
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 3b5a8e971343f..7d29f8c9de0da 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -7710,7 +7710,8 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
> > static int intel_atomic_check_async(struct intel_atomic_state *state, struct intel_crtc *crtc)
> > {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > - const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > + const struct intel_crtc_state *old_crtc_state;
> > + struct intel_crtc_state *new_crtc_state;
> > const struct intel_plane_state *new_plane_state, *old_plane_state;
> > struct intel_plane *plane;
> > int i;
> > @@ -7718,6 +7719,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> > old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> > new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> >
> > + if (new_crtc_state->enable_psr2_sel_fetch) {
> > + drm_dbg_kms(&i915->drm, "PSR2 selective fetch not compatible with async flip, doing a sync flip instead\n");
> > + new_crtc_state->uapi.async_flip = false;
> > + return 0;
> > + }
>
> It should just return -EINVAL here. And I'd put the somewhere after the
> needs_modeset/hw.active checks to keep things in some kind of
> reasonable order.
Okay, easy do that but that would not cause any issues for desktop environments?
We advertise async flip capability but state will always be rejected when PSR2 is enabled.
Will also need to switch to PSR1 or skip all kms_async_flip tests when PSR2 selective fetch is enabled.
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips
2021-10-29 22:55 ` Souza, Jose
@ 2021-10-30 0:15 ` Souza, Jose
0 siblings, 0 replies; 14+ messages in thread
From: Souza, Jose @ 2021-10-30 0:15 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, Kahola, Mika, Hogander, Jouni
On Fri, 2021-10-29 at 22:55 +0000, Souza, Jose wrote:
> On Fri, 2021-10-29 at 09:22 +0300, Ville Syrjälä wrote:
> > On Thu, Oct 28, 2021 at 08:18:48PM +0000, Souza, Jose wrote:
> > > On Thu, 2021-10-28 at 20:46 +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 28, 2021 at 05:43:51PM +0000, Souza, Jose wrote:
> > > > > On Thu, 2021-10-28 at 20:38 +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Oct 28, 2021 at 05:02:41PM +0000, Souza, Jose wrote:
> > > > > > > On Thu, 2021-10-28 at 16:32 +0300, Ville Syrjälä wrote:
> > > > > > > > On Wed, Oct 27, 2021 at 11:48:55AM -0700, José Roberto de Souza wrote:
> > > > > > > > > Async flips are not supported by selective fetch and we had a check
> > > > > > > > > for that but that check was only executed when doing modesets.
> > > > > > > > > So moving this check to the page flip path, so it can be properly
> > > > > > > > > handled.
> > > > > > > > >
> > > > > > > > > This fix a failure in kms_async_flips@test-cursor.
> > > > > > > > >
> > > > > > > > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > > > > > > > Cc: Jouni Hogander <jouni.hogander@intel.com>
> > > > > > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > > > > > > ---
> > > > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 8 ++------
> > > > > > > > > 1 file changed, 2 insertions(+), 6 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > > index 8d08e3cf08c1f..ce6850ed72c60 100644
> > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > > > @@ -729,12 +729,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > > > > > return false;
> > > > > > > > > }
> > > > > > > > >
> > > > > > > > > - if (crtc_state->uapi.async_flip) {
> > > > > > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > > > > > - "PSR2 sel fetch not enabled, async flip enabled\n");
> > > > > > > > > - return false;
> > > > > > > > > - }
> > > > > > > > > -
> > > > > > > > > /* Wa_14010254185 Wa_14010103792 */
> > > > > > > > > if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > > > > > drm_dbg_kms(&dev_priv->drm,
> > > > > > > > > @@ -1592,6 +1586,8 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c
> > > > > > > > > {
> > > > > > > > > if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > > > > return false;
> > > > > > > > > + if (crtc_state->uapi.async_flip)
> > > > > > > > > + return false;
> > > > > > > >
> > > > > > > > This looks dodgy. Pretty sure we can't turn off this thing during
> > > > > > > > an async flip. So I think the correct short term fix is to not do
> > > > > > > > async flips with psr2 enabled. The longer term fix would involve
> > > > > > > > using the same approach Stan is preparing for the async flip
> > > > > > > > watermark tweaking, which is to convert the first async flip into
> > > > > > > > a sync flip.
> > >
> > > You mean do something like this?
> > >
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 3b5a8e971343f..7d29f8c9de0da 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -7710,7 +7710,8 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state,
> > > static int intel_atomic_check_async(struct intel_atomic_state *state, struct intel_crtc *crtc)
> > > {
> > > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > > - const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > > + const struct intel_crtc_state *old_crtc_state;
> > > + struct intel_crtc_state *new_crtc_state;
> > > const struct intel_plane_state *new_plane_state, *old_plane_state;
> > > struct intel_plane *plane;
> > > int i;
> > > @@ -7718,6 +7719,12 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
> > > old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> > > new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > >
> > > + if (new_crtc_state->enable_psr2_sel_fetch) {
> > > + drm_dbg_kms(&i915->drm, "PSR2 selective fetch not compatible with async flip, doing a sync flip instead\n");
> > > + new_crtc_state->uapi.async_flip = false;
> > > + return 0;
> > > + }
> >
> > It should just return -EINVAL here. And I'd put the somewhere after the
> > needs_modeset/hw.active checks to keep things in some kind of
> > reasonable order.
>
> Okay, easy do that but that would not cause any issues for desktop environments?
> We advertise async flip capability but state will always be rejected when PSR2 is enabled.
>
> Will also need to switch to PSR1 or skip all kms_async_flip tests when PSR2 selective fetch is enabled.
Please disregard the above comment and this whole patch.
Did more debug and found better ways to solve all async flip + PSR problems.
IGT patches will change the failure to skip as we don't have a way around it: https://patchwork.freedesktop.org/series/96439/
Kernel patch fixing possible corruptions with async flip: https://patchwork.freedesktop.org/series/96440/
>
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-10-30 0:15 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-27 18:48 [Intel-gfx] [PATCH] drm/i915/psr2: Do full fetches when doing async flips José Roberto de Souza
2021-10-27 21:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-28 4:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-28 5:59 ` [Intel-gfx] [PATCH] " Karthik B S
2021-10-28 13:32 ` Ville Syrjälä
2021-10-28 17:02 ` Souza, Jose
2021-10-28 17:38 ` Ville Syrjälä
2021-10-28 17:43 ` Souza, Jose
2021-10-28 17:46 ` Ville Syrjälä
2021-10-28 20:18 ` Souza, Jose
2021-10-29 6:22 ` Ville Syrjälä
2021-10-29 22:55 ` Souza, Jose
2021-10-30 0:15 ` Souza, Jose
2021-10-28 21:40 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/psr2: Do full fetches when doing async flips (rev3) Patchwork
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all data and code used by this external index.