* [PATCH v2 00/30] Add Loongarch softmmu support.
@ 2021-11-09 12:51 Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 01/30] target/loongarch: Update README Xiaojuan Yang
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
This series patch add softmmu support for LoongArch.
Base on the linux-user emulation support V9 patch.
* https://patchew.org/QEMU/1630586467-22463-1-git-send-email-gaosong@loongson.cn/diff/1636340895-5255-1-git-send-email-gaosong@loongson.cn/
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The manual:
* https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
Changes for v2:
1.Combine patch 2 and 3 into one.
2.Adjust the order of the patch.
3.Modify some emulate errors when use the kernel from the github.
4.Adjust some format problem.
5.Others mainly follow Richard's code review comments.
Please review!
Thanks
Xiaojuan Yang (30):
target/loongarch: Update README
target/loongarch: Add CSR registers definition
target/loongarch: Add basic vmstate description of CPU.
target/loongarch: Define exceptions for LoongArch.
target/loongarch: Implement qmp_query_cpu_definitions()
target/loongarch: Add stabletimer support
target/loongarch: Add MMU support for LoongArch CPU.
target/loongarch: Add LoongArch CSR/IOCSR instruction
target/loongarch: Add TLB instruction support
target/loongarch: Add other core instructions support
target/loongarch: Add LoongArch interrupt and exception handle
target/loongarch: Add timer related instructions support.
target/loongarch: Add gdb support.
target/loongarch: Implement privilege instructions disassembly
hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson
Platform
hw/loongarch: Add a virt LoongArch 3A5000 board support
hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC)
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
hw/loongarch: Add irq hierarchy for the system
hw/loongarch: Add some devices support for 3A5000.
hw/loongarch: Add LoongArch ls7a rtc device support
hw/loongarch: Add default bios startup support.
hw/loongarch: Add -kernel and -initrd options support
hw/loongarch: Add LoongArch smbios support
hw/loongarch: Add LoongArch acpi support
hw/loongarch: Add machine->possible_cpus
hw/loongarch: Add Numa support.
.../devices/loongarch64-softmmu/default.mak | 3 +
configs/targets/loongarch64-softmmu.mak | 4 +
gdb-xml/loongarch-base64.xml | 43 +
gdb-xml/loongarch-fpu64.xml | 57 ++
hw/Kconfig | 1 +
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 349 +++++++
hw/acpi/meson.build | 1 +
hw/intc/Kconfig | 12 +
hw/intc/loongarch_extioi.c | 588 ++++++++++++
hw/intc/loongarch_pch_msi.c | 73 ++
hw/intc/loongarch_pch_pic.c | 283 ++++++
hw/intc/meson.build | 3 +
hw/loongarch/Kconfig | 22 +
hw/loongarch/acpi-build.c | 653 +++++++++++++
hw/loongarch/fw_cfg.c | 33 +
hw/loongarch/fw_cfg.h | 15 +
hw/loongarch/ipi.c | 146 +++
hw/loongarch/loongarch_int.c | 59 ++
hw/loongarch/ls3a5000_virt.c | 647 +++++++++++++
hw/loongarch/meson.build | 7 +
hw/meson.build | 1 +
hw/pci-host/Kconfig | 4 +
hw/pci-host/ls7a.c | 223 +++++
hw/pci-host/meson.build | 1 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 323 +++++++
hw/rtc/meson.build | 1 +
include/exec/poison.h | 2 +
include/hw/acpi/ls7a.h | 53 ++
include/hw/intc/loongarch_extioi.h | 101 ++
include/hw/intc/loongarch_pch_msi.h | 16 +
include/hw/intc/loongarch_pch_pic.h | 49 +
include/hw/loongarch/gipi.h | 37 +
include/hw/loongarch/loongarch.h | 78 ++
include/hw/pci-host/ls7a.h | 66 ++
include/sysemu/arch_init.h | 1 +
pc-bios/loongarch_bios.bin | Bin 0 -> 4128768 bytes
qapi/machine-target.json | 6 +-
qapi/machine.json | 2 +-
softmmu/qdev-monitor.c | 3 +-
target/Kconfig | 1 +
target/loongarch/Kconfig | 2 +
target/loongarch/README | 20 +
target/loongarch/cpu-csr.h | 334 +++++++
target/loongarch/cpu-param.h | 3 +
target/loongarch/cpu.c | 390 ++++++++
target/loongarch/cpu.h | 220 ++++-
target/loongarch/csr_helper.c | 331 +++++++
target/loongarch/disas.c | 86 ++
target/loongarch/gdbstub.c | 97 ++
target/loongarch/helper.h | 24 +
target/loongarch/insn_trans/trans_core.c.inc | 570 +++++++++++
target/loongarch/insn_trans/trans_extra.c.inc | 32 +
target/loongarch/insns.decode | 51 +
target/loongarch/internals.h | 26 +
target/loongarch/machine.c | 210 ++++
target/loongarch/meson.build | 10 +
target/loongarch/op_helper.c | 58 ++
target/loongarch/stabletimer.c | 70 ++
target/loongarch/tlb_helper.c | 901 ++++++++++++++++++
target/loongarch/translate.c | 7 +
62 files changed, 7410 insertions(+), 6 deletions(-)
create mode 100644 configs/devices/loongarch64-softmmu/default.mak
create mode 100644 configs/targets/loongarch64-softmmu.mak
create mode 100644 gdb-xml/loongarch-base64.xml
create mode 100644 gdb-xml/loongarch-fpu64.xml
create mode 100644 hw/acpi/ls7a.c
create mode 100644 hw/intc/loongarch_extioi.c
create mode 100644 hw/intc/loongarch_pch_msi.c
create mode 100644 hw/intc/loongarch_pch_pic.c
create mode 100644 hw/loongarch/Kconfig
create mode 100644 hw/loongarch/acpi-build.c
create mode 100644 hw/loongarch/fw_cfg.c
create mode 100644 hw/loongarch/fw_cfg.h
create mode 100644 hw/loongarch/ipi.c
create mode 100644 hw/loongarch/loongarch_int.c
create mode 100644 hw/loongarch/ls3a5000_virt.c
create mode 100644 hw/loongarch/meson.build
create mode 100644 hw/pci-host/ls7a.c
create mode 100644 hw/rtc/ls7a_rtc.c
create mode 100644 include/hw/acpi/ls7a.h
create mode 100644 include/hw/intc/loongarch_extioi.h
create mode 100644 include/hw/intc/loongarch_pch_msi.h
create mode 100644 include/hw/intc/loongarch_pch_pic.h
create mode 100644 include/hw/loongarch/gipi.h
create mode 100644 include/hw/loongarch/loongarch.h
create mode 100644 include/hw/pci-host/ls7a.h
create mode 100644 pc-bios/loongarch_bios.bin
create mode 100644 target/loongarch/Kconfig
create mode 100644 target/loongarch/cpu-csr.h
create mode 100644 target/loongarch/csr_helper.c
create mode 100644 target/loongarch/gdbstub.c
create mode 100644 target/loongarch/insn_trans/trans_core.c.inc
create mode 100644 target/loongarch/machine.c
create mode 100644 target/loongarch/stabletimer.c
create mode 100644 target/loongarch/tlb_helper.c
--
2.27.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 01/30] target/loongarch: Update README
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/README | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index 09f809cf80..b307bd4091 100644
--- a/target/loongarch/README
+++ b/target/loongarch/README
@@ -71,6 +71,26 @@
./qemu-loongarch64 /opt/clfs/usr/bin/pwd
...
+- Softmmu emulation
+
+ Add support softmmu emulation support in the following series patches.
+ Mainly emulate a virt 3A5000 board that is not exactly the same as the host.
+ Kernel code is on the github and the uefi code will be opened in the near future.
+ All required binaries can get from github for test.
+
+ 1.Download kernel and the cross-tools.(vmlinux)
+
+ wget https://github.com/loongson/linux
+ wget https://github.com/loongson/build-tools/releases/latest/download/loongarch64-clfs-20210831-cross-tools.tar.xz
+
+ 2.Download the clfs-system and made a ramdisk with busybox.(ramdisk)
+
+ 3.Run with command,eg:
+
+ ./build/qemu-system-loongarch64 -m 4G -smp 16 --cpu Loongson-3A5000 --machine loongson7a -kernel ./vmlinux -initrd ./ramdisk -append "root=/dev/ram console=ttyS0,115200 rdinit=/sbin/init loglevel=8" -monitor tcp::4000,server,nowait -nographic
+
+The vmlinux and ramdisk binary can get from :
+ git clone https://github.com/yangxiaojuan-loongson/qemu-binary
- Note.
We can get the latest LoongArch documents or LoongArch tools at https://github.com/loongson/
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 02/30] target/loongarch: Add CSR registers definition
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 01/30] target/loongarch: Update README Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu-csr.h | 334 +++++++++++++++++++++++++++++++++++++
target/loongarch/cpu.c | 12 ++
target/loongarch/cpu.h | 127 ++++++++++++++
3 files changed, 473 insertions(+)
create mode 100644 target/loongarch/cpu-csr.h
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
new file mode 100644
index 0000000000..ef7511bf51
--- /dev/null
+++ b/target/loongarch/cpu-csr.h
@@ -0,0 +1,334 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU CSR registers
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_CSR_H
+#define LOONGARCH_CPU_CSR_H
+
+/* Base on: kernal: arch/loongarch/include/asm/loongarch.h */
+
+/* Basic CSR register */
+#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
+FIELD(CSR_CRMD, PLV, 0, 2)
+FIELD(CSR_CRMD, IE, 2, 1)
+FIELD(CSR_CRMD, DA, 3, 1)
+FIELD(CSR_CRMD, PG, 4, 1)
+FIELD(CSR_CRMD, DATF, 5, 2)
+FIELD(CSR_CRMD, DATM, 7, 2)
+FIELD(CSR_CRMD, WE, 9, 1)
+
+#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
+FIELD(CSR_PRMD, PPLV, 0, 2)
+FIELD(CSR_PRMD, PIE, 2, 1)
+FIELD(CSR_PRMD, PWE, 3, 1)
+
+#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
+FIELD(CSR_EUEN, FPE, 0, 1)
+FIELD(CSR_EUEN, SXE, 1, 1)
+FIELD(CSR_EUEN, ASXE, 2, 1)
+FIELD(CSR_EUEN, BTE, 3, 1)
+
+#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
+
+#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
+FIELD(CSR_ECFG, LIE, 0, 13)
+FIELD(CSR_ECFG, VS, 16, 3)
+
+#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
+FIELD(CSR_ESTAT, IS, 0, 13)
+FIELD(CSR_ESTAT, ECODE, 16, 6)
+FIELD(CSR_ESTAT, ESUBCODE, 22, 9)
+
+#define EXCODE_IP 64
+#define EXCCODE_INT 0
+#define EXCCODE_PIL 1
+#define EXCCODE_PIS 2
+#define EXCCODE_PIF 3
+#define EXCCODE_PME 4
+#define EXCCODE_PNR 5
+#define EXCCODE_PNX 6
+#define EXCCODE_PPI 7
+#define EXCCODE_ADE 8
+#define EXCCODE_ALE 9
+#define EXCCODE_BCE 10
+#define EXCCODE_SYS 11
+#define EXCCODE_BRK 12
+#define EXCCODE_INE 13
+#define EXCCODE_IPE 14
+#define EXCCODE_FPD 15
+#define EXCCODE_SXD 16
+#define EXCCODE_ASXD 17
+#define EXCCODE_FPE 18 /* Have different expsubcode */
+#define EXCCODE_VFPE 18
+#define EXCCODE_WPEF 19 /* Have different expsubcode */
+#define EXCCODE_WPEM 19
+#define EXCCODE_BTD 20
+#define EXCCODE_BTE 21
+
+#define LOONGARCH_CSR_ERA 0x6 /* ERA */
+
+#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
+
+#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
+
+#define LOONGARCH_CSR_EENTRY 0xc /* Exception enter base address */
+
+/* TLB related CSR register */
+#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
+FIELD(CSR_TLBIDX, INDEX, 0, 12)
+FIELD(CSR_TLBIDX, PS, 24, 6)
+FIELD(CSR_TLBIDX, NE, 31, 1)
+
+#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi without ASID */
+FIELD(CSR_TLBEHI, VPPN, 13, 35)
+
+#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
+FIELD(CSR_TLBELO0, V, 0, 1)
+FIELD(CSR_TLBELO0, D, 1, 1)
+FIELD(CSR_TLBELO0, PLV, 2, 2)
+FIELD(CSR_TLBELO0, MAT, 4, 2)
+FIELD(CSR_TLBELO0, G, 6, 1)
+FIELD(CSR_TLBELO0, PPN, 12, 36)
+FIELD(CSR_TLBELO0, NR, 61, 1)
+FIELD(CSR_TLBELO0, NX, 62, 1)
+FIELD(CSR_TLBELO0, RPLV, 63, 1)
+
+#define LOONGARCH_CSR_TLBELO1 0x13 /* 64 TLB EntryLo1 */
+FIELD(CSR_TLBELO1, V, 0, 1)
+FIELD(CSR_TLBELO1, D, 1, 1)
+FIELD(CSR_TLBELO1, PLV, 2, 2)
+FIELD(CSR_TLBELO1, MAT, 4, 2)
+FIELD(CSR_TLBELO1, G, 6, 1)
+FIELD(CSR_TLBELO1, PPN, 12, 36)
+FIELD(CSR_TLBELO1, NR, 61, 1)
+FIELD(CSR_TLBELO1, NX, 62, 1)
+FIELD(CSR_TLBELO1, RPLV, 63, 1)
+
+#define LOONGARCH_CSR_ASID 0x18 /* ASID */
+FIELD(CSR_ASID, ASID, 0, 10)
+FIELD(CSR_ASID, ASIDBITS, 16, 8)
+
+/* Page table base address when badv[47] = 0 */
+#define LOONGARCH_CSR_PGDL 0x19
+/* Page table base address when badv[47] = 1 */
+#define LOONGARCH_CSR_PGDH 0x1a
+
+#define LOONGARCH_CSR_PGD 0x1b /* Page table base */
+
+#define LOONGARCH_CSR_PWCL 0x1c /* PWCl */
+FIELD(CSR_PWCL, PTBASE, 0, 5)
+FIELD(CSR_PWCL, PTWIDTH, 5, 5)
+FIELD(CSR_PWCL, DIR1_BASE, 10, 5)
+FIELD(CSR_PWCL, DIR1_WIDTH, 15, 5)
+FIELD(CSR_PWCL, DIR2_BASE, 20, 5)
+FIELD(CSR_PWCL, DIR2_WIDTH, 25, 5)
+FIELD(CSR_PWCL, PTEWIDTH, 30, 2)
+
+#define LOONGARCH_CSR_PWCH 0x1d /* PWCh */
+FIELD(CSR_PWCH, DIR3_BASE, 0, 6)
+FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6)
+FIELD(CSR_PWCH, DIR4_BASE, 12, 6)
+FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6)
+
+#define LOONGARCH_CSR_STLBPS 0x1e /* 64 */
+FIELD(CSR_STLBPS, PS, 0, 5)
+
+#define LOONGARCH_CSR_RVACFG 0x1f
+
+/* Config CSR registers */
+#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
+
+#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
+FIELD(CSR_PRCFG1, SAVE_NUM, 0, 4)
+FIELD(CSR_PRCFG1, TIMER_BITS, 4, 8)
+FIELD(CSR_PRCFG1, VSMAX, 12, 3)
+
+#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
+
+#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
+FIELD(CSR_PRCFG3, TLB_TYPE, 0, 4)
+FIELD(CSR_PRCFG3, MTLB_ENTRY, 4, 8)
+FIELD(CSR_PRCFG3, STLB_WAYS, 12, 8)
+FIELD(CSR_PRCFG3, STLB_SETS, 20, 8)
+
+/* Save registers */
+#define LOONGARCH_CSR_SAVE0 0x30
+#define LOONGARCH_CSR_SAVE1 0x31
+#define LOONGARCH_CSR_SAVE2 0x32
+#define LOONGARCH_CSR_SAVE3 0x33
+#define LOONGARCH_CSR_SAVE4 0x34
+#define LOONGARCH_CSR_SAVE5 0x35
+#define LOONGARCH_CSR_SAVE6 0x36
+#define LOONGARCH_CSR_SAVE7 0x37
+
+/* Timer registers */
+#define LOONGARCH_CSR_TMID 0x40 /* Timer ID */
+
+#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
+FIELD(CSR_TCFG, EN, 0, 1)
+FIELD(CSR_TCFG, PERIODIC, 1, 1)
+FIELD(CSR_TCFG, INIT_VAL, 2, 46)
+
+#define LOONGARCH_CSR_TVAL 0x42 /* Timer ticks remain */
+
+#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
+
+#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
+
+/* LLBCTL register */
+#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
+
+/* Implement dependent */
+#define LOONGARCH_CSR_IMPCTL1 0x80 /* LoongArch config1 */
+
+#define LOONGARCH_CSR_IMPCTL2 0x81 /* LoongArch config2*/
+
+/* TLB Refill registers */
+#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception address */
+#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
+#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
+#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KScratch for TLB refill */
+FIELD(CSR_TLBRERA, ISTLBR, 0, 1)
+FIELD(CSR_TLBRERA, PC, 2, 62)
+#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
+#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
+#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
+FIELD(CSR_TLBREHI, PS, 0, 6)
+FIELD(CSR_TLBREHI, VPPN, 13, 35)
+#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
+FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
+FIELD(CSR_TLBRPRMD, PIE, 2, 1)
+FIELD(CSR_TLBRPRMD, PWE, 4, 1)
+
+/* Machine Error registers */
+#define LOONGARCH_CSR_MERRCTL 0x90 /* ERRCTL */
+#define LOONGARCH_CSR_MERRINFO 0x91
+#define LOONGARCH_CSR_MERRINFO1 0x92
+#define LOONGARCH_CSR_MERRENT 0x93 /* MError exception base */
+#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception PC */
+#define LOONGARCH_CSR_MERRSAVE 0x95 /* KScratch for error exception */
+
+#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
+
+/* Direct map windows */
+#define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */
+#define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */
+#define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */
+#define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
+#define CSR_DMW_BASE_SH 48
+#define dmwin_va2pa(va) \
+ (va & (((unsigned long)1 << CSR_DMW_BASE_SH) - 1))
+
+/* Performance Counter registers */
+#define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
+#define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
+#define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */
+#define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */
+#define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */
+#define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */
+#define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */
+#define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */
+
+/* Debug registers */
+#define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */
+#define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */
+
+#define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */
+#define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */
+#define LOONGARCH_CSR_DB0CTL 0x312 /* data breakpoint 0 control */
+#define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */
+
+#define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */
+#define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */
+#define LOONGARCH_CSR_DB1CTL 0x31a /* data breakpoint 1 control */
+#define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */
+
+#define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */
+#define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */
+#define LOONGARCH_CSR_DB2CTL 0x322 /* data breakpoint 2 control */
+#define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */
+
+#define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */
+#define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */
+#define LOONGARCH_CSR_DB3CTL 0x32a /* data breakpoint 3 control */
+#define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */
+
+#define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */
+#define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */
+#define LOONGARCH_CSR_DB4CTL 0x332 /* data breakpoint 4 control */
+#define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */
+
+#define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */
+#define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */
+#define LOONGARCH_CSR_DB5CTL 0x33a /* data breakpoint 5 control */
+#define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */
+
+#define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */
+#define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */
+#define LOONGARCH_CSR_DB6CTL 0x342 /* data breakpoint 6 control */
+#define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */
+
+#define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */
+#define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */
+#define LOONGARCH_CSR_DB7CTL 0x34a /* data breakpoint 7 control */
+#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
+
+#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
+#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
+
+#define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */
+#define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */
+#define LOONGARCH_CSR_IB0CTL 0x392 /* inst breakpoint 0 control */
+#define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */
+
+#define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */
+#define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */
+#define LOONGARCH_CSR_IB1CTL 0x39a /* inst breakpoint 1 control */
+#define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */
+
+#define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */
+#define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */
+#define LOONGARCH_CSR_IB2CTL 0x3a2 /* inst breakpoint 2 control */
+#define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */
+
+#define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */
+#define LOONGARCH_CSR_IB3MASK 0x3a9 /* inst breakpoint 3 mask */
+#define LOONGARCH_CSR_IB3CTL 0x3aa /* inst breakpoint 3 control */
+#define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */
+
+#define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */
+#define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */
+#define LOONGARCH_CSR_IB4CTL 0x3b2 /* inst breakpoint 4 control */
+#define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */
+
+#define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */
+#define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */
+#define LOONGARCH_CSR_IB5CTL 0x3ba /* inst breakpoint 5 control */
+#define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */
+
+#define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */
+#define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */
+#define LOONGARCH_CSR_IB6CTL 0x3c2 /* inst breakpoint 6 control */
+#define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */
+
+#define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */
+#define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */
+#define LOONGARCH_CSR_IB7CTL 0x3ca /* inst breakpoint 7 control */
+#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
+
+#define LOONGARCH_CSR_DBG 0x500 /* debug config */
+FIELD(CSR_DBG, DST, 0, 1)
+FIELD(CSR_DBG, DREV, 1, 7)
+FIELD(CSR_DBG, DEI, 8, 1)
+FIELD(CSR_DBG, DCL, 9, 1)
+FIELD(CSR_DBG, DFW, 10, 1)
+FIELD(CSR_DBG, DMW, 11, 1)
+FIELD(CSR_DBG, ECODE, 16, 6)
+
+#define LOONGARCH_CSR_DERA 0x501 /* Debug era */
+#define LOONGARCH_CSR_DESAVE 0x502 /* Debug save */
+
+#endif /* LOONGARCH_CPU_CSR_H */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad11b98853..01a17d8221 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -156,6 +156,8 @@ static void loongarch_3a5000_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 0xf00f);
data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 0x60);
env->cpucfg[20] = data;
+
+ env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
}
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
@@ -179,12 +181,22 @@ static void loongarch_cpu_reset(DeviceState *dev)
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env;
+ uint64_t data;
lacc->parent_reset(dev);
env->fcsr0_mask = 0x1f1f031f;
env->fcsr0 = 0x0;
+ /* Set direct mapping mode after reset */
+ data = FIELD_DP64(0, CSR_CRMD, PLV, 0);
+ data = FIELD_DP64(data, CSR_CRMD, IE, 0);
+ data = FIELD_DP64(data, CSR_CRMD, DA, 1);
+ data = FIELD_DP64(data, CSR_CRMD, PG, 0);
+ data = FIELD_DP64(data, CSR_CRMD, DATF, 1);
+ data = FIELD_DP64(data, CSR_CRMD, DATM, 1);
+ env->CSR_CRMD = data;
+
restore_fp_status(env);
cs->exception_index = EXCP_NONE;
}
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 7509c77654..10fcd53104 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -11,6 +11,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
+#include "cpu-csr.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -170,6 +171,132 @@ struct CPULoongArchState {
uint64_t llval;
uint64_t badaddr;
+
+ /* LoongArch CSR registers */
+ uint64_t CSR_CRMD;
+ uint64_t CSR_PRMD;
+ uint64_t CSR_EUEN;
+ uint64_t CSR_MISC;
+ uint64_t CSR_ECFG;
+ uint64_t CSR_ESTAT;
+ uint64_t CSR_ERA;
+ uint64_t CSR_BADV;
+ uint64_t CSR_BADI;
+ uint64_t CSR_EENTRY;
+ uint64_t CSR_TLBIDX;
+ uint64_t CSR_TLBEHI;
+ uint64_t CSR_TLBELO0;
+ uint64_t CSR_TLBELO1;
+ uint64_t CSR_ASID;
+ uint64_t CSR_PGDL;
+ uint64_t CSR_PGDH;
+ uint64_t CSR_PGD;
+ uint64_t CSR_PWCL;
+ uint64_t CSR_PWCH;
+ uint64_t CSR_STLBPS;
+ uint64_t CSR_RVACFG;
+ uint64_t CSR_CPUID;
+ uint64_t CSR_PRCFG1;
+ uint64_t CSR_PRCFG2;
+ uint64_t CSR_PRCFG3;
+ uint64_t CSR_SAVE0;
+ uint64_t CSR_SAVE1;
+ uint64_t CSR_SAVE2;
+ uint64_t CSR_SAVE3;
+ uint64_t CSR_SAVE4;
+ uint64_t CSR_SAVE5;
+ uint64_t CSR_SAVE6;
+ uint64_t CSR_SAVE7;
+ uint64_t CSR_TMID;
+ uint64_t CSR_TCFG;
+ uint64_t CSR_TVAL;
+ uint64_t CSR_CNTC;
+ uint64_t CSR_TINTCLR;
+ uint64_t CSR_LLBCTL;
+ uint64_t CSR_IMPCTL1;
+ uint64_t CSR_IMPCTL2;
+ uint64_t CSR_TLBRENTRY;
+ uint64_t CSR_TLBRBADV;
+ uint64_t CSR_TLBRERA;
+ uint64_t CSR_TLBRSAVE;
+ uint64_t CSR_TLBRELO0;
+ uint64_t CSR_TLBRELO1;
+ uint64_t CSR_TLBREHI;
+ uint64_t CSR_TLBRPRMD;
+ uint64_t CSR_MERRCTL;
+ uint64_t CSR_MERRINFO;
+ uint64_t CSR_MERRINFO1;
+ uint64_t CSR_MERRENT;
+ uint64_t CSR_MERRERA;
+ uint64_t CSR_MERRSAVE;
+ uint64_t CSR_CTAG;
+ uint64_t CSR_DMWIN0;
+ uint64_t CSR_DMWIN1;
+ uint64_t CSR_DMWIN2;
+ uint64_t CSR_DMWIN3;
+ uint64_t CSR_PERFCTRL0;
+ uint64_t CSR_PERFCNTR0;
+ uint64_t CSR_PERFCTRL1;
+ uint64_t CSR_PERFCNTR1;
+ uint64_t CSR_PERFCTRL2;
+ uint64_t CSR_PERFCNTR2;
+ uint64_t CSR_PERFCTRL3;
+ uint64_t CSR_PERFCNTR3;
+ uint64_t CSR_MWPC;
+ uint64_t CSR_MWPS;
+ uint64_t CSR_DB0ADDR;
+ uint64_t CSR_DB0MASK;
+ uint64_t CSR_DB0CTL;
+ uint64_t CSR_DB0ASID;
+ uint64_t CSR_DB1ADDR;
+ uint64_t CSR_DB1MASK;
+ uint64_t CSR_DB1CTL;
+ uint64_t CSR_DB1ASID;
+ uint64_t CSR_DB2ADDR;
+ uint64_t CSR_DB2MASK;
+ uint64_t CSR_DB2CTL;
+ uint64_t CSR_DB2ASID;
+ uint64_t CSR_DB3ADDR;
+ uint64_t CSR_DB3MASK;
+ uint64_t CSR_DB3CTL;
+ uint64_t CSR_DB3ASID;
+ uint64_t CSR_FWPC;
+ uint64_t CSR_FWPS;
+ uint64_t CSR_IB0ADDR;
+ uint64_t CSR_IB0MASK;
+ uint64_t CSR_IB0CTL;
+ uint64_t CSR_IB0ASID;
+ uint64_t CSR_IB1ADDR;
+ uint64_t CSR_IB1MASK;
+ uint64_t CSR_IB1CTL;
+ uint64_t CSR_IB1ASID;
+ uint64_t CSR_IB2ADDR;
+ uint64_t CSR_IB2MASK;
+ uint64_t CSR_IB2CTL;
+ uint64_t CSR_IB2ASID;
+ uint64_t CSR_IB3ADDR;
+ uint64_t CSR_IB3MASK;
+ uint64_t CSR_IB3CTL;
+ uint64_t CSR_IB3ASID;
+ uint64_t CSR_IB4ADDR;
+ uint64_t CSR_IB4MASK;
+ uint64_t CSR_IB4CTL;
+ uint64_t CSR_IB4ASID;
+ uint64_t CSR_IB5ADDR;
+ uint64_t CSR_IB5MASK;
+ uint64_t CSR_IB5CTL;
+ uint64_t CSR_IB5ASID;
+ uint64_t CSR_IB6ADDR;
+ uint64_t CSR_IB6MASK;
+ uint64_t CSR_IB6CTL;
+ uint64_t CSR_IB6ASID;
+ uint64_t CSR_IB7ADDR;
+ uint64_t CSR_IB7MASK;
+ uint64_t CSR_IB7CTL;
+ uint64_t CSR_IB7ASID;
+ uint64_t CSR_DBG;
+ uint64_t CSR_DERA;
+ uint64_t CSR_DESAVE;
};
/**
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU.
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 01/30] target/loongarch: Update README Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch Xiaojuan Yang
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 4 +
target/loongarch/internals.h | 4 +
target/loongarch/machine.c | 154 +++++++++++++++++++++++++++++++++++
target/loongarch/meson.build | 6 ++
4 files changed, 168 insertions(+)
create mode 100644 target/loongarch/machine.c
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 01a17d8221..a53c8ebfb5 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -12,6 +12,7 @@
#include "sysemu/qtest.h"
#include "exec/exec-all.h"
#include "qapi/qapi-commands-machine-target.h"
+#include "migration/vmstate.h"
#include "cpu.h"
#include "internals.h"
#include "fpu/softfloat-helpers.h"
@@ -297,6 +298,9 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
cc->has_work = loongarch_cpu_has_work;
cc->dump_state = loongarch_cpu_dump_state;
cc->set_pc = loongarch_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ dc->vmsd = &vmstate_loongarch_cpu;
+#endif
cc->disas_set_info = loongarch_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops = &loongarch_tcg_ops;
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index e9e63742c4..49ed6829d7 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -25,4 +25,8 @@ const char *loongarch_exception_name(int32_t exception);
void restore_fp_status(CPULoongArchState *env);
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_loongarch_cpu;
+#endif
+
#endif
diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c
new file mode 100644
index 0000000000..b628374814
--- /dev/null
+++ b/target/loongarch/machine.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch machine State
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+/* LoongArch CPU state */
+
+const VMStateDescription vmstate_loongarch_cpu = {
+ .name = "cpu",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+
+ VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
+ VMSTATE_UINTTL(env.pc, LoongArchCPU),
+ VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+ VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
+
+ /* Remaining CSR registers */
+ VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CPUID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE3, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE4, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE5, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE6, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_SAVE7, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TMID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TINTCLR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRINFO, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRENT, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DMWIN0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DMWIN1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DMWIN2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DMWIN3, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCTRL0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCNTR0, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCTRL1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCNTR1, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCTRL2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCNTR2, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCTRL3, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_PERFCNTR3, LoongArchCPU),
+ /* debug */
+ VMSTATE_UINT64(env.CSR_MWPC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_MWPS, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB0ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB0MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB0CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB0ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB1ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB1MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB1CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB1ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB2ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB2MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB2CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB2ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB3ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB3MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB3CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DB3ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_FWPC, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_FWPS, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB0ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB0MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB0CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB0ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB1ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB1MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB1CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB1ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB2ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB2MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB2CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB2ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB3ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB3MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB3CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB3ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB4ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB4MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB4CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB4ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB5ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB5MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB5CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB5ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB6ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB6MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB6CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB6ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB7ADDR, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB7MASK, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB7CTL, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_IB7ASID, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
+ VMSTATE_UINT64(env.CSR_DESAVE, LoongArchCPU),
+
+ VMSTATE_END_OF_LIST()
+ },
+};
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index bcb076e55f..103f36ee15 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -14,6 +14,12 @@ loongarch_tcg_ss.add(files(
))
loongarch_tcg_ss.add(zlib)
+loongarch_softmmu_ss = ss.source_set()
+loongarch_softmmu_ss.add(files(
+ 'machine.c',
+))
+
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
target_arch += {'loongarch': loongarch_ss}
+target_softmmu_arch += {'loongarch': loongarch_softmmu_ss}
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch.
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
` (2 preceding siblings ...)
2021-11-09 12:51 ` [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
This patch introduces all possible exceptions.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.c | 13 +++++++++++++
target/loongarch/cpu.h | 17 +++++++++++++++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index a53c8ebfb5..16443159cc 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -37,6 +37,19 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_BREAK] = "Break",
[EXCP_INE] = "Instruction Non-existent",
[EXCP_FPE] = "Floating Point Exception",
+ [EXCP_IPE] = "Error privilege level access",
+ [EXCP_TLBL] = "TLB load",
+ [EXCP_TLBS] = "TLB store",
+ [EXCP_INST_NOTAVAIL] = "TLB inst not exist",
+ [EXCP_TLBM] = "TLB modify",
+ [EXCP_TLBPE] = "TLB priviledged error",
+ [EXCP_TLBNX] = "TLB execute-inhibit",
+ [EXCP_TLBNR] = "TLB read-inhibit",
+ [EXCP_EXT_INTERRUPT] = "Interrupt",
+ [EXCP_DBP] = "Debug breakpoint",
+ [EXCP_IBE] = "Instruction bus error",
+ [EXCP_DBE] = "Data bus error",
+ [EXCP_DINT] = "Debug interrupt",
};
const char *loongarch_exception_name(int32_t exception)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 10fcd53104..399c4cb5e8 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -369,8 +369,21 @@ enum {
EXCP_BREAK,
EXCP_INE,
EXCP_FPE,
-
- EXCP_LAST = EXCP_FPE,
+ EXCP_IPE,
+ EXCP_TLBL,
+ EXCP_TLBS,
+ EXCP_INST_NOTAVAIL,
+ EXCP_TLBM,
+ EXCP_TLBPE,
+ EXCP_TLBNX,
+ EXCP_TLBNR,
+ EXCP_EXT_INTERRUPT,
+ EXCP_DBP,
+ EXCP_IBE,
+ EXCP_DBE,
+ EXCP_DINT,
+
+ EXCP_LAST = EXCP_DINT,
};
#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions()
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
` (3 preceding siblings ...)
2021-11-09 12:51 ` [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
This patch introduces qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
qapi/machine-target.json | 6 ++++--
target/loongarch/cpu.c | 28 ++++++++++++++++++++++++++++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index f5ec4bc172..682dc86b42 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -324,7 +324,8 @@
'TARGET_ARM',
'TARGET_I386',
'TARGET_S390X',
- 'TARGET_MIPS' ] } }
+ 'TARGET_MIPS',
+ 'TARGET_LOONGARCH64' ] } }
##
# @query-cpu-definitions:
@@ -340,4 +341,5 @@
'TARGET_ARM',
'TARGET_I386',
'TARGET_S390X',
- 'TARGET_MIPS' ] } }
+ 'TARGET_MIPS',
+ 'TARGET_LOONGARCH64' ] } }
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 16443159cc..c3e7c5dc98 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -342,3 +342,31 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
};
DEFINE_TYPES(loongarch_cpu_type_infos)
+
+static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CpuDefinitionInfoList **cpu_list = user_data;
+ CpuDefinitionInfo *info;
+ const char *typename;
+
+ typename = object_class_get_name(oc);
+ info = g_malloc0(sizeof(*info));
+ info->name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
+ info->q_typename = g_strdup(typename);
+
+ QAPI_LIST_PREPEND(*cpu_list, info);
+}
+
+CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
+{
+ CpuDefinitionInfoList *cpu_list = NULL;
+ GSList *list;
+
+ list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
+ g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
+ g_slist_free(list);
+
+ return cpu_list;
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 12/30] target/loongarch: Add timer related instructions support.
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
` (4 preceding siblings ...)
2021-11-09 12:51 ` [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
@ 2021-11-09 12:51 ` Xiaojuan Yang
5 siblings, 0 replies; 7+ messages in thread
From: Xiaojuan Yang @ 2021-11-09 12:51 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, thuth, philmd, i.qemu, richard.henderson, laurent,
peterx, f4bug, yangxiaojuan, alistair.francis, maobibo, gaosong,
pbonzini, mark.cave-ayland, chenhuacai, alex.bennee, david
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/helper.h | 1 +
| 32 +++++++++++++++++++
target/loongarch/op_helper.c | 4 +++
target/loongarch/translate.c | 2 ++
4 files changed, 39 insertions(+)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index afb362c9c7..fc4eaa1ce8 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -114,4 +114,5 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
DEF_HELPER_1(ertn, void, env)
DEF_HELPER_1(idle, void, env)
+DEF_HELPER_1(rdtime_d, i64, env)
#endif /* !CONFIG_USER_ONLY */
--git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
index 76f0698da7..ab46331547 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -33,22 +33,54 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
return true;
}
+#ifndef CONFIG_USER_ONLY
+static bool gen_rdtime(DisasContext *ctx, arg_rdtimel_w *a,
+ bool word, bool high)
+{
+ TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_rdtime_d(dst1, cpu_env);
+ if (word) {
+ tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
+ }
+ tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TMID));
+
+ return true;
+}
+#endif
+
static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 0);
+#endif
}
static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 1, 1);
+#endif
}
static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
{
+#ifdef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
return true;
+#else
+ return gen_rdtime(ctx, a, 0, 0);
+#endif
}
static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index e2a9fd9ad0..fb47914c87 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -134,5 +134,9 @@ void helper_idle(CPULoongArchState *env)
do_raise_exception(env, EXCP_HLT, 0);
}
+uint64_t helper_rdtime_d(CPULoongArchState *env)
+{
+ return cpu_loongarch_get_stable_counter(env);
+}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3935b14163..15276a240f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval;
TCGv_i32 cpu_fcsr0;
TCGv_i64 cpu_fpr[32];
+#include "exec/gen-icount.h"
+
#define DISAS_STOP DISAS_TARGET_0
#define DISAS_EXIT DISAS_TARGET_1
--
2.27.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-11-09 12:56 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-09 12:51 [PATCH v2 00/30] Add Loongarch softmmu support Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 01/30] target/loongarch: Update README Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 02/30] target/loongarch: Add CSR registers definition Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 03/30] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 04/30] target/loongarch: Define exceptions for LoongArch Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 05/30] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-11-09 12:51 ` [PATCH v2 12/30] target/loongarch: Add timer related instructions support Xiaojuan Yang
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