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From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com,
	tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org,
	robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v6 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties
Date: Tue, 16 Nov 2021 10:16:11 +0800	[thread overview]
Message-ID: <1637028976-9201-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1637028976-9201-1-git-send-email-hongxing.zhu@nxp.com>

i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index acea1cd444fd..643a6333b07b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -127,6 +127,12 @@ properties:
     enum: [1, 2, 3, 4]
     default: 1
 
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: pcie-phy
+
   reset-gpio:
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com,
	tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org,
	robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v6 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties
Date: Tue, 16 Nov 2021 10:16:11 +0800	[thread overview]
Message-ID: <1637028976-9201-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1637028976-9201-1-git-send-email-hongxing.zhu@nxp.com>

i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index acea1cd444fd..643a6333b07b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -127,6 +127,12 @@ properties:
     enum: [1, 2, 3, 4]
     default: 1
 
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: pcie-phy
+
   reset-gpio:
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Richard Zhu <hongxing.zhu@nxp.com>
To: l.stach@pengutronix.de, marcel.ziswiler@toradex.com,
	tharvey@gateworks.com, kishon@ti.com, vkoul@kernel.org,
	robh@kernel.org, galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com, Richard Zhu <hongxing.zhu@nxp.com>
Subject: [PATCH v6 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties
Date: Tue, 16 Nov 2021 10:16:11 +0800	[thread overview]
Message-ID: <1637028976-9201-4-git-send-email-hongxing.zhu@nxp.com> (raw)
In-Reply-To: <1637028976-9201-1-git-send-email-hongxing.zhu@nxp.com>

i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index acea1cd444fd..643a6333b07b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -127,6 +127,12 @@ properties:
     enum: [1, 2, 3, 4]
     default: 1
 
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: pcie-phy
+
   reset-gpio:
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-11-16  2:43 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-16  2:16 [PATCH v6 0/8] Add the imx8m pcie phy driver and imx8mm pcie support Richard Zhu
2021-11-16  2:16 ` Richard Zhu
2021-11-16  2:16 ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 1/8] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 2/8] dt-bindings: phy: Add imx8 pcie phy driver support Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` Richard Zhu [this message]
2021-11-16  2:16   ` [PATCH v6 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 4/8] arm64: dts: imx8mm: Add the pcie phy support Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 5/8] phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 6/8] arm64: dts: imx8mm: Add the pcie support Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 7/8] arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16 ` [PATCH v6 8/8] PCI: imx: Add the imx8mm pcie support Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-16  2:16   ` Richard Zhu
2021-11-18  1:54 [PATCH v6 0/8] Add the imx8m pcie phy driver and " Richard Zhu
2021-11-18  1:54 ` [PATCH v6 3/8] dt-bindings: imx6q-pcie: Add PHY phandles and name properties Richard Zhu
2021-11-18  1:54   ` Richard Zhu
2021-11-18  1:54   ` Richard Zhu

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