* [PATCH v4 0/5] Add pin control support for lpass sc7280
@ 2021-12-03 11:32 Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (4 more replies)
0 siblings, 5 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu
This patch series is to split lpass variant common pin control
functions and SoC specific functions and to add lpass sc7280 pincontrol support.
It also Adds dt-bindings for lpass sc7280 lpass lpi pincontrol.
Changes Since V3:
-- Update separate Kconfig fields for sm8250 and sc7280.
-- Update module license and description.
-- Move static variables to corresponding .c files from header file.
Changes Since V2:
-- Add new dt-bindings for sc7280 lpi driver.
-- Make clock voting change as separate patch.
-- Split existing pincontrol driver and make common functions
as part of separate file.
-- Rename lpass pincontrol lpi dt-bindings to sm8250 specific dt-bindings
Changes Since V1:
-- Make lpi pinctrl variant data structure as constant
-- Add appropriate commit message
-- Change signedoff by sequence.
Srinivasa Rao Mandadapu (5):
dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
pinctrl: qcom: Move chip specific functions to right files
pinctrl: qcom: Update clock voting as optional
pinctrl: qcom: Add SC7280 lpass pin configuration
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 -----------
.../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 ++++++++++
.../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++
drivers/pinctrl/qcom/Kconfig | 16 ++
drivers/pinctrl/qcom/Makefile | 2 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 252 +--------------------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++
9 files changed, 704 insertions(+), 374 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v4 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
Change generic lpass lpi pincotrol bindings file to SoC specific file,
to distinguish and accomadate other SoC specific dt bindings.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.com>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ---------------------
.../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++
2 files changed, 130 insertions(+), 130 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
deleted file mode 100644
index e47ebf9..0000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
+++ /dev/null
@@ -1,130 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
- Low Power Island (LPI) TLMM block
-
-maintainers:
- - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-
-description: |
- This binding describes the Top Level Mode Multiplexer block found in the
- LPASS LPI IP on most Qualcomm SoCs
-
-properties:
- compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
-
- reg:
- minItems: 2
- maxItems: 2
-
- clocks:
- items:
- - description: LPASS Core voting clock
- - description: LPASS Audio voting clock
-
- clock-names:
- items:
- - const: core
- - const: audio
-
- gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
-#PIN CONFIGURATION NODES
-patternProperties:
- '-pins$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
-
- properties:
- pins:
- description:
- List of gpio pins affected by the properties specified in this
- subnode.
- items:
- oneOf:
- - pattern: "^gpio([0-9]|[1-9][0-9])$"
- minItems: 1
- maxItems: 14
-
- function:
- enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
- qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
- dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
- i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
- dmic3_data, i2s2_data ]
- description:
- Specify the alternative function to be configured for the specified
- pins.
-
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-pull-down: true
-
- bias-pull-up: true
-
- bias-disable: true
-
- output-high: true
-
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/sound/qcom,q6afe.h>
- lpi_tlmm: pinctrl@33c0000 {
- compatible = "qcom,sm8250-lpass-lpi-pinctrl";
- reg = <0x33c0000 0x20000>,
- <0x3550000 0x10000>;
- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- clock-names = "core", "audio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&lpi_tlmm 0 0 14>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..e47ebf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ lpi_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 14>;
+ };
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Venkata Prasad Potturu, Srinivasa Rao Mandadapu
Change generic lpass lpi pincotrol bindings file to SoC specific file,
to distinguish and accomadate other SoC specific dt bindings.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.com>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
.../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ---------------------
.../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++
2 files changed, 130 insertions(+), 130 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
deleted file mode 100644
index e47ebf9..0000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
+++ /dev/null
@@ -1,130 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
- Low Power Island (LPI) TLMM block
-
-maintainers:
- - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-
-description: |
- This binding describes the Top Level Mode Multiplexer block found in the
- LPASS LPI IP on most Qualcomm SoCs
-
-properties:
- compatible:
- const: qcom,sm8250-lpass-lpi-pinctrl
-
- reg:
- minItems: 2
- maxItems: 2
-
- clocks:
- items:
- - description: LPASS Core voting clock
- - description: LPASS Audio voting clock
-
- clock-names:
- items:
- - const: core
- - const: audio
-
- gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
-#PIN CONFIGURATION NODES
-patternProperties:
- '-pins$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
- $ref: "/schemas/pinctrl/pincfg-node.yaml"
-
- properties:
- pins:
- description:
- List of gpio pins affected by the properties specified in this
- subnode.
- items:
- oneOf:
- - pattern: "^gpio([0-9]|[1-9][0-9])$"
- minItems: 1
- maxItems: 14
-
- function:
- enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
- qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
- dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
- i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
- dmic3_data, i2s2_data ]
- description:
- Specify the alternative function to be configured for the specified
- pins.
-
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-pull-down: true
-
- bias-pull-up: true
-
- bias-disable: true
-
- output-high: true
-
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/sound/qcom,q6afe.h>
- lpi_tlmm: pinctrl@33c0000 {
- compatible = "qcom,sm8250-lpass-lpi-pinctrl";
- reg = <0x33c0000 0x20000>,
- <0x3550000 0x10000>;
- clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- clock-names = "core", "audio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&lpi_tlmm 0 0 14>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..e47ebf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sm8250-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 14
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+ lpi_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8250-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 14>;
+ };
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Add device tree binding Documentation details for Qualcomm SC7280
LPASS LPI pinctrl driver.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
.../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..62babb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sc7280-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 15
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+ };
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Venkata Prasad Potturu, Srinivasa Rao Mandadapu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Add device tree binding Documentation details for Qualcomm SC7280
LPASS LPI pinctrl driver.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
.../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..62babb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
+ Low Power Island (LPI) TLMM block
+
+maintainers:
+ - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ LPASS LPI IP on most Qualcomm SoCs
+
+properties:
+ compatible:
+ const: qcom,sc7280-lpass-lpi-pinctrl
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9])$"
+ minItems: 1
+ maxItems: 15
+
+ function:
+ enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
+ qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
+ dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
+ i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
+ dmic3_data, i2s2_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0x33c0000 0x20000>,
+ <0x3550000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+ };
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Update lpass lpi pin control driver to accommodate new lpass variant
SoC specific drivers.
Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
and common declarations to pinctrl-lpass-lpi.h header file.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
5 files changed, 280 insertions(+), 243 deletions(-)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5ff4207..e750e10 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+config PINCTRL_SM8250_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 7a12e8c..8bc877e 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
+obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 2f19ab4..bcc12f6 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -4,237 +4,16 @@
* Copyright (c) 2020 Linaro Ltd.
*/
-#include <linux/bitops.h>
-#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
-#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
-
-#define LPI_SLEW_RATE_CTL_REG 0xa000
-#define LPI_TLMM_REG_OFFSET 0x1000
-#define LPI_SLEW_RATE_MAX 0x03
-#define LPI_SLEW_BITS_SIZE 0x02
-#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
-#define LPI_GPIO_CFG_REG 0x00
-#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
-#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
-#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
-#define LPI_GPIO_OE_MASK BIT(9)
-#define LPI_GPIO_VALUE_REG 0x04
-#define LPI_GPIO_VALUE_IN_MASK BIT(0)
-#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
-
-#define LPI_GPIO_BIAS_DISABLE 0x0
-#define LPI_GPIO_PULL_DOWN 0x1
-#define LPI_GPIO_KEEPER 0x2
-#define LPI_GPIO_PULL_UP 0x3
-#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
-#define NO_SLEW -1
-
-#define LPI_FUNCTION(fname) \
- [LPI_MUX_##fname] = { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
- { \
- .name = "gpio" #id, \
- .pins = gpio##id##_pins, \
- .pin = id, \
- .slew_offset = soff, \
- .npins = ARRAY_SIZE(gpio##id##_pins), \
- .funcs = (int[]){ \
- LPI_MUX_gpio, \
- LPI_MUX_##f1, \
- LPI_MUX_##f2, \
- LPI_MUX_##f3, \
- LPI_MUX_##f4, \
- }, \
- .nfuncs = 5, \
- }
-
-struct lpi_pingroup {
- const char *name;
- const unsigned int *pins;
- unsigned int npins;
- unsigned int pin;
- /* Bit offset in slew register for SoundWire pins only */
- int slew_offset;
- unsigned int *funcs;
- unsigned int nfuncs;
-};
-
-struct lpi_function {
- const char *name;
- const char * const *groups;
- unsigned int ngroups;
-};
-
-struct lpi_pinctrl_variant_data {
- const struct pinctrl_pin_desc *pins;
- int npins;
- const struct lpi_pingroup *groups;
- int ngroups;
- const struct lpi_function *functions;
- int nfunctions;
-};
-
-#define MAX_LPI_NUM_CLKS 2
-
-struct lpi_pinctrl {
- struct device *dev;
- struct pinctrl_dev *ctrl;
- struct gpio_chip chip;
- struct pinctrl_desc desc;
- char __iomem *tlmm_base;
- char __iomem *slew_base;
- struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
- struct mutex slew_access_lock;
- const struct lpi_pinctrl_variant_data *data;
-};
-
-/* sm8250 variant specific data */
-static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
- PINCTRL_PIN(0, "gpio0"),
- PINCTRL_PIN(1, "gpio1"),
- PINCTRL_PIN(2, "gpio2"),
- PINCTRL_PIN(3, "gpio3"),
- PINCTRL_PIN(4, "gpio4"),
- PINCTRL_PIN(5, "gpio5"),
- PINCTRL_PIN(6, "gpio6"),
- PINCTRL_PIN(7, "gpio7"),
- PINCTRL_PIN(8, "gpio8"),
- PINCTRL_PIN(9, "gpio9"),
- PINCTRL_PIN(10, "gpio10"),
- PINCTRL_PIN(11, "gpio11"),
- PINCTRL_PIN(12, "gpio12"),
- PINCTRL_PIN(13, "gpio13"),
-};
-
-enum sm8250_lpi_functions {
- LPI_MUX_dmic1_clk,
- LPI_MUX_dmic1_data,
- LPI_MUX_dmic2_clk,
- LPI_MUX_dmic2_data,
- LPI_MUX_dmic3_clk,
- LPI_MUX_dmic3_data,
- LPI_MUX_i2s1_clk,
- LPI_MUX_i2s1_data,
- LPI_MUX_i2s1_ws,
- LPI_MUX_i2s2_clk,
- LPI_MUX_i2s2_data,
- LPI_MUX_i2s2_ws,
- LPI_MUX_qua_mi2s_data,
- LPI_MUX_qua_mi2s_sclk,
- LPI_MUX_qua_mi2s_ws,
- LPI_MUX_swr_rx_clk,
- LPI_MUX_swr_rx_data,
- LPI_MUX_swr_tx_clk,
- LPI_MUX_swr_tx_data,
- LPI_MUX_wsa_swr_clk,
- LPI_MUX_wsa_swr_data,
- LPI_MUX_gpio,
- LPI_MUX__,
-};
-
-static const unsigned int gpio0_pins[] = { 0 };
-static const unsigned int gpio1_pins[] = { 1 };
-static const unsigned int gpio2_pins[] = { 2 };
-static const unsigned int gpio3_pins[] = { 3 };
-static const unsigned int gpio4_pins[] = { 4 };
-static const unsigned int gpio5_pins[] = { 5 };
-static const unsigned int gpio6_pins[] = { 6 };
-static const unsigned int gpio7_pins[] = { 7 };
-static const unsigned int gpio8_pins[] = { 8 };
-static const unsigned int gpio9_pins[] = { 9 };
-static const unsigned int gpio10_pins[] = { 10 };
-static const unsigned int gpio11_pins[] = { 11 };
-static const unsigned int gpio12_pins[] = { 12 };
-static const unsigned int gpio13_pins[] = { 13 };
-static const char * const swr_tx_clk_groups[] = { "gpio0" };
-static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
-static const char * const swr_rx_clk_groups[] = { "gpio3" };
-static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
-static const char * const dmic1_clk_groups[] = { "gpio6" };
-static const char * const dmic1_data_groups[] = { "gpio7" };
-static const char * const dmic2_clk_groups[] = { "gpio8" };
-static const char * const dmic2_data_groups[] = { "gpio9" };
-static const char * const i2s2_clk_groups[] = { "gpio10" };
-static const char * const i2s2_ws_groups[] = { "gpio11" };
-static const char * const dmic3_clk_groups[] = { "gpio12" };
-static const char * const dmic3_data_groups[] = { "gpio13" };
-static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
-static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
-static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
-static const char * const i2s1_clk_groups[] = { "gpio6" };
-static const char * const i2s1_ws_groups[] = { "gpio7" };
-static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
-static const char * const wsa_swr_clk_groups[] = { "gpio10" };
-static const char * const wsa_swr_data_groups[] = { "gpio11" };
-static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
-
-static const struct lpi_pingroup sm8250_groups[] = {
- LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
- LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
- LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
- LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
- LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
- LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
- LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
- LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
- LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
- LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
- LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
- LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
-};
-
-static const struct lpi_function sm8250_functions[] = {
- LPI_FUNCTION(dmic1_clk),
- LPI_FUNCTION(dmic1_data),
- LPI_FUNCTION(dmic2_clk),
- LPI_FUNCTION(dmic2_data),
- LPI_FUNCTION(dmic3_clk),
- LPI_FUNCTION(dmic3_data),
- LPI_FUNCTION(i2s1_clk),
- LPI_FUNCTION(i2s1_data),
- LPI_FUNCTION(i2s1_ws),
- LPI_FUNCTION(i2s2_clk),
- LPI_FUNCTION(i2s2_data),
- LPI_FUNCTION(i2s2_ws),
- LPI_FUNCTION(qua_mi2s_data),
- LPI_FUNCTION(qua_mi2s_sclk),
- LPI_FUNCTION(qua_mi2s_ws),
- LPI_FUNCTION(swr_rx_clk),
- LPI_FUNCTION(swr_rx_data),
- LPI_FUNCTION(swr_tx_clk),
- LPI_FUNCTION(swr_tx_data),
- LPI_FUNCTION(wsa_swr_clk),
- LPI_FUNCTION(wsa_swr_data),
-};
-
-static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
- .pins = sm8250_lpi_pins,
- .npins = ARRAY_SIZE(sm8250_lpi_pins),
- .groups = sm8250_groups,
- .ngroups = ARRAY_SIZE(sm8250_groups),
- .functions = sm8250_functions,
- .nfunctions = ARRAY_SIZE(sm8250_functions),
-};
+#include "pinctrl-lpass-lpi.h"
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
@@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
.dbg_show = lpi_gpio_dbg_show,
};
-static int lpi_pinctrl_probe(struct platform_device *pdev)
+int lpi_pinctrl_probe(struct platform_device *pdev)
{
const struct lpi_pinctrl_variant_data *data;
struct device *dev = &pdev->dev;
@@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
return ret;
}
+EXPORT_SYMBOL(lpi_pinctrl_probe);
-static int lpi_pinctrl_remove(struct platform_device *pdev)
+
+int lpi_pinctrl_remove(struct platform_device *pdev)
{
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
@@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
return 0;
}
+EXPORT_SYMBOL(lpi_pinctrl_remove);
-static const struct of_device_id lpi_pinctrl_of_match[] = {
- {
- .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
- .data = &sm8250_lpi_data,
- },
- { }
-};
-MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
-
-static struct platform_driver lpi_pinctrl_driver = {
- .driver = {
- .name = "qcom-lpass-lpi-pinctrl",
- .of_match_table = lpi_pinctrl_of_match,
- },
- .probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
-};
-
-module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
MODULE_LICENSE("GPL");
+
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
new file mode 100644
index 0000000..ad84565
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+#ifndef __PINCTRL_LPASS_LPI_H__
+#define __PINCTRL_LPASS_LPI_H__
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET 0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER 0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW -1
+
+#define LPI_FUNCTION(fname) \
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .pin = id, \
+ .slew_offset = soff, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5, \
+ }
+
+struct lpi_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+ unsigned int pin;
+ /* Bit offset in slew register for SoundWire pins only */
+ int slew_offset;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+};
+
+#define MAX_LPI_NUM_CLKS 2
+
+struct lpi_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *ctrl;
+ struct gpio_chip chip;
+ struct pinctrl_desc desc;
+ char __iomem *tlmm_base;
+ char __iomem *slew_base;
+ struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
+ struct mutex slew_access_lock;
+ const struct lpi_pinctrl_variant_data *data;
+};
+
+int lpi_pinctrl_probe(struct platform_device *pdev);
+int lpi_pinctrl_remove(struct platform_device *pdev);
+
+#endif /*__PINCTRL_LPASS_LPI_H__*/
+
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
new file mode 100644
index 0000000..9a5db15
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+
+/* sm8250 variant specific data */
+static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
+
+static const struct lpi_pingroup sm8250_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
+ LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+};
+
+static const struct lpi_function sm8250_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
+ .pins = sm8250_lpi_pins,
+ .npins = ARRAY_SIZE(sm8250_lpi_pins),
+ .groups = sm8250_groups,
+ .ngroups = ARRAY_SIZE(sm8250_groups),
+ .functions = sm8250_functions,
+ .nfunctions = ARRAY_SIZE(sm8250_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
+ .data = &sm8250_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sm8250-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
+
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Venkata Prasad Potturu, Srinivasa Rao Mandadapu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Update lpass lpi pin control driver to accommodate new lpass variant
SoC specific drivers.
Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
and common declarations to pinctrl-lpass-lpi.h header file.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
5 files changed, 280 insertions(+), 243 deletions(-)
create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5ff4207..e750e10 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
+config PINCTRL_SM8250_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 7a12e8c..8bc877e 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
+obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 2f19ab4..bcc12f6 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -4,237 +4,16 @@
* Copyright (c) 2020 Linaro Ltd.
*/
-#include <linux/bitops.h>
-#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
-#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
-#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
#include "../core.h"
#include "../pinctrl-utils.h"
-
-#define LPI_SLEW_RATE_CTL_REG 0xa000
-#define LPI_TLMM_REG_OFFSET 0x1000
-#define LPI_SLEW_RATE_MAX 0x03
-#define LPI_SLEW_BITS_SIZE 0x02
-#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
-#define LPI_GPIO_CFG_REG 0x00
-#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
-#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
-#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
-#define LPI_GPIO_OE_MASK BIT(9)
-#define LPI_GPIO_VALUE_REG 0x04
-#define LPI_GPIO_VALUE_IN_MASK BIT(0)
-#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
-
-#define LPI_GPIO_BIAS_DISABLE 0x0
-#define LPI_GPIO_PULL_DOWN 0x1
-#define LPI_GPIO_KEEPER 0x2
-#define LPI_GPIO_PULL_UP 0x3
-#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
-#define NO_SLEW -1
-
-#define LPI_FUNCTION(fname) \
- [LPI_MUX_##fname] = { \
- .name = #fname, \
- .groups = fname##_groups, \
- .ngroups = ARRAY_SIZE(fname##_groups), \
- }
-
-#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
- { \
- .name = "gpio" #id, \
- .pins = gpio##id##_pins, \
- .pin = id, \
- .slew_offset = soff, \
- .npins = ARRAY_SIZE(gpio##id##_pins), \
- .funcs = (int[]){ \
- LPI_MUX_gpio, \
- LPI_MUX_##f1, \
- LPI_MUX_##f2, \
- LPI_MUX_##f3, \
- LPI_MUX_##f4, \
- }, \
- .nfuncs = 5, \
- }
-
-struct lpi_pingroup {
- const char *name;
- const unsigned int *pins;
- unsigned int npins;
- unsigned int pin;
- /* Bit offset in slew register for SoundWire pins only */
- int slew_offset;
- unsigned int *funcs;
- unsigned int nfuncs;
-};
-
-struct lpi_function {
- const char *name;
- const char * const *groups;
- unsigned int ngroups;
-};
-
-struct lpi_pinctrl_variant_data {
- const struct pinctrl_pin_desc *pins;
- int npins;
- const struct lpi_pingroup *groups;
- int ngroups;
- const struct lpi_function *functions;
- int nfunctions;
-};
-
-#define MAX_LPI_NUM_CLKS 2
-
-struct lpi_pinctrl {
- struct device *dev;
- struct pinctrl_dev *ctrl;
- struct gpio_chip chip;
- struct pinctrl_desc desc;
- char __iomem *tlmm_base;
- char __iomem *slew_base;
- struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
- struct mutex slew_access_lock;
- const struct lpi_pinctrl_variant_data *data;
-};
-
-/* sm8250 variant specific data */
-static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
- PINCTRL_PIN(0, "gpio0"),
- PINCTRL_PIN(1, "gpio1"),
- PINCTRL_PIN(2, "gpio2"),
- PINCTRL_PIN(3, "gpio3"),
- PINCTRL_PIN(4, "gpio4"),
- PINCTRL_PIN(5, "gpio5"),
- PINCTRL_PIN(6, "gpio6"),
- PINCTRL_PIN(7, "gpio7"),
- PINCTRL_PIN(8, "gpio8"),
- PINCTRL_PIN(9, "gpio9"),
- PINCTRL_PIN(10, "gpio10"),
- PINCTRL_PIN(11, "gpio11"),
- PINCTRL_PIN(12, "gpio12"),
- PINCTRL_PIN(13, "gpio13"),
-};
-
-enum sm8250_lpi_functions {
- LPI_MUX_dmic1_clk,
- LPI_MUX_dmic1_data,
- LPI_MUX_dmic2_clk,
- LPI_MUX_dmic2_data,
- LPI_MUX_dmic3_clk,
- LPI_MUX_dmic3_data,
- LPI_MUX_i2s1_clk,
- LPI_MUX_i2s1_data,
- LPI_MUX_i2s1_ws,
- LPI_MUX_i2s2_clk,
- LPI_MUX_i2s2_data,
- LPI_MUX_i2s2_ws,
- LPI_MUX_qua_mi2s_data,
- LPI_MUX_qua_mi2s_sclk,
- LPI_MUX_qua_mi2s_ws,
- LPI_MUX_swr_rx_clk,
- LPI_MUX_swr_rx_data,
- LPI_MUX_swr_tx_clk,
- LPI_MUX_swr_tx_data,
- LPI_MUX_wsa_swr_clk,
- LPI_MUX_wsa_swr_data,
- LPI_MUX_gpio,
- LPI_MUX__,
-};
-
-static const unsigned int gpio0_pins[] = { 0 };
-static const unsigned int gpio1_pins[] = { 1 };
-static const unsigned int gpio2_pins[] = { 2 };
-static const unsigned int gpio3_pins[] = { 3 };
-static const unsigned int gpio4_pins[] = { 4 };
-static const unsigned int gpio5_pins[] = { 5 };
-static const unsigned int gpio6_pins[] = { 6 };
-static const unsigned int gpio7_pins[] = { 7 };
-static const unsigned int gpio8_pins[] = { 8 };
-static const unsigned int gpio9_pins[] = { 9 };
-static const unsigned int gpio10_pins[] = { 10 };
-static const unsigned int gpio11_pins[] = { 11 };
-static const unsigned int gpio12_pins[] = { 12 };
-static const unsigned int gpio13_pins[] = { 13 };
-static const char * const swr_tx_clk_groups[] = { "gpio0" };
-static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
-static const char * const swr_rx_clk_groups[] = { "gpio3" };
-static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
-static const char * const dmic1_clk_groups[] = { "gpio6" };
-static const char * const dmic1_data_groups[] = { "gpio7" };
-static const char * const dmic2_clk_groups[] = { "gpio8" };
-static const char * const dmic2_data_groups[] = { "gpio9" };
-static const char * const i2s2_clk_groups[] = { "gpio10" };
-static const char * const i2s2_ws_groups[] = { "gpio11" };
-static const char * const dmic3_clk_groups[] = { "gpio12" };
-static const char * const dmic3_data_groups[] = { "gpio13" };
-static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
-static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
-static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
-static const char * const i2s1_clk_groups[] = { "gpio6" };
-static const char * const i2s1_ws_groups[] = { "gpio7" };
-static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
-static const char * const wsa_swr_clk_groups[] = { "gpio10" };
-static const char * const wsa_swr_data_groups[] = { "gpio11" };
-static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
-
-static const struct lpi_pingroup sm8250_groups[] = {
- LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
- LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
- LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
- LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
- LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
- LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
- LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
- LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
- LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
- LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
- LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
- LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
- LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
-};
-
-static const struct lpi_function sm8250_functions[] = {
- LPI_FUNCTION(dmic1_clk),
- LPI_FUNCTION(dmic1_data),
- LPI_FUNCTION(dmic2_clk),
- LPI_FUNCTION(dmic2_data),
- LPI_FUNCTION(dmic3_clk),
- LPI_FUNCTION(dmic3_data),
- LPI_FUNCTION(i2s1_clk),
- LPI_FUNCTION(i2s1_data),
- LPI_FUNCTION(i2s1_ws),
- LPI_FUNCTION(i2s2_clk),
- LPI_FUNCTION(i2s2_data),
- LPI_FUNCTION(i2s2_ws),
- LPI_FUNCTION(qua_mi2s_data),
- LPI_FUNCTION(qua_mi2s_sclk),
- LPI_FUNCTION(qua_mi2s_ws),
- LPI_FUNCTION(swr_rx_clk),
- LPI_FUNCTION(swr_rx_data),
- LPI_FUNCTION(swr_tx_clk),
- LPI_FUNCTION(swr_tx_data),
- LPI_FUNCTION(wsa_swr_clk),
- LPI_FUNCTION(wsa_swr_data),
-};
-
-static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
- .pins = sm8250_lpi_pins,
- .npins = ARRAY_SIZE(sm8250_lpi_pins),
- .groups = sm8250_groups,
- .ngroups = ARRAY_SIZE(sm8250_groups),
- .functions = sm8250_functions,
- .nfunctions = ARRAY_SIZE(sm8250_functions),
-};
+#include "pinctrl-lpass-lpi.h"
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
@@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
.dbg_show = lpi_gpio_dbg_show,
};
-static int lpi_pinctrl_probe(struct platform_device *pdev)
+int lpi_pinctrl_probe(struct platform_device *pdev)
{
const struct lpi_pinctrl_variant_data *data;
struct device *dev = &pdev->dev;
@@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
return ret;
}
+EXPORT_SYMBOL(lpi_pinctrl_probe);
-static int lpi_pinctrl_remove(struct platform_device *pdev)
+
+int lpi_pinctrl_remove(struct platform_device *pdev)
{
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
@@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
return 0;
}
+EXPORT_SYMBOL(lpi_pinctrl_remove);
-static const struct of_device_id lpi_pinctrl_of_match[] = {
- {
- .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
- .data = &sm8250_lpi_data,
- },
- { }
-};
-MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
-
-static struct platform_driver lpi_pinctrl_driver = {
- .driver = {
- .name = "qcom-lpass-lpi-pinctrl",
- .of_match_table = lpi_pinctrl_of_match,
- },
- .probe = lpi_pinctrl_probe,
- .remove = lpi_pinctrl_remove,
-};
-
-module_platform_driver(lpi_pinctrl_driver);
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
MODULE_LICENSE("GPL");
+
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
new file mode 100644
index 0000000..ad84565
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+#ifndef __PINCTRL_LPASS_LPI_H__
+#define __PINCTRL_LPASS_LPI_H__
+
+#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_TLMM_REG_OFFSET 0x1000
+#define LPI_SLEW_RATE_MAX 0x03
+#define LPI_SLEW_BITS_SIZE 0x02
+#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
+#define LPI_GPIO_CFG_REG 0x00
+#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
+#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
+#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
+#define LPI_GPIO_OE_MASK BIT(9)
+#define LPI_GPIO_VALUE_REG 0x04
+#define LPI_GPIO_VALUE_IN_MASK BIT(0)
+#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
+
+#define LPI_GPIO_BIAS_DISABLE 0x0
+#define LPI_GPIO_PULL_DOWN 0x1
+#define LPI_GPIO_KEEPER 0x2
+#define LPI_GPIO_PULL_UP 0x3
+#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
+#define NO_SLEW -1
+
+#define LPI_FUNCTION(fname) \
+ [LPI_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .pin = id, \
+ .slew_offset = soff, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5, \
+ }
+
+struct lpi_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ unsigned int npins;
+ unsigned int pin;
+ /* Bit offset in slew register for SoundWire pins only */
+ int slew_offset;
+ unsigned int *funcs;
+ unsigned int nfuncs;
+};
+
+struct lpi_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct lpi_pinctrl_variant_data {
+ const struct pinctrl_pin_desc *pins;
+ int npins;
+ const struct lpi_pingroup *groups;
+ int ngroups;
+ const struct lpi_function *functions;
+ int nfunctions;
+};
+
+#define MAX_LPI_NUM_CLKS 2
+
+struct lpi_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *ctrl;
+ struct gpio_chip chip;
+ struct pinctrl_desc desc;
+ char __iomem *tlmm_base;
+ char __iomem *slew_base;
+ struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
+ struct mutex slew_access_lock;
+ const struct lpi_pinctrl_variant_data *data;
+};
+
+int lpi_pinctrl_probe(struct platform_device *pdev);
+int lpi_pinctrl_remove(struct platform_device *pdev);
+
+#endif /*__PINCTRL_LPASS_LPI_H__*/
+
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
new file mode 100644
index 0000000..9a5db15
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020 Linaro Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+
+/* sm8250 variant specific data */
+static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
+
+static const struct lpi_pingroup sm8250_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
+ LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+};
+
+static const struct lpi_function sm8250_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
+ .pins = sm8250_lpi_pins,
+ .npins = ARRAY_SIZE(sm8250_lpi_pins),
+ .groups = sm8250_groups,
+ .ngroups = ARRAY_SIZE(sm8250_groups),
+ .functions = sm8250_functions,
+ .nfunctions = ARRAY_SIZE(sm8250_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
+ .data = &sm8250_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sm8250-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
+
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, these are maintained as power domains and
operated from lpass audio core cc.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index bcc12f6..c2a1110 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
"Slew resource not provided\n");
- ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
+ ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
return dev_err_probe(dev, ret, "Can't get clocks\n");
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Venkata Prasad Potturu, Srinivasa Rao Mandadapu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, these are maintained as power domains and
operated from lpass audio core cc.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index bcc12f6..c2a1110 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
"Slew resource not provided\n");
- ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
+ ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
return dev_err_probe(dev, ret, "Can't get clocks\n");
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
` (3 subsequent siblings)
4 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Srinivasa Rao Mandadapu, Venkata Prasad Potturu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Add pin control support for SC7280 LPASS LPI.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/Kconfig | 8 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index e750e10..37fe868 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
+config PINCTRL_SC7280_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 8bc877e..6c3ddaf 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
+obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
new file mode 100644
index 0000000..94bec15
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * ALSA SoC platform-machine driver for QTi LPASS
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+static const unsigned int gpio14_pins[] = { 14 };
+
+/* sc7280 variant specific data */
+static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
+
+static const struct lpi_pingroup sc7280_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
+ LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+ LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
+};
+
+static const struct lpi_function sc7280_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
+ .pins = sc7280_lpi_pins,
+ .npins = ARRAY_SIZE(sc7280_lpi_pins),
+ .groups = sc7280_groups,
+ .ngroups = ARRAY_SIZE(sc7280_groups),
+ .functions = sc7280_functions,
+ .nfunctions = ARRAY_SIZE(sc7280_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
+ .data = &sc7280_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sc7280-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
+
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
@ 2021-12-03 11:32 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-03 11:32 UTC (permalink / raw)
To: agross, bjorn.andersson, lgirdwood, broonie, robh+dt, plai,
bgoswami, perex, tiwai, srinivas.kandagatla, rohitkr,
linux-arm-msm, alsa-devel, devicetree, linux-kernel, swboyd,
judyhsiao, Linus Walleij, linux-gpio
Cc: Venkata Prasad Potturu, Srinivasa Rao Mandadapu
From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Add pin control support for SC7280 LPASS LPI.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
---
drivers/pinctrl/qcom/Kconfig | 8 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index e750e10..37fe868 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
+config PINCTRL_SC7280_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
+
endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 8bc877e..6c3ddaf 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
+obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
new file mode 100644
index 0000000..94bec15
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * ALSA SoC platform-machine driver for QTi LPASS
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_dmic1_clk,
+ LPI_MUX_dmic1_data,
+ LPI_MUX_dmic2_clk,
+ LPI_MUX_dmic2_data,
+ LPI_MUX_dmic3_clk,
+ LPI_MUX_dmic3_data,
+ LPI_MUX_i2s1_clk,
+ LPI_MUX_i2s1_data,
+ LPI_MUX_i2s1_ws,
+ LPI_MUX_i2s2_clk,
+ LPI_MUX_i2s2_data,
+ LPI_MUX_i2s2_ws,
+ LPI_MUX_qua_mi2s_data,
+ LPI_MUX_qua_mi2s_sclk,
+ LPI_MUX_qua_mi2s_ws,
+ LPI_MUX_swr_rx_clk,
+ LPI_MUX_swr_rx_data,
+ LPI_MUX_swr_tx_clk,
+ LPI_MUX_swr_tx_data,
+ LPI_MUX_wsa_swr_clk,
+ LPI_MUX_wsa_swr_data,
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const unsigned int gpio0_pins[] = { 0 };
+static const unsigned int gpio1_pins[] = { 1 };
+static const unsigned int gpio2_pins[] = { 2 };
+static const unsigned int gpio3_pins[] = { 3 };
+static const unsigned int gpio4_pins[] = { 4 };
+static const unsigned int gpio5_pins[] = { 5 };
+static const unsigned int gpio6_pins[] = { 6 };
+static const unsigned int gpio7_pins[] = { 7 };
+static const unsigned int gpio8_pins[] = { 8 };
+static const unsigned int gpio9_pins[] = { 9 };
+static const unsigned int gpio10_pins[] = { 10 };
+static const unsigned int gpio11_pins[] = { 11 };
+static const unsigned int gpio12_pins[] = { 12 };
+static const unsigned int gpio13_pins[] = { 13 };
+static const unsigned int gpio14_pins[] = { 14 };
+
+/* sc7280 variant specific data */
+static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+};
+
+static const char * const swr_tx_clk_groups[] = { "gpio0" };
+static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
+static const char * const swr_rx_clk_groups[] = { "gpio3" };
+static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
+static const char * const dmic1_clk_groups[] = { "gpio6" };
+static const char * const dmic1_data_groups[] = { "gpio7" };
+static const char * const dmic2_clk_groups[] = { "gpio8" };
+static const char * const dmic2_data_groups[] = { "gpio9" };
+static const char * const i2s2_clk_groups[] = { "gpio10" };
+static const char * const i2s2_ws_groups[] = { "gpio11" };
+static const char * const dmic3_clk_groups[] = { "gpio12" };
+static const char * const dmic3_data_groups[] = { "gpio13" };
+static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
+static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
+static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
+static const char * const i2s1_clk_groups[] = { "gpio6" };
+static const char * const i2s1_ws_groups[] = { "gpio7" };
+static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
+static const char * const wsa_swr_clk_groups[] = { "gpio10" };
+static const char * const wsa_swr_data_groups[] = { "gpio11" };
+static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
+
+static const struct lpi_pingroup sc7280_groups[] = {
+ LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
+ LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
+ LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
+ LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
+ LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
+ LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
+ LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
+ LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
+ LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
+ LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
+ LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
+ LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
+ LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
+ LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
+};
+
+static const struct lpi_function sc7280_functions[] = {
+ LPI_FUNCTION(dmic1_clk),
+ LPI_FUNCTION(dmic1_data),
+ LPI_FUNCTION(dmic2_clk),
+ LPI_FUNCTION(dmic2_data),
+ LPI_FUNCTION(dmic3_clk),
+ LPI_FUNCTION(dmic3_data),
+ LPI_FUNCTION(i2s1_clk),
+ LPI_FUNCTION(i2s1_data),
+ LPI_FUNCTION(i2s1_ws),
+ LPI_FUNCTION(i2s2_clk),
+ LPI_FUNCTION(i2s2_data),
+ LPI_FUNCTION(i2s2_ws),
+ LPI_FUNCTION(qua_mi2s_data),
+ LPI_FUNCTION(qua_mi2s_sclk),
+ LPI_FUNCTION(qua_mi2s_ws),
+ LPI_FUNCTION(swr_rx_clk),
+ LPI_FUNCTION(swr_rx_data),
+ LPI_FUNCTION(swr_tx_clk),
+ LPI_FUNCTION(swr_tx_data),
+ LPI_FUNCTION(wsa_swr_clk),
+ LPI_FUNCTION(wsa_swr_data),
+};
+
+static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
+ .pins = sc7280_lpi_pins,
+ .npins = ARRAY_SIZE(sc7280_lpi_pins),
+ .groups = sc7280_groups,
+ .ngroups = ARRAY_SIZE(sc7280_groups),
+ .functions = sc7280_functions,
+ .nfunctions = ARRAY_SIZE(sc7280_functions),
+};
+
+static const struct of_device_id lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
+ .data = &sc7280_lpi_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
+
+static struct platform_driver lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sc7280-lpass-lpi-pinctrl",
+ .of_match_table = lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+
+module_platform_driver(lpi_pinctrl_driver);
+MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
+
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
@ 2021-12-03 23:34 ` Rob Herring
-1 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2021-12-03 23:34 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: robh+dt, Srinivasa Rao Mandadapu, alsa-devel, rohitkr, plai,
bjorn.andersson, agross, linux-arm-msm, devicetree, judyhsiao,
Linus Walleij, bgoswami, srinivas.kandagatla, broonie, tiwai,
lgirdwood, perex, swboyd, linux-kernel, linux-gpio,
Venkata Prasad Potturu
On Fri, 03 Dec 2021 17:02:17 +0530, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Add device tree binding Documentation details for Qualcomm SC7280
> LPASS LPI pinctrl driver.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml: duplicate '$id' value 'http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#'
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1563187
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
@ 2021-12-03 23:34 ` Rob Herring
-1 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2021-12-03 23:34 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: swboyd, judyhsiao, devicetree, broonie, linux-kernel, alsa-devel,
plai, Venkata Prasad Potturu, robh+dt, linux-arm-msm,
srinivas.kandagatla, bjorn.andersson, tiwai, bgoswami,
linux-gpio, rohitkr, perex, agross, Linus Walleij, lgirdwood
On Fri, 03 Dec 2021 17:02:16 +0530, Srinivasa Rao Mandadapu wrote:
> Change generic lpass lpi pincotrol bindings file to SoC specific file,
> to distinguish and accomadate other SoC specific dt bindings.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.com>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ---------------------
> .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++
> 2 files changed, 130 insertions(+), 130 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1563181
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings
@ 2021-12-03 23:34 ` Rob Herring
0 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2021-12-03 23:34 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Srinivasa Rao Mandadapu,
lgirdwood, Venkata Prasad Potturu, linux-arm-msm, plai, tiwai,
agross, swboyd, bjorn.andersson, linux-gpio, robh+dt, rohitkr,
broonie, judyhsiao, Linus Walleij, linux-kernel
On Fri, 03 Dec 2021 17:02:17 +0530, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Add device tree binding Documentation details for Qualcomm SC7280
> LPASS LPI pinctrl driver.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 115 +++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml: duplicate '$id' value 'http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#'
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1563187
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific
@ 2021-12-03 23:34 ` Rob Herring
0 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2021-12-03 23:34 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, lgirdwood,
Venkata Prasad Potturu, linux-arm-msm, plai, tiwai, linux-kernel,
robh+dt, swboyd, linux-gpio, broonie, agross, rohitkr,
bjorn.andersson, judyhsiao, Linus Walleij
On Fri, 03 Dec 2021 17:02:16 +0530, Srinivasa Rao Mandadapu wrote:
> Change generic lpass lpi pincotrol bindings file to SoC specific file,
> to distinguish and accomadate other SoC specific dt bindings.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.com>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> .../bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml | 130 ---------------------
> .../pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml | 130 +++++++++++++++++++++
> 2 files changed, 130 insertions(+), 130 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1563181
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
(?)
@ 2021-12-04 21:26 ` kernel test robot
-1 siblings, 0 replies; 28+ messages in thread
From: kernel test robot @ 2021-12-04 21:26 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 15243 bytes --]
Hi Srinivasa,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linusw-pinctrl/devel]
[also build test ERROR on v5.16-rc3 next-20211203]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Srinivasa-Rao-Mandadapu/Add-pin-control-support-for-lpass-sc7280/20211203-193459
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20211205/202112050556.lOn2ELbe-lkp(a)intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ecdbb1a63402cec9531a8c9490fd70fe8feeed87
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Srinivasa-Rao-Mandadapu/Add-pin-control-support-for-lpass-sc7280/20211203-193459
git checkout ecdbb1a63402cec9531a8c9490fd70fe8feeed87
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c: In function 'lpi_gpio_set_mux':
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:113:9: error: implicit declaration of function 'u32p_replace_bits' [-Werror=implicit-function-declaration]
113 | u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
| ^~~~~~~~~~~~~~~~~
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c: In function 'lpi_config_get':
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:138:16: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
138 | pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
| ^~~~~~~~~
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c: In function 'lpi_config_set':
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:244:23: error: implicit declaration of function 'u32_encode_bits' [-Werror=implicit-function-declaration]
244 | val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
| ^~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/u32p_replace_bits +113 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 95
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 96 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 97 unsigned int group_num)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 98 {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 99 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 100 const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 101 u32 val;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 102 int i, pin = g->pin;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 103
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 104 for (i = 0; i < g->nfuncs; i++) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 105 if (g->funcs[i] == function)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 106 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 107 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 108
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 109 if (WARN_ON(i == g->nfuncs))
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 110 return -EINVAL;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 111
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 112 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 @113 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 114 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 115
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 116 return 0;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 117 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 118
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 119 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 120 .get_functions_count = lpi_gpio_get_functions_count,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 121 .get_function_name = lpi_gpio_get_function_name,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 122 .get_function_groups = lpi_gpio_get_function_groups,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 123 .set_mux = lpi_gpio_set_mux,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 124 };
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 125
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 126 static int lpi_config_get(struct pinctrl_dev *pctldev,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 127 unsigned int pin, unsigned long *config)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 128 {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 129 unsigned int param = pinconf_to_config_param(*config);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 130 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 131 unsigned int arg = 0;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 132 int is_out;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 133 int pull;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 134 u32 ctl_reg;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 135
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 136 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 137 is_out = ctl_reg & LPI_GPIO_OE_MASK;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 @138 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 139
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 140 switch (param) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 141 case PIN_CONFIG_BIAS_DISABLE:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 142 if (pull == LPI_GPIO_BIAS_DISABLE)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 143 arg = 1;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 144 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 145 case PIN_CONFIG_BIAS_PULL_DOWN:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 146 if (pull == LPI_GPIO_PULL_DOWN)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 147 arg = 1;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 148 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 149 case PIN_CONFIG_BIAS_BUS_HOLD:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 150 if (pull == LPI_GPIO_KEEPER)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 151 arg = 1;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 152 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 153 case PIN_CONFIG_BIAS_PULL_UP:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 154 if (pull == LPI_GPIO_PULL_UP)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 155 arg = 1;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 156 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 157 case PIN_CONFIG_INPUT_ENABLE:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 158 case PIN_CONFIG_OUTPUT:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 159 if (is_out)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 160 arg = 1;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 161 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 162 default:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 163 return -EINVAL;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 164 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 165
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 166 *config = pinconf_to_config_packed(param, arg);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 167 return 0;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 168 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 169
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 170 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 171 unsigned long *configs, unsigned int nconfs)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 172 {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 173 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
2a9be38099e338f Jonathan Marek 2021-03-04 174 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 175 bool value, output_enabled = false;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 176 const struct lpi_pingroup *g;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 177 unsigned long sval;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 178 int i, slew_offset;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 179 u32 val;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 180
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 181 g = &pctrl->data->groups[group];
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 182 for (i = 0; i < nconfs; i++) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 183 param = pinconf_to_config_param(configs[i]);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 184 arg = pinconf_to_config_argument(configs[i]);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 185
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 186 switch (param) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 187 case PIN_CONFIG_BIAS_DISABLE:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 188 pullup = LPI_GPIO_BIAS_DISABLE;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 189 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 190 case PIN_CONFIG_BIAS_PULL_DOWN:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 191 pullup = LPI_GPIO_PULL_DOWN;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 192 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 193 case PIN_CONFIG_BIAS_BUS_HOLD:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 194 pullup = LPI_GPIO_KEEPER;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 195 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 196 case PIN_CONFIG_BIAS_PULL_UP:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 197 pullup = LPI_GPIO_PULL_UP;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 198 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 199 case PIN_CONFIG_INPUT_ENABLE:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 200 output_enabled = false;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 201 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 202 case PIN_CONFIG_OUTPUT:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 203 output_enabled = true;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 204 value = arg;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 205 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 206 case PIN_CONFIG_DRIVE_STRENGTH:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 207 strength = arg;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 208 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 209 case PIN_CONFIG_SLEW_RATE:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 210 if (arg > LPI_SLEW_RATE_MAX) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 211 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 212 arg, group);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 213 return -EINVAL;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 214 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 215
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 216 slew_offset = g->slew_offset;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 217 if (slew_offset == NO_SLEW)
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 218 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 219
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 220 mutex_lock(&pctrl->slew_access_lock);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 221
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 222 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 223 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 224 sval |= arg << slew_offset;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 225 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 226
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 227 mutex_unlock(&pctrl->slew_access_lock);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 228 break;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 229 default:
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 230 return -EINVAL;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 231 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 232 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 233
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 234 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 235
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 236 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 237 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 238 LPI_GPIO_OUT_STRENGTH_MASK);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 239 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 240
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 241 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 242
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 243 if (output_enabled) {
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 @244 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 245 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 246 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 247
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 248 return 0;
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 249 }
6e261d1090d6db0 Srinivas Kandagatla 2020-12-02 250
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
@ 2021-12-06 2:35 ` Bjorn Andersson
-1 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 2:35 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Srinivasa Rao Mandadapu, Venkata Prasad Potturu
On Fri 03 Dec 03:32 PST 2021, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Update bulk clock voting to optional voting as ADSP bypass platform doesn't
> need macro and decodec clocks, these are maintained as power domains and
> operated from lpass audio core cc.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index bcc12f6..c2a1110 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
> return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
> "Slew resource not provided\n");
>
> - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
> + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
If some platforms requires this clock and others doesn't have one, then
please make this statement conditional on the compatible, rather than
making it optional on both.
Thanks,
Bjorn
> if (ret)
> return dev_err_probe(dev, ret, "Can't get clocks\n");
>
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
@ 2021-12-06 2:35 ` Bjorn Andersson
0 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 2:35 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Srinivasa Rao Mandadapu,
Venkata Prasad Potturu, linux-arm-msm, plai, tiwai, agross,
robh+dt, lgirdwood, linux-gpio, broonie, rohitkr, swboyd,
judyhsiao, Linus Walleij, linux-kernel
On Fri 03 Dec 03:32 PST 2021, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Update bulk clock voting to optional voting as ADSP bypass platform doesn't
> need macro and decodec clocks, these are maintained as power domains and
> operated from lpass audio core cc.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index bcc12f6..c2a1110 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
> return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
> "Slew resource not provided\n");
>
> - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
> + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
If some platforms requires this clock and others doesn't have one, then
please make this statement conditional on the compatible, rather than
making it optional on both.
Thanks,
Bjorn
> if (ret)
> return dev_err_probe(dev, ret, "Can't get clocks\n");
>
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
@ 2021-12-06 16:25 ` Bjorn Andersson
-1 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 16:25 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Srinivasa Rao Mandadapu, Venkata Prasad Potturu
On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Add pin control support for SC7280 LPASS LPI.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 ++
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
> 3 files changed, 178 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index e750e10..37fe868 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>
> +config PINCTRL_SC7280_LPASS_LPI
> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
You misspelled SC7280 here.
> + depends on PINCTRL_LPASS_LPI
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 8bc877e..6c3ddaf 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
> +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
Please keep these entries sorted alphabetically, same with Kconfig.
Regards,
Bjorn
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> new file mode 100644
> index 0000000..94bec15
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * ALSA SoC platform-machine driver for QTi LPASS
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-lpass-lpi.h"
> +
> +enum lpass_lpi_functions {
> + LPI_MUX_dmic1_clk,
> + LPI_MUX_dmic1_data,
> + LPI_MUX_dmic2_clk,
> + LPI_MUX_dmic2_data,
> + LPI_MUX_dmic3_clk,
> + LPI_MUX_dmic3_data,
> + LPI_MUX_i2s1_clk,
> + LPI_MUX_i2s1_data,
> + LPI_MUX_i2s1_ws,
> + LPI_MUX_i2s2_clk,
> + LPI_MUX_i2s2_data,
> + LPI_MUX_i2s2_ws,
> + LPI_MUX_qua_mi2s_data,
> + LPI_MUX_qua_mi2s_sclk,
> + LPI_MUX_qua_mi2s_ws,
> + LPI_MUX_swr_rx_clk,
> + LPI_MUX_swr_rx_data,
> + LPI_MUX_swr_tx_clk,
> + LPI_MUX_swr_tx_data,
> + LPI_MUX_wsa_swr_clk,
> + LPI_MUX_wsa_swr_data,
> + LPI_MUX_gpio,
> + LPI_MUX__,
> +};
> +
> +static const unsigned int gpio0_pins[] = { 0 };
> +static const unsigned int gpio1_pins[] = { 1 };
> +static const unsigned int gpio2_pins[] = { 2 };
> +static const unsigned int gpio3_pins[] = { 3 };
> +static const unsigned int gpio4_pins[] = { 4 };
> +static const unsigned int gpio5_pins[] = { 5 };
> +static const unsigned int gpio6_pins[] = { 6 };
> +static const unsigned int gpio7_pins[] = { 7 };
> +static const unsigned int gpio8_pins[] = { 8 };
> +static const unsigned int gpio9_pins[] = { 9 };
> +static const unsigned int gpio10_pins[] = { 10 };
> +static const unsigned int gpio11_pins[] = { 11 };
> +static const unsigned int gpio12_pins[] = { 12 };
> +static const unsigned int gpio13_pins[] = { 13 };
> +static const unsigned int gpio14_pins[] = { 14 };
> +
> +/* sc7280 variant specific data */
> +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
> + PINCTRL_PIN(0, "gpio0"),
> + PINCTRL_PIN(1, "gpio1"),
> + PINCTRL_PIN(2, "gpio2"),
> + PINCTRL_PIN(3, "gpio3"),
> + PINCTRL_PIN(4, "gpio4"),
> + PINCTRL_PIN(5, "gpio5"),
> + PINCTRL_PIN(6, "gpio6"),
> + PINCTRL_PIN(7, "gpio7"),
> + PINCTRL_PIN(8, "gpio8"),
> + PINCTRL_PIN(9, "gpio9"),
> + PINCTRL_PIN(10, "gpio10"),
> + PINCTRL_PIN(11, "gpio11"),
> + PINCTRL_PIN(12, "gpio12"),
> + PINCTRL_PIN(13, "gpio13"),
> + PINCTRL_PIN(14, "gpio14"),
> +};
> +
> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> +static const char * const dmic1_clk_groups[] = { "gpio6" };
> +static const char * const dmic1_data_groups[] = { "gpio7" };
> +static const char * const dmic2_clk_groups[] = { "gpio8" };
> +static const char * const dmic2_data_groups[] = { "gpio9" };
> +static const char * const i2s2_clk_groups[] = { "gpio10" };
> +static const char * const i2s2_ws_groups[] = { "gpio11" };
> +static const char * const dmic3_clk_groups[] = { "gpio12" };
> +static const char * const dmic3_data_groups[] = { "gpio13" };
> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> +static const char * const i2s1_clk_groups[] = { "gpio6" };
> +static const char * const i2s1_ws_groups[] = { "gpio7" };
> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
> +
> +static const struct lpi_pingroup sc7280_groups[] = {
> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
> +};
> +
> +static const struct lpi_function sc7280_functions[] = {
> + LPI_FUNCTION(dmic1_clk),
> + LPI_FUNCTION(dmic1_data),
> + LPI_FUNCTION(dmic2_clk),
> + LPI_FUNCTION(dmic2_data),
> + LPI_FUNCTION(dmic3_clk),
> + LPI_FUNCTION(dmic3_data),
> + LPI_FUNCTION(i2s1_clk),
> + LPI_FUNCTION(i2s1_data),
> + LPI_FUNCTION(i2s1_ws),
> + LPI_FUNCTION(i2s2_clk),
> + LPI_FUNCTION(i2s2_data),
> + LPI_FUNCTION(i2s2_ws),
> + LPI_FUNCTION(qua_mi2s_data),
> + LPI_FUNCTION(qua_mi2s_sclk),
> + LPI_FUNCTION(qua_mi2s_ws),
> + LPI_FUNCTION(swr_rx_clk),
> + LPI_FUNCTION(swr_rx_data),
> + LPI_FUNCTION(swr_tx_clk),
> + LPI_FUNCTION(swr_tx_data),
> + LPI_FUNCTION(wsa_swr_clk),
> + LPI_FUNCTION(wsa_swr_data),
> +};
> +
> +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
> + .pins = sc7280_lpi_pins,
> + .npins = ARRAY_SIZE(sc7280_lpi_pins),
> + .groups = sc7280_groups,
> + .ngroups = ARRAY_SIZE(sc7280_groups),
> + .functions = sc7280_functions,
> + .nfunctions = ARRAY_SIZE(sc7280_functions),
> +};
> +
> +static const struct of_device_id lpi_pinctrl_of_match[] = {
> + {
> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
> + .data = &sc7280_lpi_data,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> +
> +static struct platform_driver lpi_pinctrl_driver = {
> + .driver = {
> + .name = "qcom-sc7280-lpass-lpi-pinctrl",
> + .of_match_table = lpi_pinctrl_of_match,
> + },
> + .probe = lpi_pinctrl_probe,
> + .remove = lpi_pinctrl_remove,
> +};
> +
> +module_platform_driver(lpi_pinctrl_driver);
> +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
> +MODULE_LICENSE("GPL");
> +
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
@ 2021-12-06 16:25 ` Bjorn Andersson
0 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 16:25 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Srinivasa Rao Mandadapu,
Venkata Prasad Potturu, linux-arm-msm, plai, tiwai, agross,
robh+dt, lgirdwood, linux-gpio, broonie, rohitkr, swboyd,
judyhsiao, Linus Walleij, linux-kernel
On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Add pin control support for SC7280 LPASS LPI.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 ++
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
> 3 files changed, 178 insertions(+)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index e750e10..37fe868 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>
> +config PINCTRL_SC7280_LPASS_LPI
> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
You misspelled SC7280 here.
> + depends on PINCTRL_LPASS_LPI
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 8bc877e..6c3ddaf 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
> +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
Please keep these entries sorted alphabetically, same with Kconfig.
Regards,
Bjorn
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> new file mode 100644
> index 0000000..94bec15
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * ALSA SoC platform-machine driver for QTi LPASS
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-lpass-lpi.h"
> +
> +enum lpass_lpi_functions {
> + LPI_MUX_dmic1_clk,
> + LPI_MUX_dmic1_data,
> + LPI_MUX_dmic2_clk,
> + LPI_MUX_dmic2_data,
> + LPI_MUX_dmic3_clk,
> + LPI_MUX_dmic3_data,
> + LPI_MUX_i2s1_clk,
> + LPI_MUX_i2s1_data,
> + LPI_MUX_i2s1_ws,
> + LPI_MUX_i2s2_clk,
> + LPI_MUX_i2s2_data,
> + LPI_MUX_i2s2_ws,
> + LPI_MUX_qua_mi2s_data,
> + LPI_MUX_qua_mi2s_sclk,
> + LPI_MUX_qua_mi2s_ws,
> + LPI_MUX_swr_rx_clk,
> + LPI_MUX_swr_rx_data,
> + LPI_MUX_swr_tx_clk,
> + LPI_MUX_swr_tx_data,
> + LPI_MUX_wsa_swr_clk,
> + LPI_MUX_wsa_swr_data,
> + LPI_MUX_gpio,
> + LPI_MUX__,
> +};
> +
> +static const unsigned int gpio0_pins[] = { 0 };
> +static const unsigned int gpio1_pins[] = { 1 };
> +static const unsigned int gpio2_pins[] = { 2 };
> +static const unsigned int gpio3_pins[] = { 3 };
> +static const unsigned int gpio4_pins[] = { 4 };
> +static const unsigned int gpio5_pins[] = { 5 };
> +static const unsigned int gpio6_pins[] = { 6 };
> +static const unsigned int gpio7_pins[] = { 7 };
> +static const unsigned int gpio8_pins[] = { 8 };
> +static const unsigned int gpio9_pins[] = { 9 };
> +static const unsigned int gpio10_pins[] = { 10 };
> +static const unsigned int gpio11_pins[] = { 11 };
> +static const unsigned int gpio12_pins[] = { 12 };
> +static const unsigned int gpio13_pins[] = { 13 };
> +static const unsigned int gpio14_pins[] = { 14 };
> +
> +/* sc7280 variant specific data */
> +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
> + PINCTRL_PIN(0, "gpio0"),
> + PINCTRL_PIN(1, "gpio1"),
> + PINCTRL_PIN(2, "gpio2"),
> + PINCTRL_PIN(3, "gpio3"),
> + PINCTRL_PIN(4, "gpio4"),
> + PINCTRL_PIN(5, "gpio5"),
> + PINCTRL_PIN(6, "gpio6"),
> + PINCTRL_PIN(7, "gpio7"),
> + PINCTRL_PIN(8, "gpio8"),
> + PINCTRL_PIN(9, "gpio9"),
> + PINCTRL_PIN(10, "gpio10"),
> + PINCTRL_PIN(11, "gpio11"),
> + PINCTRL_PIN(12, "gpio12"),
> + PINCTRL_PIN(13, "gpio13"),
> + PINCTRL_PIN(14, "gpio14"),
> +};
> +
> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> +static const char * const dmic1_clk_groups[] = { "gpio6" };
> +static const char * const dmic1_data_groups[] = { "gpio7" };
> +static const char * const dmic2_clk_groups[] = { "gpio8" };
> +static const char * const dmic2_data_groups[] = { "gpio9" };
> +static const char * const i2s2_clk_groups[] = { "gpio10" };
> +static const char * const i2s2_ws_groups[] = { "gpio11" };
> +static const char * const dmic3_clk_groups[] = { "gpio12" };
> +static const char * const dmic3_data_groups[] = { "gpio13" };
> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> +static const char * const i2s1_clk_groups[] = { "gpio6" };
> +static const char * const i2s1_ws_groups[] = { "gpio7" };
> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
> +
> +static const struct lpi_pingroup sc7280_groups[] = {
> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
> +};
> +
> +static const struct lpi_function sc7280_functions[] = {
> + LPI_FUNCTION(dmic1_clk),
> + LPI_FUNCTION(dmic1_data),
> + LPI_FUNCTION(dmic2_clk),
> + LPI_FUNCTION(dmic2_data),
> + LPI_FUNCTION(dmic3_clk),
> + LPI_FUNCTION(dmic3_data),
> + LPI_FUNCTION(i2s1_clk),
> + LPI_FUNCTION(i2s1_data),
> + LPI_FUNCTION(i2s1_ws),
> + LPI_FUNCTION(i2s2_clk),
> + LPI_FUNCTION(i2s2_data),
> + LPI_FUNCTION(i2s2_ws),
> + LPI_FUNCTION(qua_mi2s_data),
> + LPI_FUNCTION(qua_mi2s_sclk),
> + LPI_FUNCTION(qua_mi2s_ws),
> + LPI_FUNCTION(swr_rx_clk),
> + LPI_FUNCTION(swr_rx_data),
> + LPI_FUNCTION(swr_tx_clk),
> + LPI_FUNCTION(swr_tx_data),
> + LPI_FUNCTION(wsa_swr_clk),
> + LPI_FUNCTION(wsa_swr_data),
> +};
> +
> +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
> + .pins = sc7280_lpi_pins,
> + .npins = ARRAY_SIZE(sc7280_lpi_pins),
> + .groups = sc7280_groups,
> + .ngroups = ARRAY_SIZE(sc7280_groups),
> + .functions = sc7280_functions,
> + .nfunctions = ARRAY_SIZE(sc7280_functions),
> +};
> +
> +static const struct of_device_id lpi_pinctrl_of_match[] = {
> + {
> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
> + .data = &sc7280_lpi_data,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> +
> +static struct platform_driver lpi_pinctrl_driver = {
> + .driver = {
> + .name = "qcom-sc7280-lpass-lpi-pinctrl",
> + .of_match_table = lpi_pinctrl_of_match,
> + },
> + .probe = lpi_pinctrl_probe,
> + .remove = lpi_pinctrl_remove,
> +};
> +
> +module_platform_driver(lpi_pinctrl_driver);
> +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
> +MODULE_LICENSE("GPL");
> +
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
@ 2021-12-06 16:32 ` Bjorn Andersson
-1 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 16:32 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Srinivasa Rao Mandadapu, Venkata Prasad Potturu
On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
I don't see anything _wrong_ with the current filename, so this patch
isn't really moving chip function to the _right_ files.
May I suggest that you make $subject:
"pinctrl: qcom: Extract chip specific LPASS LPI code"
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Update lpass lpi pin control driver to accommodate new lpass variant
> SoC specific drivers.
I also have a hard time parsing this sentence.
> Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
> and common declarations to pinctrl-lpass-lpi.h header file.
How about simply:
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
> drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
> 5 files changed, 280 insertions(+), 243 deletions(-)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 5ff4207..e750e10 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>
> +config PINCTRL_SM8250_LPASS_LPI
> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
> + depends on PINCTRL_LPASS_LPI
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 7a12e8c..8bc877e 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index 2f19ab4..bcc12f6 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -4,237 +4,16 @@
> * Copyright (c) 2020 Linaro Ltd.
> */
>
> -#include <linux/bitops.h>
> -#include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/gpio/driver.h>
> -#include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> -#include <linux/of.h>
> #include <linux/pinctrl/pinconf-generic.h>
> #include <linux/pinctrl/pinconf.h>
> #include <linux/pinctrl/pinmux.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -#include <linux/types.h>
> #include "../core.h"
> #include "../pinctrl-utils.h"
> -
> -#define LPI_SLEW_RATE_CTL_REG 0xa000
> -#define LPI_TLMM_REG_OFFSET 0x1000
> -#define LPI_SLEW_RATE_MAX 0x03
> -#define LPI_SLEW_BITS_SIZE 0x02
> -#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> -#define LPI_GPIO_CFG_REG 0x00
> -#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> -#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> -#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> -#define LPI_GPIO_OE_MASK BIT(9)
> -#define LPI_GPIO_VALUE_REG 0x04
> -#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> -#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> -
> -#define LPI_GPIO_BIAS_DISABLE 0x0
> -#define LPI_GPIO_PULL_DOWN 0x1
> -#define LPI_GPIO_KEEPER 0x2
> -#define LPI_GPIO_PULL_UP 0x3
> -#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
> -#define NO_SLEW -1
> -
> -#define LPI_FUNCTION(fname) \
> - [LPI_MUX_##fname] = { \
> - .name = #fname, \
> - .groups = fname##_groups, \
> - .ngroups = ARRAY_SIZE(fname##_groups), \
> - }
> -
> -#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> - { \
> - .name = "gpio" #id, \
> - .pins = gpio##id##_pins, \
> - .pin = id, \
> - .slew_offset = soff, \
> - .npins = ARRAY_SIZE(gpio##id##_pins), \
> - .funcs = (int[]){ \
> - LPI_MUX_gpio, \
> - LPI_MUX_##f1, \
> - LPI_MUX_##f2, \
> - LPI_MUX_##f3, \
> - LPI_MUX_##f4, \
> - }, \
> - .nfuncs = 5, \
> - }
> -
> -struct lpi_pingroup {
> - const char *name;
> - const unsigned int *pins;
> - unsigned int npins;
> - unsigned int pin;
> - /* Bit offset in slew register for SoundWire pins only */
> - int slew_offset;
> - unsigned int *funcs;
> - unsigned int nfuncs;
> -};
> -
> -struct lpi_function {
> - const char *name;
> - const char * const *groups;
> - unsigned int ngroups;
> -};
> -
> -struct lpi_pinctrl_variant_data {
> - const struct pinctrl_pin_desc *pins;
> - int npins;
> - const struct lpi_pingroup *groups;
> - int ngroups;
> - const struct lpi_function *functions;
> - int nfunctions;
> -};
> -
> -#define MAX_LPI_NUM_CLKS 2
> -
> -struct lpi_pinctrl {
> - struct device *dev;
> - struct pinctrl_dev *ctrl;
> - struct gpio_chip chip;
> - struct pinctrl_desc desc;
> - char __iomem *tlmm_base;
> - char __iomem *slew_base;
> - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
> - struct mutex slew_access_lock;
> - const struct lpi_pinctrl_variant_data *data;
> -};
> -
> -/* sm8250 variant specific data */
> -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
> - PINCTRL_PIN(0, "gpio0"),
> - PINCTRL_PIN(1, "gpio1"),
> - PINCTRL_PIN(2, "gpio2"),
> - PINCTRL_PIN(3, "gpio3"),
> - PINCTRL_PIN(4, "gpio4"),
> - PINCTRL_PIN(5, "gpio5"),
> - PINCTRL_PIN(6, "gpio6"),
> - PINCTRL_PIN(7, "gpio7"),
> - PINCTRL_PIN(8, "gpio8"),
> - PINCTRL_PIN(9, "gpio9"),
> - PINCTRL_PIN(10, "gpio10"),
> - PINCTRL_PIN(11, "gpio11"),
> - PINCTRL_PIN(12, "gpio12"),
> - PINCTRL_PIN(13, "gpio13"),
> -};
> -
> -enum sm8250_lpi_functions {
> - LPI_MUX_dmic1_clk,
> - LPI_MUX_dmic1_data,
> - LPI_MUX_dmic2_clk,
> - LPI_MUX_dmic2_data,
> - LPI_MUX_dmic3_clk,
> - LPI_MUX_dmic3_data,
> - LPI_MUX_i2s1_clk,
> - LPI_MUX_i2s1_data,
> - LPI_MUX_i2s1_ws,
> - LPI_MUX_i2s2_clk,
> - LPI_MUX_i2s2_data,
> - LPI_MUX_i2s2_ws,
> - LPI_MUX_qua_mi2s_data,
> - LPI_MUX_qua_mi2s_sclk,
> - LPI_MUX_qua_mi2s_ws,
> - LPI_MUX_swr_rx_clk,
> - LPI_MUX_swr_rx_data,
> - LPI_MUX_swr_tx_clk,
> - LPI_MUX_swr_tx_data,
> - LPI_MUX_wsa_swr_clk,
> - LPI_MUX_wsa_swr_data,
> - LPI_MUX_gpio,
> - LPI_MUX__,
> -};
> -
> -static const unsigned int gpio0_pins[] = { 0 };
> -static const unsigned int gpio1_pins[] = { 1 };
> -static const unsigned int gpio2_pins[] = { 2 };
> -static const unsigned int gpio3_pins[] = { 3 };
> -static const unsigned int gpio4_pins[] = { 4 };
> -static const unsigned int gpio5_pins[] = { 5 };
> -static const unsigned int gpio6_pins[] = { 6 };
> -static const unsigned int gpio7_pins[] = { 7 };
> -static const unsigned int gpio8_pins[] = { 8 };
> -static const unsigned int gpio9_pins[] = { 9 };
> -static const unsigned int gpio10_pins[] = { 10 };
> -static const unsigned int gpio11_pins[] = { 11 };
> -static const unsigned int gpio12_pins[] = { 12 };
> -static const unsigned int gpio13_pins[] = { 13 };
> -static const char * const swr_tx_clk_groups[] = { "gpio0" };
> -static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
> -static const char * const swr_rx_clk_groups[] = { "gpio3" };
> -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> -static const char * const dmic1_clk_groups[] = { "gpio6" };
> -static const char * const dmic1_data_groups[] = { "gpio7" };
> -static const char * const dmic2_clk_groups[] = { "gpio8" };
> -static const char * const dmic2_data_groups[] = { "gpio9" };
> -static const char * const i2s2_clk_groups[] = { "gpio10" };
> -static const char * const i2s2_ws_groups[] = { "gpio11" };
> -static const char * const dmic3_clk_groups[] = { "gpio12" };
> -static const char * const dmic3_data_groups[] = { "gpio13" };
> -static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> -static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> -static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> -static const char * const i2s1_clk_groups[] = { "gpio6" };
> -static const char * const i2s1_ws_groups[] = { "gpio7" };
> -static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> -static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> -static const char * const wsa_swr_data_groups[] = { "gpio11" };
> -static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
> -
> -static const struct lpi_pingroup sm8250_groups[] = {
> - LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> - LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> - LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> - LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> - LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> - LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
> - LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> - LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> - LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> - LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> - LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> - LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> - LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> - LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> -};
> -
> -static const struct lpi_function sm8250_functions[] = {
> - LPI_FUNCTION(dmic1_clk),
> - LPI_FUNCTION(dmic1_data),
> - LPI_FUNCTION(dmic2_clk),
> - LPI_FUNCTION(dmic2_data),
> - LPI_FUNCTION(dmic3_clk),
> - LPI_FUNCTION(dmic3_data),
> - LPI_FUNCTION(i2s1_clk),
> - LPI_FUNCTION(i2s1_data),
> - LPI_FUNCTION(i2s1_ws),
> - LPI_FUNCTION(i2s2_clk),
> - LPI_FUNCTION(i2s2_data),
> - LPI_FUNCTION(i2s2_ws),
> - LPI_FUNCTION(qua_mi2s_data),
> - LPI_FUNCTION(qua_mi2s_sclk),
> - LPI_FUNCTION(qua_mi2s_ws),
> - LPI_FUNCTION(swr_rx_clk),
> - LPI_FUNCTION(swr_rx_data),
> - LPI_FUNCTION(swr_tx_clk),
> - LPI_FUNCTION(swr_tx_data),
> - LPI_FUNCTION(wsa_swr_clk),
> - LPI_FUNCTION(wsa_swr_data),
> -};
> -
> -static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
> - .pins = sm8250_lpi_pins,
> - .npins = ARRAY_SIZE(sm8250_lpi_pins),
> - .groups = sm8250_groups,
> - .ngroups = ARRAY_SIZE(sm8250_groups),
> - .functions = sm8250_functions,
> - .nfunctions = ARRAY_SIZE(sm8250_functions),
> -};
> +#include "pinctrl-lpass-lpi.h"
>
> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
> unsigned int addr)
> @@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
> .dbg_show = lpi_gpio_dbg_show,
> };
>
> -static int lpi_pinctrl_probe(struct platform_device *pdev)
> +int lpi_pinctrl_probe(struct platform_device *pdev)
> {
> const struct lpi_pinctrl_variant_data *data;
> struct device *dev = &pdev->dev;
> @@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
>
> return ret;
> }
> +EXPORT_SYMBOL(lpi_pinctrl_probe);
>
> -static int lpi_pinctrl_remove(struct platform_device *pdev)
> +
> +int lpi_pinctrl_remove(struct platform_device *pdev)
> {
> struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
>
> @@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
>
> return 0;
> }
> +EXPORT_SYMBOL(lpi_pinctrl_remove);
>
> -static const struct of_device_id lpi_pinctrl_of_match[] = {
> - {
> - .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
> - .data = &sm8250_lpi_data,
> - },
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> -
> -static struct platform_driver lpi_pinctrl_driver = {
> - .driver = {
> - .name = "qcom-lpass-lpi-pinctrl",
> - .of_match_table = lpi_pinctrl_of_match,
> - },
> - .probe = lpi_pinctrl_probe,
> - .remove = lpi_pinctrl_remove,
> -};
> -
> -module_platform_driver(lpi_pinctrl_driver);
> MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
> MODULE_LICENSE("GPL");
> +
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> new file mode 100644
> index 0000000..ad84565
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +#ifndef __PINCTRL_LPASS_LPI_H__
> +#define __PINCTRL_LPASS_LPI_H__
> +
> +#define LPI_SLEW_RATE_CTL_REG 0xa000
> +#define LPI_TLMM_REG_OFFSET 0x1000
> +#define LPI_SLEW_RATE_MAX 0x03
> +#define LPI_SLEW_BITS_SIZE 0x02
> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> +#define LPI_GPIO_CFG_REG 0x00
> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> +#define LPI_GPIO_OE_MASK BIT(9)
> +#define LPI_GPIO_VALUE_REG 0x04
> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> +
> +#define LPI_GPIO_BIAS_DISABLE 0x0
> +#define LPI_GPIO_PULL_DOWN 0x1
> +#define LPI_GPIO_KEEPER 0x2
> +#define LPI_GPIO_PULL_UP 0x3
> +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
> +#define NO_SLEW -1
> +
> +#define LPI_FUNCTION(fname) \
> + [LPI_MUX_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .pin = id, \
> + .slew_offset = soff, \
> + .npins = ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + LPI_MUX_gpio, \
> + LPI_MUX_##f1, \
> + LPI_MUX_##f2, \
> + LPI_MUX_##f3, \
> + LPI_MUX_##f4, \
> + }, \
> + .nfuncs = 5, \
> + }
> +
> +struct lpi_pingroup {
> + const char *name;
> + const unsigned int *pins;
> + unsigned int npins;
> + unsigned int pin;
> + /* Bit offset in slew register for SoundWire pins only */
> + int slew_offset;
> + unsigned int *funcs;
> + unsigned int nfuncs;
> +};
> +
> +struct lpi_function {
> + const char *name;
> + const char * const *groups;
> + unsigned int ngroups;
> +};
> +
> +struct lpi_pinctrl_variant_data {
> + const struct pinctrl_pin_desc *pins;
> + int npins;
> + const struct lpi_pingroup *groups;
> + int ngroups;
> + const struct lpi_function *functions;
> + int nfunctions;
> +};
> +
> +#define MAX_LPI_NUM_CLKS 2
> +
> +struct lpi_pinctrl {
Afaict this is only used by the common code, if so there's no need to
expose it in the header file.
> + struct device *dev;
> + struct pinctrl_dev *ctrl;
> + struct gpio_chip chip;
> + struct pinctrl_desc desc;
> + char __iomem *tlmm_base;
> + char __iomem *slew_base;
> + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
> + struct mutex slew_access_lock;
> + const struct lpi_pinctrl_variant_data *data;
> +};
> +
> +int lpi_pinctrl_probe(struct platform_device *pdev);
> +int lpi_pinctrl_remove(struct platform_device *pdev);
> +
> +#endif /*__PINCTRL_LPASS_LPI_H__*/
> +
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> new file mode 100644
> index 0000000..9a5db15
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> @@ -0,0 +1,166 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-lpass-lpi.h"
> +
> +enum lpass_lpi_functions {
> + LPI_MUX_dmic1_clk,
> + LPI_MUX_dmic1_data,
> + LPI_MUX_dmic2_clk,
> + LPI_MUX_dmic2_data,
> + LPI_MUX_dmic3_clk,
> + LPI_MUX_dmic3_data,
> + LPI_MUX_i2s1_clk,
> + LPI_MUX_i2s1_data,
> + LPI_MUX_i2s1_ws,
> + LPI_MUX_i2s2_clk,
> + LPI_MUX_i2s2_data,
> + LPI_MUX_i2s2_ws,
> + LPI_MUX_qua_mi2s_data,
> + LPI_MUX_qua_mi2s_sclk,
> + LPI_MUX_qua_mi2s_ws,
> + LPI_MUX_swr_rx_clk,
> + LPI_MUX_swr_rx_data,
> + LPI_MUX_swr_tx_clk,
> + LPI_MUX_swr_tx_data,
> + LPI_MUX_wsa_swr_clk,
> + LPI_MUX_wsa_swr_data,
> + LPI_MUX_gpio,
> + LPI_MUX__,
> +};
> +
> +static const unsigned int gpio0_pins[] = { 0 };
> +static const unsigned int gpio1_pins[] = { 1 };
> +static const unsigned int gpio2_pins[] = { 2 };
> +static const unsigned int gpio3_pins[] = { 3 };
> +static const unsigned int gpio4_pins[] = { 4 };
> +static const unsigned int gpio5_pins[] = { 5 };
> +static const unsigned int gpio6_pins[] = { 6 };
> +static const unsigned int gpio7_pins[] = { 7 };
> +static const unsigned int gpio8_pins[] = { 8 };
> +static const unsigned int gpio9_pins[] = { 9 };
> +static const unsigned int gpio10_pins[] = { 10 };
> +static const unsigned int gpio11_pins[] = { 11 };
> +static const unsigned int gpio12_pins[] = { 12 };
> +static const unsigned int gpio13_pins[] = { 13 };
> +
> +/* sm8250 variant specific data */
> +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
> + PINCTRL_PIN(0, "gpio0"),
> + PINCTRL_PIN(1, "gpio1"),
> + PINCTRL_PIN(2, "gpio2"),
> + PINCTRL_PIN(3, "gpio3"),
> + PINCTRL_PIN(4, "gpio4"),
> + PINCTRL_PIN(5, "gpio5"),
> + PINCTRL_PIN(6, "gpio6"),
> + PINCTRL_PIN(7, "gpio7"),
> + PINCTRL_PIN(8, "gpio8"),
> + PINCTRL_PIN(9, "gpio9"),
> + PINCTRL_PIN(10, "gpio10"),
> + PINCTRL_PIN(11, "gpio11"),
> + PINCTRL_PIN(12, "gpio12"),
> + PINCTRL_PIN(13, "gpio13"),
> +};
> +
> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> +static const char * const dmic1_clk_groups[] = { "gpio6" };
> +static const char * const dmic1_data_groups[] = { "gpio7" };
> +static const char * const dmic2_clk_groups[] = { "gpio8" };
> +static const char * const dmic2_data_groups[] = { "gpio9" };
> +static const char * const i2s2_clk_groups[] = { "gpio10" };
> +static const char * const i2s2_ws_groups[] = { "gpio11" };
> +static const char * const dmic3_clk_groups[] = { "gpio12" };
> +static const char * const dmic3_data_groups[] = { "gpio13" };
> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> +static const char * const i2s1_clk_groups[] = { "gpio6" };
> +static const char * const i2s1_ws_groups[] = { "gpio7" };
> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
> +
> +static const struct lpi_pingroup sm8250_groups[] = {
> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> +};
> +
> +static const struct lpi_function sm8250_functions[] = {
> + LPI_FUNCTION(dmic1_clk),
> + LPI_FUNCTION(dmic1_data),
> + LPI_FUNCTION(dmic2_clk),
> + LPI_FUNCTION(dmic2_data),
> + LPI_FUNCTION(dmic3_clk),
> + LPI_FUNCTION(dmic3_data),
> + LPI_FUNCTION(i2s1_clk),
> + LPI_FUNCTION(i2s1_data),
> + LPI_FUNCTION(i2s1_ws),
> + LPI_FUNCTION(i2s2_clk),
> + LPI_FUNCTION(i2s2_data),
> + LPI_FUNCTION(i2s2_ws),
> + LPI_FUNCTION(qua_mi2s_data),
> + LPI_FUNCTION(qua_mi2s_sclk),
> + LPI_FUNCTION(qua_mi2s_ws),
> + LPI_FUNCTION(swr_rx_clk),
> + LPI_FUNCTION(swr_rx_data),
> + LPI_FUNCTION(swr_tx_clk),
> + LPI_FUNCTION(swr_tx_data),
> + LPI_FUNCTION(wsa_swr_clk),
> + LPI_FUNCTION(wsa_swr_data),
> +};
> +
> +static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
> + .pins = sm8250_lpi_pins,
> + .npins = ARRAY_SIZE(sm8250_lpi_pins),
> + .groups = sm8250_groups,
> + .ngroups = ARRAY_SIZE(sm8250_groups),
> + .functions = sm8250_functions,
> + .nfunctions = ARRAY_SIZE(sm8250_functions),
> +};
> +
> +static const struct of_device_id lpi_pinctrl_of_match[] = {
> + {
> + .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
> + .data = &sm8250_lpi_data,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> +
> +static struct platform_driver lpi_pinctrl_driver = {
> + .driver = {
> + .name = "qcom-sm8250-lpass-lpi-pinctrl",
> + .of_match_table = lpi_pinctrl_of_match,
> + },
> + .probe = lpi_pinctrl_probe,
> + .remove = lpi_pinctrl_remove,
> +};
> +
> +module_platform_driver(lpi_pinctrl_driver);
> +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
> +MODULE_LICENSE("GPL");
> +
Unnecessary empty line.
Thanks,
Bjorn
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
@ 2021-12-06 16:32 ` Bjorn Andersson
0 siblings, 0 replies; 28+ messages in thread
From: Bjorn Andersson @ 2021-12-06 16:32 UTC (permalink / raw)
To: Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Srinivasa Rao Mandadapu,
Venkata Prasad Potturu, linux-arm-msm, plai, tiwai, agross,
robh+dt, lgirdwood, linux-gpio, broonie, rohitkr, swboyd,
judyhsiao, Linus Walleij, linux-kernel
On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
I don't see anything _wrong_ with the current filename, so this patch
isn't really moving chip function to the _right_ files.
May I suggest that you make $subject:
"pinctrl: qcom: Extract chip specific LPASS LPI code"
> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>
> Update lpass lpi pin control driver to accommodate new lpass variant
> SoC specific drivers.
I also have a hard time parsing this sentence.
> Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
> and common declarations to pinctrl-lpass-lpi.h header file.
How about simply:
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
> ---
> drivers/pinctrl/qcom/Kconfig | 8 +
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
> drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
> 5 files changed, 280 insertions(+), 243 deletions(-)
> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 5ff4207..e750e10 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>
> +config PINCTRL_SM8250_LPASS_LPI
> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
> + depends on PINCTRL_LPASS_LPI
> + help
> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
> + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
> +
> endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 7a12e8c..8bc877e 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
> +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index 2f19ab4..bcc12f6 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -4,237 +4,16 @@
> * Copyright (c) 2020 Linaro Ltd.
> */
>
> -#include <linux/bitops.h>
> -#include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/gpio/driver.h>
> -#include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> -#include <linux/of.h>
> #include <linux/pinctrl/pinconf-generic.h>
> #include <linux/pinctrl/pinconf.h>
> #include <linux/pinctrl/pinmux.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -#include <linux/types.h>
> #include "../core.h"
> #include "../pinctrl-utils.h"
> -
> -#define LPI_SLEW_RATE_CTL_REG 0xa000
> -#define LPI_TLMM_REG_OFFSET 0x1000
> -#define LPI_SLEW_RATE_MAX 0x03
> -#define LPI_SLEW_BITS_SIZE 0x02
> -#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> -#define LPI_GPIO_CFG_REG 0x00
> -#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> -#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> -#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> -#define LPI_GPIO_OE_MASK BIT(9)
> -#define LPI_GPIO_VALUE_REG 0x04
> -#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> -#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> -
> -#define LPI_GPIO_BIAS_DISABLE 0x0
> -#define LPI_GPIO_PULL_DOWN 0x1
> -#define LPI_GPIO_KEEPER 0x2
> -#define LPI_GPIO_PULL_UP 0x3
> -#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
> -#define NO_SLEW -1
> -
> -#define LPI_FUNCTION(fname) \
> - [LPI_MUX_##fname] = { \
> - .name = #fname, \
> - .groups = fname##_groups, \
> - .ngroups = ARRAY_SIZE(fname##_groups), \
> - }
> -
> -#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> - { \
> - .name = "gpio" #id, \
> - .pins = gpio##id##_pins, \
> - .pin = id, \
> - .slew_offset = soff, \
> - .npins = ARRAY_SIZE(gpio##id##_pins), \
> - .funcs = (int[]){ \
> - LPI_MUX_gpio, \
> - LPI_MUX_##f1, \
> - LPI_MUX_##f2, \
> - LPI_MUX_##f3, \
> - LPI_MUX_##f4, \
> - }, \
> - .nfuncs = 5, \
> - }
> -
> -struct lpi_pingroup {
> - const char *name;
> - const unsigned int *pins;
> - unsigned int npins;
> - unsigned int pin;
> - /* Bit offset in slew register for SoundWire pins only */
> - int slew_offset;
> - unsigned int *funcs;
> - unsigned int nfuncs;
> -};
> -
> -struct lpi_function {
> - const char *name;
> - const char * const *groups;
> - unsigned int ngroups;
> -};
> -
> -struct lpi_pinctrl_variant_data {
> - const struct pinctrl_pin_desc *pins;
> - int npins;
> - const struct lpi_pingroup *groups;
> - int ngroups;
> - const struct lpi_function *functions;
> - int nfunctions;
> -};
> -
> -#define MAX_LPI_NUM_CLKS 2
> -
> -struct lpi_pinctrl {
> - struct device *dev;
> - struct pinctrl_dev *ctrl;
> - struct gpio_chip chip;
> - struct pinctrl_desc desc;
> - char __iomem *tlmm_base;
> - char __iomem *slew_base;
> - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
> - struct mutex slew_access_lock;
> - const struct lpi_pinctrl_variant_data *data;
> -};
> -
> -/* sm8250 variant specific data */
> -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
> - PINCTRL_PIN(0, "gpio0"),
> - PINCTRL_PIN(1, "gpio1"),
> - PINCTRL_PIN(2, "gpio2"),
> - PINCTRL_PIN(3, "gpio3"),
> - PINCTRL_PIN(4, "gpio4"),
> - PINCTRL_PIN(5, "gpio5"),
> - PINCTRL_PIN(6, "gpio6"),
> - PINCTRL_PIN(7, "gpio7"),
> - PINCTRL_PIN(8, "gpio8"),
> - PINCTRL_PIN(9, "gpio9"),
> - PINCTRL_PIN(10, "gpio10"),
> - PINCTRL_PIN(11, "gpio11"),
> - PINCTRL_PIN(12, "gpio12"),
> - PINCTRL_PIN(13, "gpio13"),
> -};
> -
> -enum sm8250_lpi_functions {
> - LPI_MUX_dmic1_clk,
> - LPI_MUX_dmic1_data,
> - LPI_MUX_dmic2_clk,
> - LPI_MUX_dmic2_data,
> - LPI_MUX_dmic3_clk,
> - LPI_MUX_dmic3_data,
> - LPI_MUX_i2s1_clk,
> - LPI_MUX_i2s1_data,
> - LPI_MUX_i2s1_ws,
> - LPI_MUX_i2s2_clk,
> - LPI_MUX_i2s2_data,
> - LPI_MUX_i2s2_ws,
> - LPI_MUX_qua_mi2s_data,
> - LPI_MUX_qua_mi2s_sclk,
> - LPI_MUX_qua_mi2s_ws,
> - LPI_MUX_swr_rx_clk,
> - LPI_MUX_swr_rx_data,
> - LPI_MUX_swr_tx_clk,
> - LPI_MUX_swr_tx_data,
> - LPI_MUX_wsa_swr_clk,
> - LPI_MUX_wsa_swr_data,
> - LPI_MUX_gpio,
> - LPI_MUX__,
> -};
> -
> -static const unsigned int gpio0_pins[] = { 0 };
> -static const unsigned int gpio1_pins[] = { 1 };
> -static const unsigned int gpio2_pins[] = { 2 };
> -static const unsigned int gpio3_pins[] = { 3 };
> -static const unsigned int gpio4_pins[] = { 4 };
> -static const unsigned int gpio5_pins[] = { 5 };
> -static const unsigned int gpio6_pins[] = { 6 };
> -static const unsigned int gpio7_pins[] = { 7 };
> -static const unsigned int gpio8_pins[] = { 8 };
> -static const unsigned int gpio9_pins[] = { 9 };
> -static const unsigned int gpio10_pins[] = { 10 };
> -static const unsigned int gpio11_pins[] = { 11 };
> -static const unsigned int gpio12_pins[] = { 12 };
> -static const unsigned int gpio13_pins[] = { 13 };
> -static const char * const swr_tx_clk_groups[] = { "gpio0" };
> -static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
> -static const char * const swr_rx_clk_groups[] = { "gpio3" };
> -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> -static const char * const dmic1_clk_groups[] = { "gpio6" };
> -static const char * const dmic1_data_groups[] = { "gpio7" };
> -static const char * const dmic2_clk_groups[] = { "gpio8" };
> -static const char * const dmic2_data_groups[] = { "gpio9" };
> -static const char * const i2s2_clk_groups[] = { "gpio10" };
> -static const char * const i2s2_ws_groups[] = { "gpio11" };
> -static const char * const dmic3_clk_groups[] = { "gpio12" };
> -static const char * const dmic3_data_groups[] = { "gpio13" };
> -static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> -static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> -static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> -static const char * const i2s1_clk_groups[] = { "gpio6" };
> -static const char * const i2s1_ws_groups[] = { "gpio7" };
> -static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> -static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> -static const char * const wsa_swr_data_groups[] = { "gpio11" };
> -static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
> -
> -static const struct lpi_pingroup sm8250_groups[] = {
> - LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> - LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> - LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> - LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> - LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> - LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
> - LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> - LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> - LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> - LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> - LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> - LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> - LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> - LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> -};
> -
> -static const struct lpi_function sm8250_functions[] = {
> - LPI_FUNCTION(dmic1_clk),
> - LPI_FUNCTION(dmic1_data),
> - LPI_FUNCTION(dmic2_clk),
> - LPI_FUNCTION(dmic2_data),
> - LPI_FUNCTION(dmic3_clk),
> - LPI_FUNCTION(dmic3_data),
> - LPI_FUNCTION(i2s1_clk),
> - LPI_FUNCTION(i2s1_data),
> - LPI_FUNCTION(i2s1_ws),
> - LPI_FUNCTION(i2s2_clk),
> - LPI_FUNCTION(i2s2_data),
> - LPI_FUNCTION(i2s2_ws),
> - LPI_FUNCTION(qua_mi2s_data),
> - LPI_FUNCTION(qua_mi2s_sclk),
> - LPI_FUNCTION(qua_mi2s_ws),
> - LPI_FUNCTION(swr_rx_clk),
> - LPI_FUNCTION(swr_rx_data),
> - LPI_FUNCTION(swr_tx_clk),
> - LPI_FUNCTION(swr_tx_data),
> - LPI_FUNCTION(wsa_swr_clk),
> - LPI_FUNCTION(wsa_swr_data),
> -};
> -
> -static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
> - .pins = sm8250_lpi_pins,
> - .npins = ARRAY_SIZE(sm8250_lpi_pins),
> - .groups = sm8250_groups,
> - .ngroups = ARRAY_SIZE(sm8250_groups),
> - .functions = sm8250_functions,
> - .nfunctions = ARRAY_SIZE(sm8250_functions),
> -};
> +#include "pinctrl-lpass-lpi.h"
>
> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
> unsigned int addr)
> @@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
> .dbg_show = lpi_gpio_dbg_show,
> };
>
> -static int lpi_pinctrl_probe(struct platform_device *pdev)
> +int lpi_pinctrl_probe(struct platform_device *pdev)
> {
> const struct lpi_pinctrl_variant_data *data;
> struct device *dev = &pdev->dev;
> @@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
>
> return ret;
> }
> +EXPORT_SYMBOL(lpi_pinctrl_probe);
>
> -static int lpi_pinctrl_remove(struct platform_device *pdev)
> +
> +int lpi_pinctrl_remove(struct platform_device *pdev)
> {
> struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
>
> @@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
>
> return 0;
> }
> +EXPORT_SYMBOL(lpi_pinctrl_remove);
>
> -static const struct of_device_id lpi_pinctrl_of_match[] = {
> - {
> - .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
> - .data = &sm8250_lpi_data,
> - },
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> -
> -static struct platform_driver lpi_pinctrl_driver = {
> - .driver = {
> - .name = "qcom-lpass-lpi-pinctrl",
> - .of_match_table = lpi_pinctrl_of_match,
> - },
> - .probe = lpi_pinctrl_probe,
> - .remove = lpi_pinctrl_remove,
> -};
> -
> -module_platform_driver(lpi_pinctrl_driver);
> MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
> MODULE_LICENSE("GPL");
> +
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> new file mode 100644
> index 0000000..ad84565
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +#ifndef __PINCTRL_LPASS_LPI_H__
> +#define __PINCTRL_LPASS_LPI_H__
> +
> +#define LPI_SLEW_RATE_CTL_REG 0xa000
> +#define LPI_TLMM_REG_OFFSET 0x1000
> +#define LPI_SLEW_RATE_MAX 0x03
> +#define LPI_SLEW_BITS_SIZE 0x02
> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
> +#define LPI_GPIO_CFG_REG 0x00
> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
> +#define LPI_GPIO_OE_MASK BIT(9)
> +#define LPI_GPIO_VALUE_REG 0x04
> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
> +
> +#define LPI_GPIO_BIAS_DISABLE 0x0
> +#define LPI_GPIO_PULL_DOWN 0x1
> +#define LPI_GPIO_KEEPER 0x2
> +#define LPI_GPIO_PULL_UP 0x3
> +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
> +#define NO_SLEW -1
> +
> +#define LPI_FUNCTION(fname) \
> + [LPI_MUX_##fname] = { \
> + .name = #fname, \
> + .groups = fname##_groups, \
> + .ngroups = ARRAY_SIZE(fname##_groups), \
> + }
> +
> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
> + { \
> + .name = "gpio" #id, \
> + .pins = gpio##id##_pins, \
> + .pin = id, \
> + .slew_offset = soff, \
> + .npins = ARRAY_SIZE(gpio##id##_pins), \
> + .funcs = (int[]){ \
> + LPI_MUX_gpio, \
> + LPI_MUX_##f1, \
> + LPI_MUX_##f2, \
> + LPI_MUX_##f3, \
> + LPI_MUX_##f4, \
> + }, \
> + .nfuncs = 5, \
> + }
> +
> +struct lpi_pingroup {
> + const char *name;
> + const unsigned int *pins;
> + unsigned int npins;
> + unsigned int pin;
> + /* Bit offset in slew register for SoundWire pins only */
> + int slew_offset;
> + unsigned int *funcs;
> + unsigned int nfuncs;
> +};
> +
> +struct lpi_function {
> + const char *name;
> + const char * const *groups;
> + unsigned int ngroups;
> +};
> +
> +struct lpi_pinctrl_variant_data {
> + const struct pinctrl_pin_desc *pins;
> + int npins;
> + const struct lpi_pingroup *groups;
> + int ngroups;
> + const struct lpi_function *functions;
> + int nfunctions;
> +};
> +
> +#define MAX_LPI_NUM_CLKS 2
> +
> +struct lpi_pinctrl {
Afaict this is only used by the common code, if so there's no need to
expose it in the header file.
> + struct device *dev;
> + struct pinctrl_dev *ctrl;
> + struct gpio_chip chip;
> + struct pinctrl_desc desc;
> + char __iomem *tlmm_base;
> + char __iomem *slew_base;
> + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
> + struct mutex slew_access_lock;
> + const struct lpi_pinctrl_variant_data *data;
> +};
> +
> +int lpi_pinctrl_probe(struct platform_device *pdev);
> +int lpi_pinctrl_remove(struct platform_device *pdev);
> +
> +#endif /*__PINCTRL_LPASS_LPI_H__*/
> +
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> new file mode 100644
> index 0000000..9a5db15
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> @@ -0,0 +1,166 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020 Linaro Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include "pinctrl-lpass-lpi.h"
> +
> +enum lpass_lpi_functions {
> + LPI_MUX_dmic1_clk,
> + LPI_MUX_dmic1_data,
> + LPI_MUX_dmic2_clk,
> + LPI_MUX_dmic2_data,
> + LPI_MUX_dmic3_clk,
> + LPI_MUX_dmic3_data,
> + LPI_MUX_i2s1_clk,
> + LPI_MUX_i2s1_data,
> + LPI_MUX_i2s1_ws,
> + LPI_MUX_i2s2_clk,
> + LPI_MUX_i2s2_data,
> + LPI_MUX_i2s2_ws,
> + LPI_MUX_qua_mi2s_data,
> + LPI_MUX_qua_mi2s_sclk,
> + LPI_MUX_qua_mi2s_ws,
> + LPI_MUX_swr_rx_clk,
> + LPI_MUX_swr_rx_data,
> + LPI_MUX_swr_tx_clk,
> + LPI_MUX_swr_tx_data,
> + LPI_MUX_wsa_swr_clk,
> + LPI_MUX_wsa_swr_data,
> + LPI_MUX_gpio,
> + LPI_MUX__,
> +};
> +
> +static const unsigned int gpio0_pins[] = { 0 };
> +static const unsigned int gpio1_pins[] = { 1 };
> +static const unsigned int gpio2_pins[] = { 2 };
> +static const unsigned int gpio3_pins[] = { 3 };
> +static const unsigned int gpio4_pins[] = { 4 };
> +static const unsigned int gpio5_pins[] = { 5 };
> +static const unsigned int gpio6_pins[] = { 6 };
> +static const unsigned int gpio7_pins[] = { 7 };
> +static const unsigned int gpio8_pins[] = { 8 };
> +static const unsigned int gpio9_pins[] = { 9 };
> +static const unsigned int gpio10_pins[] = { 10 };
> +static const unsigned int gpio11_pins[] = { 11 };
> +static const unsigned int gpio12_pins[] = { 12 };
> +static const unsigned int gpio13_pins[] = { 13 };
> +
> +/* sm8250 variant specific data */
> +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
> + PINCTRL_PIN(0, "gpio0"),
> + PINCTRL_PIN(1, "gpio1"),
> + PINCTRL_PIN(2, "gpio2"),
> + PINCTRL_PIN(3, "gpio3"),
> + PINCTRL_PIN(4, "gpio4"),
> + PINCTRL_PIN(5, "gpio5"),
> + PINCTRL_PIN(6, "gpio6"),
> + PINCTRL_PIN(7, "gpio7"),
> + PINCTRL_PIN(8, "gpio8"),
> + PINCTRL_PIN(9, "gpio9"),
> + PINCTRL_PIN(10, "gpio10"),
> + PINCTRL_PIN(11, "gpio11"),
> + PINCTRL_PIN(12, "gpio12"),
> + PINCTRL_PIN(13, "gpio13"),
> +};
> +
> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
> +static const char * const dmic1_clk_groups[] = { "gpio6" };
> +static const char * const dmic1_data_groups[] = { "gpio7" };
> +static const char * const dmic2_clk_groups[] = { "gpio8" };
> +static const char * const dmic2_data_groups[] = { "gpio9" };
> +static const char * const i2s2_clk_groups[] = { "gpio10" };
> +static const char * const i2s2_ws_groups[] = { "gpio11" };
> +static const char * const dmic3_clk_groups[] = { "gpio12" };
> +static const char * const dmic3_data_groups[] = { "gpio13" };
> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
> +static const char * const i2s1_clk_groups[] = { "gpio6" };
> +static const char * const i2s1_ws_groups[] = { "gpio7" };
> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
> +
> +static const struct lpi_pingroup sm8250_groups[] = {
> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
> + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
> +};
> +
> +static const struct lpi_function sm8250_functions[] = {
> + LPI_FUNCTION(dmic1_clk),
> + LPI_FUNCTION(dmic1_data),
> + LPI_FUNCTION(dmic2_clk),
> + LPI_FUNCTION(dmic2_data),
> + LPI_FUNCTION(dmic3_clk),
> + LPI_FUNCTION(dmic3_data),
> + LPI_FUNCTION(i2s1_clk),
> + LPI_FUNCTION(i2s1_data),
> + LPI_FUNCTION(i2s1_ws),
> + LPI_FUNCTION(i2s2_clk),
> + LPI_FUNCTION(i2s2_data),
> + LPI_FUNCTION(i2s2_ws),
> + LPI_FUNCTION(qua_mi2s_data),
> + LPI_FUNCTION(qua_mi2s_sclk),
> + LPI_FUNCTION(qua_mi2s_ws),
> + LPI_FUNCTION(swr_rx_clk),
> + LPI_FUNCTION(swr_rx_data),
> + LPI_FUNCTION(swr_tx_clk),
> + LPI_FUNCTION(swr_tx_data),
> + LPI_FUNCTION(wsa_swr_clk),
> + LPI_FUNCTION(wsa_swr_data),
> +};
> +
> +static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
> + .pins = sm8250_lpi_pins,
> + .npins = ARRAY_SIZE(sm8250_lpi_pins),
> + .groups = sm8250_groups,
> + .ngroups = ARRAY_SIZE(sm8250_groups),
> + .functions = sm8250_functions,
> + .nfunctions = ARRAY_SIZE(sm8250_functions),
> +};
> +
> +static const struct of_device_id lpi_pinctrl_of_match[] = {
> + {
> + .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
> + .data = &sm8250_lpi_data,
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
> +
> +static struct platform_driver lpi_pinctrl_driver = {
> + .driver = {
> + .name = "qcom-sm8250-lpass-lpi-pinctrl",
> + .of_match_table = lpi_pinctrl_of_match,
> + },
> + .probe = lpi_pinctrl_probe,
> + .remove = lpi_pinctrl_remove,
> +};
> +
> +module_platform_driver(lpi_pinctrl_driver);
> +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
> +MODULE_LICENSE("GPL");
> +
Unnecessary empty line.
Thanks,
Bjorn
> --
> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
2021-12-06 2:35 ` Bjorn Andersson
@ 2021-12-07 15:16 ` Srinivasa Rao Mandadapu
-1 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:16 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Venkata Prasad Potturu
On 12/6/2021 8:05 AM, Bjorn Andersson wrote:
Thanks for Your Time Bjorn!!!
> On Fri 03 Dec 03:32 PST 2021, Srinivasa Rao Mandadapu wrote:
>
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Update bulk clock voting to optional voting as ADSP bypass platform doesn't
>> need macro and decodec clocks, these are maintained as power domains and
>> operated from lpass audio core cc.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index bcc12f6..c2a1110 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
>> return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
>> "Slew resource not provided\n");
>>
>> - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
>> + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
> If some platforms requires this clock and others doesn't have one, then
> please make this statement conditional on the compatible, rather than
> making it optional on both.
>
> Thanks,
> Bjorn
Okay. will add one flag in lpi_pinctrl_variant_data structure and handle
it accordingly.
>> if (ret)
>> return dev_err_probe(dev, ret, "Can't get clocks\n");
>>
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional
@ 2021-12-07 15:16 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:16 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Venkata Prasad Potturu,
linux-arm-msm, plai, tiwai, agross, robh+dt, lgirdwood,
linux-gpio, broonie, rohitkr, swboyd, judyhsiao, Linus Walleij,
linux-kernel
On 12/6/2021 8:05 AM, Bjorn Andersson wrote:
Thanks for Your Time Bjorn!!!
> On Fri 03 Dec 03:32 PST 2021, Srinivasa Rao Mandadapu wrote:
>
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Update bulk clock voting to optional voting as ADSP bypass platform doesn't
>> need macro and decodec clocks, these are maintained as power domains and
>> operated from lpass audio core cc.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index bcc12f6..c2a1110 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -394,7 +394,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
>> return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
>> "Slew resource not provided\n");
>>
>> - ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
>> + ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
> If some platforms requires this clock and others doesn't have one, then
> please make this statement conditional on the compatible, rather than
> making it optional on both.
>
> Thanks,
> Bjorn
Okay. will add one flag in lpi_pinctrl_variant_data structure and handle
it accordingly.
>> if (ret)
>> return dev_err_probe(dev, ret, "Can't get clocks\n");
>>
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
2021-12-06 16:25 ` Bjorn Andersson
@ 2021-12-07 15:19 ` Srinivasa Rao Mandadapu
-1 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Venkata Prasad Potturu
On 12/6/2021 9:55 PM, Bjorn Andersson wrote:
Thanks for your time Bjorn!!
> On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
>
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Add pin control support for SC7280 LPASS LPI.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 8 ++
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
>> 3 files changed, 178 insertions(+)
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index e750e10..37fe868 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
>> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>>
>> +config PINCTRL_SC7280_LPASS_LPI
>> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
> You misspelled SC7280 here.
Okay. will address it.
>
>> + depends on PINCTRL_LPASS_LPI
>> + help
>> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
>> +
>> endif
>> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>> index 8bc877e..6c3ddaf 100644
>> --- a/drivers/pinctrl/qcom/Makefile
>> +++ b/drivers/pinctrl/qcom/Makefile
>> @@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
>> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
>> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
>> obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
>> +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
> Please keep these entries sorted alphabetically, same with Kconfig.
Okay. will address it.
>
> Regards,
> Bjorn
>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>> new file mode 100644
>> index 0000000..94bec15
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>> @@ -0,0 +1,169 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
>> + * ALSA SoC platform-machine driver for QTi LPASS
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/gpio/driver.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "pinctrl-lpass-lpi.h"
>> +
>> +enum lpass_lpi_functions {
>> + LPI_MUX_dmic1_clk,
>> + LPI_MUX_dmic1_data,
>> + LPI_MUX_dmic2_clk,
>> + LPI_MUX_dmic2_data,
>> + LPI_MUX_dmic3_clk,
>> + LPI_MUX_dmic3_data,
>> + LPI_MUX_i2s1_clk,
>> + LPI_MUX_i2s1_data,
>> + LPI_MUX_i2s1_ws,
>> + LPI_MUX_i2s2_clk,
>> + LPI_MUX_i2s2_data,
>> + LPI_MUX_i2s2_ws,
>> + LPI_MUX_qua_mi2s_data,
>> + LPI_MUX_qua_mi2s_sclk,
>> + LPI_MUX_qua_mi2s_ws,
>> + LPI_MUX_swr_rx_clk,
>> + LPI_MUX_swr_rx_data,
>> + LPI_MUX_swr_tx_clk,
>> + LPI_MUX_swr_tx_data,
>> + LPI_MUX_wsa_swr_clk,
>> + LPI_MUX_wsa_swr_data,
>> + LPI_MUX_gpio,
>> + LPI_MUX__,
>> +};
>> +
>> +static const unsigned int gpio0_pins[] = { 0 };
>> +static const unsigned int gpio1_pins[] = { 1 };
>> +static const unsigned int gpio2_pins[] = { 2 };
>> +static const unsigned int gpio3_pins[] = { 3 };
>> +static const unsigned int gpio4_pins[] = { 4 };
>> +static const unsigned int gpio5_pins[] = { 5 };
>> +static const unsigned int gpio6_pins[] = { 6 };
>> +static const unsigned int gpio7_pins[] = { 7 };
>> +static const unsigned int gpio8_pins[] = { 8 };
>> +static const unsigned int gpio9_pins[] = { 9 };
>> +static const unsigned int gpio10_pins[] = { 10 };
>> +static const unsigned int gpio11_pins[] = { 11 };
>> +static const unsigned int gpio12_pins[] = { 12 };
>> +static const unsigned int gpio13_pins[] = { 13 };
>> +static const unsigned int gpio14_pins[] = { 14 };
>> +
>> +/* sc7280 variant specific data */
>> +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
>> + PINCTRL_PIN(0, "gpio0"),
>> + PINCTRL_PIN(1, "gpio1"),
>> + PINCTRL_PIN(2, "gpio2"),
>> + PINCTRL_PIN(3, "gpio3"),
>> + PINCTRL_PIN(4, "gpio4"),
>> + PINCTRL_PIN(5, "gpio5"),
>> + PINCTRL_PIN(6, "gpio6"),
>> + PINCTRL_PIN(7, "gpio7"),
>> + PINCTRL_PIN(8, "gpio8"),
>> + PINCTRL_PIN(9, "gpio9"),
>> + PINCTRL_PIN(10, "gpio10"),
>> + PINCTRL_PIN(11, "gpio11"),
>> + PINCTRL_PIN(12, "gpio12"),
>> + PINCTRL_PIN(13, "gpio13"),
>> + PINCTRL_PIN(14, "gpio14"),
>> +};
>> +
>> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
>> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> +static const char * const dmic1_clk_groups[] = { "gpio6" };
>> +static const char * const dmic1_data_groups[] = { "gpio7" };
>> +static const char * const dmic2_clk_groups[] = { "gpio8" };
>> +static const char * const dmic2_data_groups[] = { "gpio9" };
>> +static const char * const i2s2_clk_groups[] = { "gpio10" };
>> +static const char * const i2s2_ws_groups[] = { "gpio11" };
>> +static const char * const dmic3_clk_groups[] = { "gpio12" };
>> +static const char * const dmic3_data_groups[] = { "gpio13" };
>> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> +static const char * const i2s1_clk_groups[] = { "gpio6" };
>> +static const char * const i2s1_ws_groups[] = { "gpio7" };
>> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
>> +
>> +static const struct lpi_pingroup sc7280_groups[] = {
>> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
>> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
>> +};
>> +
>> +static const struct lpi_function sc7280_functions[] = {
>> + LPI_FUNCTION(dmic1_clk),
>> + LPI_FUNCTION(dmic1_data),
>> + LPI_FUNCTION(dmic2_clk),
>> + LPI_FUNCTION(dmic2_data),
>> + LPI_FUNCTION(dmic3_clk),
>> + LPI_FUNCTION(dmic3_data),
>> + LPI_FUNCTION(i2s1_clk),
>> + LPI_FUNCTION(i2s1_data),
>> + LPI_FUNCTION(i2s1_ws),
>> + LPI_FUNCTION(i2s2_clk),
>> + LPI_FUNCTION(i2s2_data),
>> + LPI_FUNCTION(i2s2_ws),
>> + LPI_FUNCTION(qua_mi2s_data),
>> + LPI_FUNCTION(qua_mi2s_sclk),
>> + LPI_FUNCTION(qua_mi2s_ws),
>> + LPI_FUNCTION(swr_rx_clk),
>> + LPI_FUNCTION(swr_rx_data),
>> + LPI_FUNCTION(swr_tx_clk),
>> + LPI_FUNCTION(swr_tx_data),
>> + LPI_FUNCTION(wsa_swr_clk),
>> + LPI_FUNCTION(wsa_swr_data),
>> +};
>> +
>> +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
>> + .pins = sc7280_lpi_pins,
>> + .npins = ARRAY_SIZE(sc7280_lpi_pins),
>> + .groups = sc7280_groups,
>> + .ngroups = ARRAY_SIZE(sc7280_groups),
>> + .functions = sc7280_functions,
>> + .nfunctions = ARRAY_SIZE(sc7280_functions),
>> +};
>> +
>> +static const struct of_device_id lpi_pinctrl_of_match[] = {
>> + {
>> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
>> + .data = &sc7280_lpi_data,
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> +
>> +static struct platform_driver lpi_pinctrl_driver = {
>> + .driver = {
>> + .name = "qcom-sc7280-lpass-lpi-pinctrl",
>> + .of_match_table = lpi_pinctrl_of_match,
>> + },
>> + .probe = lpi_pinctrl_probe,
>> + .remove = lpi_pinctrl_remove,
>> +};
>> +
>> +module_platform_driver(lpi_pinctrl_driver);
>> +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
>> +MODULE_LICENSE("GPL");
>> +
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration
@ 2021-12-07 15:19 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:19 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Venkata Prasad Potturu,
linux-arm-msm, plai, tiwai, agross, robh+dt, lgirdwood,
linux-gpio, broonie, rohitkr, swboyd, judyhsiao, Linus Walleij,
linux-kernel
On 12/6/2021 9:55 PM, Bjorn Andersson wrote:
Thanks for your time Bjorn!!
> On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
>
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Add pin control support for SC7280 LPASS LPI.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 8 ++
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++
>> 3 files changed, 178 insertions(+)
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index e750e10..37fe868 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI
>> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>>
>> +config PINCTRL_SC7280_LPASS_LPI
>> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
> You misspelled SC7280 here.
Okay. will address it.
>
>> + depends on PINCTRL_LPASS_LPI
>> + help
>> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> + (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
>> +
>> endif
>> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>> index 8bc877e..6c3ddaf 100644
>> --- a/drivers/pinctrl/qcom/Makefile
>> +++ b/drivers/pinctrl/qcom/Makefile
>> @@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
>> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
>> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
>> obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
>> +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
> Please keep these entries sorted alphabetically, same with Kconfig.
Okay. will address it.
>
> Regards,
> Bjorn
>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>> new file mode 100644
>> index 0000000..94bec15
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
>> @@ -0,0 +1,169 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
>> + * ALSA SoC platform-machine driver for QTi LPASS
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/gpio/driver.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "pinctrl-lpass-lpi.h"
>> +
>> +enum lpass_lpi_functions {
>> + LPI_MUX_dmic1_clk,
>> + LPI_MUX_dmic1_data,
>> + LPI_MUX_dmic2_clk,
>> + LPI_MUX_dmic2_data,
>> + LPI_MUX_dmic3_clk,
>> + LPI_MUX_dmic3_data,
>> + LPI_MUX_i2s1_clk,
>> + LPI_MUX_i2s1_data,
>> + LPI_MUX_i2s1_ws,
>> + LPI_MUX_i2s2_clk,
>> + LPI_MUX_i2s2_data,
>> + LPI_MUX_i2s2_ws,
>> + LPI_MUX_qua_mi2s_data,
>> + LPI_MUX_qua_mi2s_sclk,
>> + LPI_MUX_qua_mi2s_ws,
>> + LPI_MUX_swr_rx_clk,
>> + LPI_MUX_swr_rx_data,
>> + LPI_MUX_swr_tx_clk,
>> + LPI_MUX_swr_tx_data,
>> + LPI_MUX_wsa_swr_clk,
>> + LPI_MUX_wsa_swr_data,
>> + LPI_MUX_gpio,
>> + LPI_MUX__,
>> +};
>> +
>> +static const unsigned int gpio0_pins[] = { 0 };
>> +static const unsigned int gpio1_pins[] = { 1 };
>> +static const unsigned int gpio2_pins[] = { 2 };
>> +static const unsigned int gpio3_pins[] = { 3 };
>> +static const unsigned int gpio4_pins[] = { 4 };
>> +static const unsigned int gpio5_pins[] = { 5 };
>> +static const unsigned int gpio6_pins[] = { 6 };
>> +static const unsigned int gpio7_pins[] = { 7 };
>> +static const unsigned int gpio8_pins[] = { 8 };
>> +static const unsigned int gpio9_pins[] = { 9 };
>> +static const unsigned int gpio10_pins[] = { 10 };
>> +static const unsigned int gpio11_pins[] = { 11 };
>> +static const unsigned int gpio12_pins[] = { 12 };
>> +static const unsigned int gpio13_pins[] = { 13 };
>> +static const unsigned int gpio14_pins[] = { 14 };
>> +
>> +/* sc7280 variant specific data */
>> +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {
>> + PINCTRL_PIN(0, "gpio0"),
>> + PINCTRL_PIN(1, "gpio1"),
>> + PINCTRL_PIN(2, "gpio2"),
>> + PINCTRL_PIN(3, "gpio3"),
>> + PINCTRL_PIN(4, "gpio4"),
>> + PINCTRL_PIN(5, "gpio5"),
>> + PINCTRL_PIN(6, "gpio6"),
>> + PINCTRL_PIN(7, "gpio7"),
>> + PINCTRL_PIN(8, "gpio8"),
>> + PINCTRL_PIN(9, "gpio9"),
>> + PINCTRL_PIN(10, "gpio10"),
>> + PINCTRL_PIN(11, "gpio11"),
>> + PINCTRL_PIN(12, "gpio12"),
>> + PINCTRL_PIN(13, "gpio13"),
>> + PINCTRL_PIN(14, "gpio14"),
>> +};
>> +
>> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
>> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> +static const char * const dmic1_clk_groups[] = { "gpio6" };
>> +static const char * const dmic1_data_groups[] = { "gpio7" };
>> +static const char * const dmic2_clk_groups[] = { "gpio8" };
>> +static const char * const dmic2_data_groups[] = { "gpio9" };
>> +static const char * const i2s2_clk_groups[] = { "gpio10" };
>> +static const char * const i2s2_ws_groups[] = { "gpio11" };
>> +static const char * const dmic3_clk_groups[] = { "gpio12" };
>> +static const char * const dmic3_data_groups[] = { "gpio13" };
>> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> +static const char * const i2s1_clk_groups[] = { "gpio6" };
>> +static const char * const i2s1_ws_groups[] = { "gpio7" };
>> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
>> +
>> +static const struct lpi_pingroup sc7280_groups[] = {
>> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
>> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> + LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),
>> +};
>> +
>> +static const struct lpi_function sc7280_functions[] = {
>> + LPI_FUNCTION(dmic1_clk),
>> + LPI_FUNCTION(dmic1_data),
>> + LPI_FUNCTION(dmic2_clk),
>> + LPI_FUNCTION(dmic2_data),
>> + LPI_FUNCTION(dmic3_clk),
>> + LPI_FUNCTION(dmic3_data),
>> + LPI_FUNCTION(i2s1_clk),
>> + LPI_FUNCTION(i2s1_data),
>> + LPI_FUNCTION(i2s1_ws),
>> + LPI_FUNCTION(i2s2_clk),
>> + LPI_FUNCTION(i2s2_data),
>> + LPI_FUNCTION(i2s2_ws),
>> + LPI_FUNCTION(qua_mi2s_data),
>> + LPI_FUNCTION(qua_mi2s_sclk),
>> + LPI_FUNCTION(qua_mi2s_ws),
>> + LPI_FUNCTION(swr_rx_clk),
>> + LPI_FUNCTION(swr_rx_data),
>> + LPI_FUNCTION(swr_tx_clk),
>> + LPI_FUNCTION(swr_tx_data),
>> + LPI_FUNCTION(wsa_swr_clk),
>> + LPI_FUNCTION(wsa_swr_data),
>> +};
>> +
>> +static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
>> + .pins = sc7280_lpi_pins,
>> + .npins = ARRAY_SIZE(sc7280_lpi_pins),
>> + .groups = sc7280_groups,
>> + .ngroups = ARRAY_SIZE(sc7280_groups),
>> + .functions = sc7280_functions,
>> + .nfunctions = ARRAY_SIZE(sc7280_functions),
>> +};
>> +
>> +static const struct of_device_id lpi_pinctrl_of_match[] = {
>> + {
>> + .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
>> + .data = &sc7280_lpi_data,
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> +
>> +static struct platform_driver lpi_pinctrl_driver = {
>> + .driver = {
>> + .name = "qcom-sc7280-lpass-lpi-pinctrl",
>> + .of_match_table = lpi_pinctrl_of_match,
>> + },
>> + .probe = lpi_pinctrl_probe,
>> + .remove = lpi_pinctrl_remove,
>> +};
>> +
>> +module_platform_driver(lpi_pinctrl_driver);
>> +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
>> +MODULE_LICENSE("GPL");
>> +
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
2021-12-06 16:32 ` Bjorn Andersson
@ 2021-12-07 15:21 ` Srinivasa Rao Mandadapu
-1 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:21 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: agross, lgirdwood, broonie, robh+dt, plai, bgoswami, perex,
tiwai, srinivas.kandagatla, rohitkr, linux-arm-msm, alsa-devel,
devicetree, linux-kernel, swboyd, judyhsiao, Linus Walleij,
linux-gpio, Venkata Prasad Potturu
On 12/6/2021 10:02 PM, Bjorn Andersson wrote:
Thanks for your Valuable inputs Bjorn!!!
> On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
>
> I don't see anything _wrong_ with the current filename, so this patch
> isn't really moving chip function to the _right_ files.
>
> May I suggest that you make $subject:
>
> "pinctrl: qcom: Extract chip specific LPASS LPI code"
Okay. Will change accordingly.
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Update lpass lpi pin control driver to accommodate new lpass variant
>> SoC specific drivers.
> I also have a hard time parsing this sentence.
>
>> Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
>> and common declarations to pinctrl-lpass-lpi.h header file.
> How about simply:
>
> Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
> to allow reusing the common code in the addition of subsequent
> platforms.
Okay. Will change accordingly.
>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 8 +
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
>> drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
>> 5 files changed, 280 insertions(+), 243 deletions(-)
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index 5ff4207..e750e10 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
>> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>>
>> +config PINCTRL_SM8250_LPASS_LPI
>> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
>> + depends on PINCTRL_LPASS_LPI
>> + help
>> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>> +
>> endif
>> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>> index 7a12e8c..8bc877e 100644
>> --- a/drivers/pinctrl/qcom/Makefile
>> +++ b/drivers/pinctrl/qcom/Makefile
>> @@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
>> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
>> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
>> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
>> +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index 2f19ab4..bcc12f6 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -4,237 +4,16 @@
>> * Copyright (c) 2020 Linaro Ltd.
>> */
>>
>> -#include <linux/bitops.h>
>> -#include <linux/bitfield.h>
>> #include <linux/clk.h>
>> #include <linux/gpio/driver.h>
>> -#include <linux/io.h>
>> #include <linux/module.h>
>> #include <linux/of_device.h>
>> -#include <linux/of.h>
>> #include <linux/pinctrl/pinconf-generic.h>
>> #include <linux/pinctrl/pinconf.h>
>> #include <linux/pinctrl/pinmux.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/slab.h>
>> -#include <linux/types.h>
>> #include "../core.h"
>> #include "../pinctrl-utils.h"
>> -
>> -#define LPI_SLEW_RATE_CTL_REG 0xa000
>> -#define LPI_TLMM_REG_OFFSET 0x1000
>> -#define LPI_SLEW_RATE_MAX 0x03
>> -#define LPI_SLEW_BITS_SIZE 0x02
>> -#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
>> -#define LPI_GPIO_CFG_REG 0x00
>> -#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
>> -#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
>> -#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
>> -#define LPI_GPIO_OE_MASK BIT(9)
>> -#define LPI_GPIO_VALUE_REG 0x04
>> -#define LPI_GPIO_VALUE_IN_MASK BIT(0)
>> -#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
>> -
>> -#define LPI_GPIO_BIAS_DISABLE 0x0
>> -#define LPI_GPIO_PULL_DOWN 0x1
>> -#define LPI_GPIO_KEEPER 0x2
>> -#define LPI_GPIO_PULL_UP 0x3
>> -#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
>> -#define NO_SLEW -1
>> -
>> -#define LPI_FUNCTION(fname) \
>> - [LPI_MUX_##fname] = { \
>> - .name = #fname, \
>> - .groups = fname##_groups, \
>> - .ngroups = ARRAY_SIZE(fname##_groups), \
>> - }
>> -
>> -#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
>> - { \
>> - .name = "gpio" #id, \
>> - .pins = gpio##id##_pins, \
>> - .pin = id, \
>> - .slew_offset = soff, \
>> - .npins = ARRAY_SIZE(gpio##id##_pins), \
>> - .funcs = (int[]){ \
>> - LPI_MUX_gpio, \
>> - LPI_MUX_##f1, \
>> - LPI_MUX_##f2, \
>> - LPI_MUX_##f3, \
>> - LPI_MUX_##f4, \
>> - }, \
>> - .nfuncs = 5, \
>> - }
>> -
>> -struct lpi_pingroup {
>> - const char *name;
>> - const unsigned int *pins;
>> - unsigned int npins;
>> - unsigned int pin;
>> - /* Bit offset in slew register for SoundWire pins only */
>> - int slew_offset;
>> - unsigned int *funcs;
>> - unsigned int nfuncs;
>> -};
>> -
>> -struct lpi_function {
>> - const char *name;
>> - const char * const *groups;
>> - unsigned int ngroups;
>> -};
>> -
>> -struct lpi_pinctrl_variant_data {
>> - const struct pinctrl_pin_desc *pins;
>> - int npins;
>> - const struct lpi_pingroup *groups;
>> - int ngroups;
>> - const struct lpi_function *functions;
>> - int nfunctions;
>> -};
>> -
>> -#define MAX_LPI_NUM_CLKS 2
>> -
>> -struct lpi_pinctrl {
>> - struct device *dev;
>> - struct pinctrl_dev *ctrl;
>> - struct gpio_chip chip;
>> - struct pinctrl_desc desc;
>> - char __iomem *tlmm_base;
>> - char __iomem *slew_base;
>> - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
>> - struct mutex slew_access_lock;
>> - const struct lpi_pinctrl_variant_data *data;
>> -};
>> -
>> -/* sm8250 variant specific data */
>> -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
>> - PINCTRL_PIN(0, "gpio0"),
>> - PINCTRL_PIN(1, "gpio1"),
>> - PINCTRL_PIN(2, "gpio2"),
>> - PINCTRL_PIN(3, "gpio3"),
>> - PINCTRL_PIN(4, "gpio4"),
>> - PINCTRL_PIN(5, "gpio5"),
>> - PINCTRL_PIN(6, "gpio6"),
>> - PINCTRL_PIN(7, "gpio7"),
>> - PINCTRL_PIN(8, "gpio8"),
>> - PINCTRL_PIN(9, "gpio9"),
>> - PINCTRL_PIN(10, "gpio10"),
>> - PINCTRL_PIN(11, "gpio11"),
>> - PINCTRL_PIN(12, "gpio12"),
>> - PINCTRL_PIN(13, "gpio13"),
>> -};
>> -
>> -enum sm8250_lpi_functions {
>> - LPI_MUX_dmic1_clk,
>> - LPI_MUX_dmic1_data,
>> - LPI_MUX_dmic2_clk,
>> - LPI_MUX_dmic2_data,
>> - LPI_MUX_dmic3_clk,
>> - LPI_MUX_dmic3_data,
>> - LPI_MUX_i2s1_clk,
>> - LPI_MUX_i2s1_data,
>> - LPI_MUX_i2s1_ws,
>> - LPI_MUX_i2s2_clk,
>> - LPI_MUX_i2s2_data,
>> - LPI_MUX_i2s2_ws,
>> - LPI_MUX_qua_mi2s_data,
>> - LPI_MUX_qua_mi2s_sclk,
>> - LPI_MUX_qua_mi2s_ws,
>> - LPI_MUX_swr_rx_clk,
>> - LPI_MUX_swr_rx_data,
>> - LPI_MUX_swr_tx_clk,
>> - LPI_MUX_swr_tx_data,
>> - LPI_MUX_wsa_swr_clk,
>> - LPI_MUX_wsa_swr_data,
>> - LPI_MUX_gpio,
>> - LPI_MUX__,
>> -};
>> -
>> -static const unsigned int gpio0_pins[] = { 0 };
>> -static const unsigned int gpio1_pins[] = { 1 };
>> -static const unsigned int gpio2_pins[] = { 2 };
>> -static const unsigned int gpio3_pins[] = { 3 };
>> -static const unsigned int gpio4_pins[] = { 4 };
>> -static const unsigned int gpio5_pins[] = { 5 };
>> -static const unsigned int gpio6_pins[] = { 6 };
>> -static const unsigned int gpio7_pins[] = { 7 };
>> -static const unsigned int gpio8_pins[] = { 8 };
>> -static const unsigned int gpio9_pins[] = { 9 };
>> -static const unsigned int gpio10_pins[] = { 10 };
>> -static const unsigned int gpio11_pins[] = { 11 };
>> -static const unsigned int gpio12_pins[] = { 12 };
>> -static const unsigned int gpio13_pins[] = { 13 };
>> -static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> -static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
>> -static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> -static const char * const dmic1_clk_groups[] = { "gpio6" };
>> -static const char * const dmic1_data_groups[] = { "gpio7" };
>> -static const char * const dmic2_clk_groups[] = { "gpio8" };
>> -static const char * const dmic2_data_groups[] = { "gpio9" };
>> -static const char * const i2s2_clk_groups[] = { "gpio10" };
>> -static const char * const i2s2_ws_groups[] = { "gpio11" };
>> -static const char * const dmic3_clk_groups[] = { "gpio12" };
>> -static const char * const dmic3_data_groups[] = { "gpio13" };
>> -static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> -static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> -static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> -static const char * const i2s1_clk_groups[] = { "gpio6" };
>> -static const char * const i2s1_ws_groups[] = { "gpio7" };
>> -static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> -static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> -static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> -static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
>> -
>> -static const struct lpi_pingroup sm8250_groups[] = {
>> - LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> - LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> - LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
>> - LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> - LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> - LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> - LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> - LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> - LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> - LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> - LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> -};
>> -
>> -static const struct lpi_function sm8250_functions[] = {
>> - LPI_FUNCTION(dmic1_clk),
>> - LPI_FUNCTION(dmic1_data),
>> - LPI_FUNCTION(dmic2_clk),
>> - LPI_FUNCTION(dmic2_data),
>> - LPI_FUNCTION(dmic3_clk),
>> - LPI_FUNCTION(dmic3_data),
>> - LPI_FUNCTION(i2s1_clk),
>> - LPI_FUNCTION(i2s1_data),
>> - LPI_FUNCTION(i2s1_ws),
>> - LPI_FUNCTION(i2s2_clk),
>> - LPI_FUNCTION(i2s2_data),
>> - LPI_FUNCTION(i2s2_ws),
>> - LPI_FUNCTION(qua_mi2s_data),
>> - LPI_FUNCTION(qua_mi2s_sclk),
>> - LPI_FUNCTION(qua_mi2s_ws),
>> - LPI_FUNCTION(swr_rx_clk),
>> - LPI_FUNCTION(swr_rx_data),
>> - LPI_FUNCTION(swr_tx_clk),
>> - LPI_FUNCTION(swr_tx_data),
>> - LPI_FUNCTION(wsa_swr_clk),
>> - LPI_FUNCTION(wsa_swr_data),
>> -};
>> -
>> -static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
>> - .pins = sm8250_lpi_pins,
>> - .npins = ARRAY_SIZE(sm8250_lpi_pins),
>> - .groups = sm8250_groups,
>> - .ngroups = ARRAY_SIZE(sm8250_groups),
>> - .functions = sm8250_functions,
>> - .nfunctions = ARRAY_SIZE(sm8250_functions),
>> -};
>> +#include "pinctrl-lpass-lpi.h"
>>
>> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
>> unsigned int addr)
>> @@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
>> .dbg_show = lpi_gpio_dbg_show,
>> };
>>
>> -static int lpi_pinctrl_probe(struct platform_device *pdev)
>> +int lpi_pinctrl_probe(struct platform_device *pdev)
>> {
>> const struct lpi_pinctrl_variant_data *data;
>> struct device *dev = &pdev->dev;
>> @@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
>>
>> return ret;
>> }
>> +EXPORT_SYMBOL(lpi_pinctrl_probe);
>>
>> -static int lpi_pinctrl_remove(struct platform_device *pdev)
>> +
>> +int lpi_pinctrl_remove(struct platform_device *pdev)
>> {
>> struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
>>
>> @@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
>>
>> return 0;
>> }
>> +EXPORT_SYMBOL(lpi_pinctrl_remove);
>>
>> -static const struct of_device_id lpi_pinctrl_of_match[] = {
>> - {
>> - .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
>> - .data = &sm8250_lpi_data,
>> - },
>> - { }
>> -};
>> -MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> -
>> -static struct platform_driver lpi_pinctrl_driver = {
>> - .driver = {
>> - .name = "qcom-lpass-lpi-pinctrl",
>> - .of_match_table = lpi_pinctrl_of_match,
>> - },
>> - .probe = lpi_pinctrl_probe,
>> - .remove = lpi_pinctrl_remove,
>> -};
>> -
>> -module_platform_driver(lpi_pinctrl_driver);
>> MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
>> MODULE_LICENSE("GPL");
>> +
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> new file mode 100644
>> index 0000000..ad84565
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> @@ -0,0 +1,98 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2020 Linaro Ltd.
>> + */
>> +#ifndef __PINCTRL_LPASS_LPI_H__
>> +#define __PINCTRL_LPASS_LPI_H__
>> +
>> +#define LPI_SLEW_RATE_CTL_REG 0xa000
>> +#define LPI_TLMM_REG_OFFSET 0x1000
>> +#define LPI_SLEW_RATE_MAX 0x03
>> +#define LPI_SLEW_BITS_SIZE 0x02
>> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
>> +#define LPI_GPIO_CFG_REG 0x00
>> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
>> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
>> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
>> +#define LPI_GPIO_OE_MASK BIT(9)
>> +#define LPI_GPIO_VALUE_REG 0x04
>> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
>> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
>> +
>> +#define LPI_GPIO_BIAS_DISABLE 0x0
>> +#define LPI_GPIO_PULL_DOWN 0x1
>> +#define LPI_GPIO_KEEPER 0x2
>> +#define LPI_GPIO_PULL_UP 0x3
>> +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
>> +#define NO_SLEW -1
>> +
>> +#define LPI_FUNCTION(fname) \
>> + [LPI_MUX_##fname] = { \
>> + .name = #fname, \
>> + .groups = fname##_groups, \
>> + .ngroups = ARRAY_SIZE(fname##_groups), \
>> + }
>> +
>> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
>> + { \
>> + .name = "gpio" #id, \
>> + .pins = gpio##id##_pins, \
>> + .pin = id, \
>> + .slew_offset = soff, \
>> + .npins = ARRAY_SIZE(gpio##id##_pins), \
>> + .funcs = (int[]){ \
>> + LPI_MUX_gpio, \
>> + LPI_MUX_##f1, \
>> + LPI_MUX_##f2, \
>> + LPI_MUX_##f3, \
>> + LPI_MUX_##f4, \
>> + }, \
>> + .nfuncs = 5, \
>> + }
>> +
>> +struct lpi_pingroup {
>> + const char *name;
>> + const unsigned int *pins;
>> + unsigned int npins;
>> + unsigned int pin;
>> + /* Bit offset in slew register for SoundWire pins only */
>> + int slew_offset;
>> + unsigned int *funcs;
>> + unsigned int nfuncs;
>> +};
>> +
>> +struct lpi_function {
>> + const char *name;
>> + const char * const *groups;
>> + unsigned int ngroups;
>> +};
>> +
>> +struct lpi_pinctrl_variant_data {
>> + const struct pinctrl_pin_desc *pins;
>> + int npins;
>> + const struct lpi_pingroup *groups;
>> + int ngroups;
>> + const struct lpi_function *functions;
>> + int nfunctions;
>> +};
>> +
>> +#define MAX_LPI_NUM_CLKS 2
>> +
>> +struct lpi_pinctrl {
> Afaict this is only used by the common code, if so there's no need to
> expose it in the header file.
>
>> + struct device *dev;
>> + struct pinctrl_dev *ctrl;
>> + struct gpio_chip chip;
>> + struct pinctrl_desc desc;
>> + char __iomem *tlmm_base;
>> + char __iomem *slew_base;
>> + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
>> + struct mutex slew_access_lock;
>> + const struct lpi_pinctrl_variant_data *data;
>> +};
>> +
>> +int lpi_pinctrl_probe(struct platform_device *pdev);
>> +int lpi_pinctrl_remove(struct platform_device *pdev);
>> +
>> +#endif /*__PINCTRL_LPASS_LPI_H__*/
>> +
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>> new file mode 100644
>> index 0000000..9a5db15
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>> @@ -0,0 +1,166 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2020 Linaro Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/gpio/driver.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "pinctrl-lpass-lpi.h"
>> +
>> +enum lpass_lpi_functions {
>> + LPI_MUX_dmic1_clk,
>> + LPI_MUX_dmic1_data,
>> + LPI_MUX_dmic2_clk,
>> + LPI_MUX_dmic2_data,
>> + LPI_MUX_dmic3_clk,
>> + LPI_MUX_dmic3_data,
>> + LPI_MUX_i2s1_clk,
>> + LPI_MUX_i2s1_data,
>> + LPI_MUX_i2s1_ws,
>> + LPI_MUX_i2s2_clk,
>> + LPI_MUX_i2s2_data,
>> + LPI_MUX_i2s2_ws,
>> + LPI_MUX_qua_mi2s_data,
>> + LPI_MUX_qua_mi2s_sclk,
>> + LPI_MUX_qua_mi2s_ws,
>> + LPI_MUX_swr_rx_clk,
>> + LPI_MUX_swr_rx_data,
>> + LPI_MUX_swr_tx_clk,
>> + LPI_MUX_swr_tx_data,
>> + LPI_MUX_wsa_swr_clk,
>> + LPI_MUX_wsa_swr_data,
>> + LPI_MUX_gpio,
>> + LPI_MUX__,
>> +};
>> +
>> +static const unsigned int gpio0_pins[] = { 0 };
>> +static const unsigned int gpio1_pins[] = { 1 };
>> +static const unsigned int gpio2_pins[] = { 2 };
>> +static const unsigned int gpio3_pins[] = { 3 };
>> +static const unsigned int gpio4_pins[] = { 4 };
>> +static const unsigned int gpio5_pins[] = { 5 };
>> +static const unsigned int gpio6_pins[] = { 6 };
>> +static const unsigned int gpio7_pins[] = { 7 };
>> +static const unsigned int gpio8_pins[] = { 8 };
>> +static const unsigned int gpio9_pins[] = { 9 };
>> +static const unsigned int gpio10_pins[] = { 10 };
>> +static const unsigned int gpio11_pins[] = { 11 };
>> +static const unsigned int gpio12_pins[] = { 12 };
>> +static const unsigned int gpio13_pins[] = { 13 };
>> +
>> +/* sm8250 variant specific data */
>> +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
>> + PINCTRL_PIN(0, "gpio0"),
>> + PINCTRL_PIN(1, "gpio1"),
>> + PINCTRL_PIN(2, "gpio2"),
>> + PINCTRL_PIN(3, "gpio3"),
>> + PINCTRL_PIN(4, "gpio4"),
>> + PINCTRL_PIN(5, "gpio5"),
>> + PINCTRL_PIN(6, "gpio6"),
>> + PINCTRL_PIN(7, "gpio7"),
>> + PINCTRL_PIN(8, "gpio8"),
>> + PINCTRL_PIN(9, "gpio9"),
>> + PINCTRL_PIN(10, "gpio10"),
>> + PINCTRL_PIN(11, "gpio11"),
>> + PINCTRL_PIN(12, "gpio12"),
>> + PINCTRL_PIN(13, "gpio13"),
>> +};
>> +
>> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
>> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> +static const char * const dmic1_clk_groups[] = { "gpio6" };
>> +static const char * const dmic1_data_groups[] = { "gpio7" };
>> +static const char * const dmic2_clk_groups[] = { "gpio8" };
>> +static const char * const dmic2_data_groups[] = { "gpio9" };
>> +static const char * const i2s2_clk_groups[] = { "gpio10" };
>> +static const char * const i2s2_ws_groups[] = { "gpio11" };
>> +static const char * const dmic3_clk_groups[] = { "gpio12" };
>> +static const char * const dmic3_data_groups[] = { "gpio13" };
>> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> +static const char * const i2s1_clk_groups[] = { "gpio6" };
>> +static const char * const i2s1_ws_groups[] = { "gpio7" };
>> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
>> +
>> +static const struct lpi_pingroup sm8250_groups[] = {
>> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
>> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> +};
>> +
>> +static const struct lpi_function sm8250_functions[] = {
>> + LPI_FUNCTION(dmic1_clk),
>> + LPI_FUNCTION(dmic1_data),
>> + LPI_FUNCTION(dmic2_clk),
>> + LPI_FUNCTION(dmic2_data),
>> + LPI_FUNCTION(dmic3_clk),
>> + LPI_FUNCTION(dmic3_data),
>> + LPI_FUNCTION(i2s1_clk),
>> + LPI_FUNCTION(i2s1_data),
>> + LPI_FUNCTION(i2s1_ws),
>> + LPI_FUNCTION(i2s2_clk),
>> + LPI_FUNCTION(i2s2_data),
>> + LPI_FUNCTION(i2s2_ws),
>> + LPI_FUNCTION(qua_mi2s_data),
>> + LPI_FUNCTION(qua_mi2s_sclk),
>> + LPI_FUNCTION(qua_mi2s_ws),
>> + LPI_FUNCTION(swr_rx_clk),
>> + LPI_FUNCTION(swr_rx_data),
>> + LPI_FUNCTION(swr_tx_clk),
>> + LPI_FUNCTION(swr_tx_data),
>> + LPI_FUNCTION(wsa_swr_clk),
>> + LPI_FUNCTION(wsa_swr_data),
>> +};
>> +
>> +static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
>> + .pins = sm8250_lpi_pins,
>> + .npins = ARRAY_SIZE(sm8250_lpi_pins),
>> + .groups = sm8250_groups,
>> + .ngroups = ARRAY_SIZE(sm8250_groups),
>> + .functions = sm8250_functions,
>> + .nfunctions = ARRAY_SIZE(sm8250_functions),
>> +};
>> +
>> +static const struct of_device_id lpi_pinctrl_of_match[] = {
>> + {
>> + .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
>> + .data = &sm8250_lpi_data,
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> +
>> +static struct platform_driver lpi_pinctrl_driver = {
>> + .driver = {
>> + .name = "qcom-sm8250-lpass-lpi-pinctrl",
>> + .of_match_table = lpi_pinctrl_of_match,
>> + },
>> + .probe = lpi_pinctrl_probe,
>> + .remove = lpi_pinctrl_remove,
>> +};
>> +
>> +module_platform_driver(lpi_pinctrl_driver);
>> +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
>> +MODULE_LICENSE("GPL");
>> +
> Unnecessary empty line.
>
> Thanks,
> Bjorn
>
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files
@ 2021-12-07 15:21 ` Srinivasa Rao Mandadapu
0 siblings, 0 replies; 28+ messages in thread
From: Srinivasa Rao Mandadapu @ 2021-12-07 15:21 UTC (permalink / raw)
To: Bjorn Andersson, Srinivasa Rao Mandadapu
Cc: devicetree, alsa-devel, bgoswami, Venkata Prasad Potturu,
linux-arm-msm, plai, tiwai, agross, robh+dt, lgirdwood,
linux-gpio, broonie, rohitkr, swboyd, judyhsiao, Linus Walleij,
linux-kernel
On 12/6/2021 10:02 PM, Bjorn Andersson wrote:
Thanks for your Valuable inputs Bjorn!!!
> On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:
>
> I don't see anything _wrong_ with the current filename, so this patch
> isn't really moving chip function to the _right_ files.
>
> May I suggest that you make $subject:
>
> "pinctrl: qcom: Extract chip specific LPASS LPI code"
Okay. Will change accordingly.
>> From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>>
>> Update lpass lpi pin control driver to accommodate new lpass variant
>> SoC specific drivers.
> I also have a hard time parsing this sentence.
>
>> Move sm8250 SoC specific functions to pinctrl-sm8250-lpass-lpi.c file
>> and common declarations to pinctrl-lpass-lpi.h header file.
> How about simply:
>
> Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
> to allow reusing the common code in the addition of subsequent
> platforms.
Okay. Will change accordingly.
>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> Co-developed-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> Signed-off-by: Venkata Prasad Potturu <potturu@codeaurora.org>
>> ---
>> drivers/pinctrl/qcom/Kconfig | 8 +
>> drivers/pinctrl/qcom/Makefile | 1 +
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 250 +-----------------------
>> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 98 ++++++++++
>> drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 166 ++++++++++++++++
>> 5 files changed, 280 insertions(+), 243 deletions(-)
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index 5ff4207..e750e10 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -320,4 +320,12 @@ config PINCTRL_LPASS_LPI
>> Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
>>
>> +config PINCTRL_SM8250_LPASS_LPI
>> + tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
>> + depends on PINCTRL_LPASS_LPI
>> + help
>> + This is the pinctrl, pinmux, pinconf and gpiolib driver for the
>> + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
>> + (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.
>> +
>> endif
>> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>> index 7a12e8c..8bc877e 100644
>> --- a/drivers/pinctrl/qcom/Makefile
>> +++ b/drivers/pinctrl/qcom/Makefile
>> @@ -37,3 +37,4 @@ obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
>> obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
>> obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
>> obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
>> +obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> index 2f19ab4..bcc12f6 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
>> @@ -4,237 +4,16 @@
>> * Copyright (c) 2020 Linaro Ltd.
>> */
>>
>> -#include <linux/bitops.h>
>> -#include <linux/bitfield.h>
>> #include <linux/clk.h>
>> #include <linux/gpio/driver.h>
>> -#include <linux/io.h>
>> #include <linux/module.h>
>> #include <linux/of_device.h>
>> -#include <linux/of.h>
>> #include <linux/pinctrl/pinconf-generic.h>
>> #include <linux/pinctrl/pinconf.h>
>> #include <linux/pinctrl/pinmux.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/slab.h>
>> -#include <linux/types.h>
>> #include "../core.h"
>> #include "../pinctrl-utils.h"
>> -
>> -#define LPI_SLEW_RATE_CTL_REG 0xa000
>> -#define LPI_TLMM_REG_OFFSET 0x1000
>> -#define LPI_SLEW_RATE_MAX 0x03
>> -#define LPI_SLEW_BITS_SIZE 0x02
>> -#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
>> -#define LPI_GPIO_CFG_REG 0x00
>> -#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
>> -#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
>> -#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
>> -#define LPI_GPIO_OE_MASK BIT(9)
>> -#define LPI_GPIO_VALUE_REG 0x04
>> -#define LPI_GPIO_VALUE_IN_MASK BIT(0)
>> -#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
>> -
>> -#define LPI_GPIO_BIAS_DISABLE 0x0
>> -#define LPI_GPIO_PULL_DOWN 0x1
>> -#define LPI_GPIO_KEEPER 0x2
>> -#define LPI_GPIO_PULL_UP 0x3
>> -#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
>> -#define NO_SLEW -1
>> -
>> -#define LPI_FUNCTION(fname) \
>> - [LPI_MUX_##fname] = { \
>> - .name = #fname, \
>> - .groups = fname##_groups, \
>> - .ngroups = ARRAY_SIZE(fname##_groups), \
>> - }
>> -
>> -#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
>> - { \
>> - .name = "gpio" #id, \
>> - .pins = gpio##id##_pins, \
>> - .pin = id, \
>> - .slew_offset = soff, \
>> - .npins = ARRAY_SIZE(gpio##id##_pins), \
>> - .funcs = (int[]){ \
>> - LPI_MUX_gpio, \
>> - LPI_MUX_##f1, \
>> - LPI_MUX_##f2, \
>> - LPI_MUX_##f3, \
>> - LPI_MUX_##f4, \
>> - }, \
>> - .nfuncs = 5, \
>> - }
>> -
>> -struct lpi_pingroup {
>> - const char *name;
>> - const unsigned int *pins;
>> - unsigned int npins;
>> - unsigned int pin;
>> - /* Bit offset in slew register for SoundWire pins only */
>> - int slew_offset;
>> - unsigned int *funcs;
>> - unsigned int nfuncs;
>> -};
>> -
>> -struct lpi_function {
>> - const char *name;
>> - const char * const *groups;
>> - unsigned int ngroups;
>> -};
>> -
>> -struct lpi_pinctrl_variant_data {
>> - const struct pinctrl_pin_desc *pins;
>> - int npins;
>> - const struct lpi_pingroup *groups;
>> - int ngroups;
>> - const struct lpi_function *functions;
>> - int nfunctions;
>> -};
>> -
>> -#define MAX_LPI_NUM_CLKS 2
>> -
>> -struct lpi_pinctrl {
>> - struct device *dev;
>> - struct pinctrl_dev *ctrl;
>> - struct gpio_chip chip;
>> - struct pinctrl_desc desc;
>> - char __iomem *tlmm_base;
>> - char __iomem *slew_base;
>> - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
>> - struct mutex slew_access_lock;
>> - const struct lpi_pinctrl_variant_data *data;
>> -};
>> -
>> -/* sm8250 variant specific data */
>> -static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
>> - PINCTRL_PIN(0, "gpio0"),
>> - PINCTRL_PIN(1, "gpio1"),
>> - PINCTRL_PIN(2, "gpio2"),
>> - PINCTRL_PIN(3, "gpio3"),
>> - PINCTRL_PIN(4, "gpio4"),
>> - PINCTRL_PIN(5, "gpio5"),
>> - PINCTRL_PIN(6, "gpio6"),
>> - PINCTRL_PIN(7, "gpio7"),
>> - PINCTRL_PIN(8, "gpio8"),
>> - PINCTRL_PIN(9, "gpio9"),
>> - PINCTRL_PIN(10, "gpio10"),
>> - PINCTRL_PIN(11, "gpio11"),
>> - PINCTRL_PIN(12, "gpio12"),
>> - PINCTRL_PIN(13, "gpio13"),
>> -};
>> -
>> -enum sm8250_lpi_functions {
>> - LPI_MUX_dmic1_clk,
>> - LPI_MUX_dmic1_data,
>> - LPI_MUX_dmic2_clk,
>> - LPI_MUX_dmic2_data,
>> - LPI_MUX_dmic3_clk,
>> - LPI_MUX_dmic3_data,
>> - LPI_MUX_i2s1_clk,
>> - LPI_MUX_i2s1_data,
>> - LPI_MUX_i2s1_ws,
>> - LPI_MUX_i2s2_clk,
>> - LPI_MUX_i2s2_data,
>> - LPI_MUX_i2s2_ws,
>> - LPI_MUX_qua_mi2s_data,
>> - LPI_MUX_qua_mi2s_sclk,
>> - LPI_MUX_qua_mi2s_ws,
>> - LPI_MUX_swr_rx_clk,
>> - LPI_MUX_swr_rx_data,
>> - LPI_MUX_swr_tx_clk,
>> - LPI_MUX_swr_tx_data,
>> - LPI_MUX_wsa_swr_clk,
>> - LPI_MUX_wsa_swr_data,
>> - LPI_MUX_gpio,
>> - LPI_MUX__,
>> -};
>> -
>> -static const unsigned int gpio0_pins[] = { 0 };
>> -static const unsigned int gpio1_pins[] = { 1 };
>> -static const unsigned int gpio2_pins[] = { 2 };
>> -static const unsigned int gpio3_pins[] = { 3 };
>> -static const unsigned int gpio4_pins[] = { 4 };
>> -static const unsigned int gpio5_pins[] = { 5 };
>> -static const unsigned int gpio6_pins[] = { 6 };
>> -static const unsigned int gpio7_pins[] = { 7 };
>> -static const unsigned int gpio8_pins[] = { 8 };
>> -static const unsigned int gpio9_pins[] = { 9 };
>> -static const unsigned int gpio10_pins[] = { 10 };
>> -static const unsigned int gpio11_pins[] = { 11 };
>> -static const unsigned int gpio12_pins[] = { 12 };
>> -static const unsigned int gpio13_pins[] = { 13 };
>> -static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> -static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
>> -static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> -static const char * const dmic1_clk_groups[] = { "gpio6" };
>> -static const char * const dmic1_data_groups[] = { "gpio7" };
>> -static const char * const dmic2_clk_groups[] = { "gpio8" };
>> -static const char * const dmic2_data_groups[] = { "gpio9" };
>> -static const char * const i2s2_clk_groups[] = { "gpio10" };
>> -static const char * const i2s2_ws_groups[] = { "gpio11" };
>> -static const char * const dmic3_clk_groups[] = { "gpio12" };
>> -static const char * const dmic3_data_groups[] = { "gpio13" };
>> -static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> -static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> -static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> -static const char * const i2s1_clk_groups[] = { "gpio6" };
>> -static const char * const i2s1_ws_groups[] = { "gpio7" };
>> -static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> -static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> -static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> -static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
>> -
>> -static const struct lpi_pingroup sm8250_groups[] = {
>> - LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> - LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> - LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> - LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
>> - LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> - LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> - LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> - LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> - LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> - LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> - LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> - LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> -};
>> -
>> -static const struct lpi_function sm8250_functions[] = {
>> - LPI_FUNCTION(dmic1_clk),
>> - LPI_FUNCTION(dmic1_data),
>> - LPI_FUNCTION(dmic2_clk),
>> - LPI_FUNCTION(dmic2_data),
>> - LPI_FUNCTION(dmic3_clk),
>> - LPI_FUNCTION(dmic3_data),
>> - LPI_FUNCTION(i2s1_clk),
>> - LPI_FUNCTION(i2s1_data),
>> - LPI_FUNCTION(i2s1_ws),
>> - LPI_FUNCTION(i2s2_clk),
>> - LPI_FUNCTION(i2s2_data),
>> - LPI_FUNCTION(i2s2_ws),
>> - LPI_FUNCTION(qua_mi2s_data),
>> - LPI_FUNCTION(qua_mi2s_sclk),
>> - LPI_FUNCTION(qua_mi2s_ws),
>> - LPI_FUNCTION(swr_rx_clk),
>> - LPI_FUNCTION(swr_rx_data),
>> - LPI_FUNCTION(swr_tx_clk),
>> - LPI_FUNCTION(swr_tx_data),
>> - LPI_FUNCTION(wsa_swr_clk),
>> - LPI_FUNCTION(wsa_swr_data),
>> -};
>> -
>> -static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
>> - .pins = sm8250_lpi_pins,
>> - .npins = ARRAY_SIZE(sm8250_lpi_pins),
>> - .groups = sm8250_groups,
>> - .ngroups = ARRAY_SIZE(sm8250_groups),
>> - .functions = sm8250_functions,
>> - .nfunctions = ARRAY_SIZE(sm8250_functions),
>> -};
>> +#include "pinctrl-lpass-lpi.h"
>>
>> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
>> unsigned int addr)
>> @@ -582,7 +361,7 @@ static const struct gpio_chip lpi_gpio_template = {
>> .dbg_show = lpi_gpio_dbg_show,
>> };
>>
>> -static int lpi_pinctrl_probe(struct platform_device *pdev)
>> +int lpi_pinctrl_probe(struct platform_device *pdev)
>> {
>> const struct lpi_pinctrl_variant_data *data;
>> struct device *dev = &pdev->dev;
>> @@ -661,8 +440,10 @@ static int lpi_pinctrl_probe(struct platform_device *pdev)
>>
>> return ret;
>> }
>> +EXPORT_SYMBOL(lpi_pinctrl_probe);
>>
>> -static int lpi_pinctrl_remove(struct platform_device *pdev)
>> +
>> +int lpi_pinctrl_remove(struct platform_device *pdev)
>> {
>> struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
>>
>> @@ -671,25 +452,8 @@ static int lpi_pinctrl_remove(struct platform_device *pdev)
>>
>> return 0;
>> }
>> +EXPORT_SYMBOL(lpi_pinctrl_remove);
>>
>> -static const struct of_device_id lpi_pinctrl_of_match[] = {
>> - {
>> - .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
>> - .data = &sm8250_lpi_data,
>> - },
>> - { }
>> -};
>> -MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> -
>> -static struct platform_driver lpi_pinctrl_driver = {
>> - .driver = {
>> - .name = "qcom-lpass-lpi-pinctrl",
>> - .of_match_table = lpi_pinctrl_of_match,
>> - },
>> - .probe = lpi_pinctrl_probe,
>> - .remove = lpi_pinctrl_remove,
>> -};
>> -
>> -module_platform_driver(lpi_pinctrl_driver);
>> MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
>> MODULE_LICENSE("GPL");
>> +
>> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> new file mode 100644
>> index 0000000..ad84565
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
>> @@ -0,0 +1,98 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2020 Linaro Ltd.
>> + */
>> +#ifndef __PINCTRL_LPASS_LPI_H__
>> +#define __PINCTRL_LPASS_LPI_H__
>> +
>> +#define LPI_SLEW_RATE_CTL_REG 0xa000
>> +#define LPI_TLMM_REG_OFFSET 0x1000
>> +#define LPI_SLEW_RATE_MAX 0x03
>> +#define LPI_SLEW_BITS_SIZE 0x02
>> +#define LPI_SLEW_RATE_MASK GENMASK(1, 0)
>> +#define LPI_GPIO_CFG_REG 0x00
>> +#define LPI_GPIO_PULL_MASK GENMASK(1, 0)
>> +#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
>> +#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
>> +#define LPI_GPIO_OE_MASK BIT(9)
>> +#define LPI_GPIO_VALUE_REG 0x04
>> +#define LPI_GPIO_VALUE_IN_MASK BIT(0)
>> +#define LPI_GPIO_VALUE_OUT_MASK BIT(1)
>> +
>> +#define LPI_GPIO_BIAS_DISABLE 0x0
>> +#define LPI_GPIO_PULL_DOWN 0x1
>> +#define LPI_GPIO_KEEPER 0x2
>> +#define LPI_GPIO_PULL_UP 0x3
>> +#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
>> +#define NO_SLEW -1
>> +
>> +#define LPI_FUNCTION(fname) \
>> + [LPI_MUX_##fname] = { \
>> + .name = #fname, \
>> + .groups = fname##_groups, \
>> + .ngroups = ARRAY_SIZE(fname##_groups), \
>> + }
>> +
>> +#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
>> + { \
>> + .name = "gpio" #id, \
>> + .pins = gpio##id##_pins, \
>> + .pin = id, \
>> + .slew_offset = soff, \
>> + .npins = ARRAY_SIZE(gpio##id##_pins), \
>> + .funcs = (int[]){ \
>> + LPI_MUX_gpio, \
>> + LPI_MUX_##f1, \
>> + LPI_MUX_##f2, \
>> + LPI_MUX_##f3, \
>> + LPI_MUX_##f4, \
>> + }, \
>> + .nfuncs = 5, \
>> + }
>> +
>> +struct lpi_pingroup {
>> + const char *name;
>> + const unsigned int *pins;
>> + unsigned int npins;
>> + unsigned int pin;
>> + /* Bit offset in slew register for SoundWire pins only */
>> + int slew_offset;
>> + unsigned int *funcs;
>> + unsigned int nfuncs;
>> +};
>> +
>> +struct lpi_function {
>> + const char *name;
>> + const char * const *groups;
>> + unsigned int ngroups;
>> +};
>> +
>> +struct lpi_pinctrl_variant_data {
>> + const struct pinctrl_pin_desc *pins;
>> + int npins;
>> + const struct lpi_pingroup *groups;
>> + int ngroups;
>> + const struct lpi_function *functions;
>> + int nfunctions;
>> +};
>> +
>> +#define MAX_LPI_NUM_CLKS 2
>> +
>> +struct lpi_pinctrl {
> Afaict this is only used by the common code, if so there's no need to
> expose it in the header file.
>
>> + struct device *dev;
>> + struct pinctrl_dev *ctrl;
>> + struct gpio_chip chip;
>> + struct pinctrl_desc desc;
>> + char __iomem *tlmm_base;
>> + char __iomem *slew_base;
>> + struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
>> + struct mutex slew_access_lock;
>> + const struct lpi_pinctrl_variant_data *data;
>> +};
>> +
>> +int lpi_pinctrl_probe(struct platform_device *pdev);
>> +int lpi_pinctrl_remove(struct platform_device *pdev);
>> +
>> +#endif /*__PINCTRL_LPASS_LPI_H__*/
>> +
>> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>> new file mode 100644
>> index 0000000..9a5db15
>> --- /dev/null
>> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
>> @@ -0,0 +1,166 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2020 Linaro Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/gpio/driver.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "pinctrl-lpass-lpi.h"
>> +
>> +enum lpass_lpi_functions {
>> + LPI_MUX_dmic1_clk,
>> + LPI_MUX_dmic1_data,
>> + LPI_MUX_dmic2_clk,
>> + LPI_MUX_dmic2_data,
>> + LPI_MUX_dmic3_clk,
>> + LPI_MUX_dmic3_data,
>> + LPI_MUX_i2s1_clk,
>> + LPI_MUX_i2s1_data,
>> + LPI_MUX_i2s1_ws,
>> + LPI_MUX_i2s2_clk,
>> + LPI_MUX_i2s2_data,
>> + LPI_MUX_i2s2_ws,
>> + LPI_MUX_qua_mi2s_data,
>> + LPI_MUX_qua_mi2s_sclk,
>> + LPI_MUX_qua_mi2s_ws,
>> + LPI_MUX_swr_rx_clk,
>> + LPI_MUX_swr_rx_data,
>> + LPI_MUX_swr_tx_clk,
>> + LPI_MUX_swr_tx_data,
>> + LPI_MUX_wsa_swr_clk,
>> + LPI_MUX_wsa_swr_data,
>> + LPI_MUX_gpio,
>> + LPI_MUX__,
>> +};
>> +
>> +static const unsigned int gpio0_pins[] = { 0 };
>> +static const unsigned int gpio1_pins[] = { 1 };
>> +static const unsigned int gpio2_pins[] = { 2 };
>> +static const unsigned int gpio3_pins[] = { 3 };
>> +static const unsigned int gpio4_pins[] = { 4 };
>> +static const unsigned int gpio5_pins[] = { 5 };
>> +static const unsigned int gpio6_pins[] = { 6 };
>> +static const unsigned int gpio7_pins[] = { 7 };
>> +static const unsigned int gpio8_pins[] = { 8 };
>> +static const unsigned int gpio9_pins[] = { 9 };
>> +static const unsigned int gpio10_pins[] = { 10 };
>> +static const unsigned int gpio11_pins[] = { 11 };
>> +static const unsigned int gpio12_pins[] = { 12 };
>> +static const unsigned int gpio13_pins[] = { 13 };
>> +
>> +/* sm8250 variant specific data */
>> +static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
>> + PINCTRL_PIN(0, "gpio0"),
>> + PINCTRL_PIN(1, "gpio1"),
>> + PINCTRL_PIN(2, "gpio2"),
>> + PINCTRL_PIN(3, "gpio3"),
>> + PINCTRL_PIN(4, "gpio4"),
>> + PINCTRL_PIN(5, "gpio5"),
>> + PINCTRL_PIN(6, "gpio6"),
>> + PINCTRL_PIN(7, "gpio7"),
>> + PINCTRL_PIN(8, "gpio8"),
>> + PINCTRL_PIN(9, "gpio9"),
>> + PINCTRL_PIN(10, "gpio10"),
>> + PINCTRL_PIN(11, "gpio11"),
>> + PINCTRL_PIN(12, "gpio12"),
>> + PINCTRL_PIN(13, "gpio13"),
>> +};
>> +
>> +static const char * const swr_tx_clk_groups[] = { "gpio0" };
>> +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
>> +static const char * const swr_rx_clk_groups[] = { "gpio3" };
>> +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
>> +static const char * const dmic1_clk_groups[] = { "gpio6" };
>> +static const char * const dmic1_data_groups[] = { "gpio7" };
>> +static const char * const dmic2_clk_groups[] = { "gpio8" };
>> +static const char * const dmic2_data_groups[] = { "gpio9" };
>> +static const char * const i2s2_clk_groups[] = { "gpio10" };
>> +static const char * const i2s2_ws_groups[] = { "gpio11" };
>> +static const char * const dmic3_clk_groups[] = { "gpio12" };
>> +static const char * const dmic3_data_groups[] = { "gpio13" };
>> +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
>> +static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
>> +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
>> +static const char * const i2s1_clk_groups[] = { "gpio6" };
>> +static const char * const i2s1_ws_groups[] = { "gpio7" };
>> +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
>> +static const char * const wsa_swr_clk_groups[] = { "gpio10" };
>> +static const char * const wsa_swr_data_groups[] = { "gpio11" };
>> +static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
>> +
>> +static const struct lpi_pingroup sm8250_groups[] = {
>> + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
>> + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
>> + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
>> + LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
>> + LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
>> + LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
>> + LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
>> + LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
>> + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
>> + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
>> + LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
>> + LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
>> +};
>> +
>> +static const struct lpi_function sm8250_functions[] = {
>> + LPI_FUNCTION(dmic1_clk),
>> + LPI_FUNCTION(dmic1_data),
>> + LPI_FUNCTION(dmic2_clk),
>> + LPI_FUNCTION(dmic2_data),
>> + LPI_FUNCTION(dmic3_clk),
>> + LPI_FUNCTION(dmic3_data),
>> + LPI_FUNCTION(i2s1_clk),
>> + LPI_FUNCTION(i2s1_data),
>> + LPI_FUNCTION(i2s1_ws),
>> + LPI_FUNCTION(i2s2_clk),
>> + LPI_FUNCTION(i2s2_data),
>> + LPI_FUNCTION(i2s2_ws),
>> + LPI_FUNCTION(qua_mi2s_data),
>> + LPI_FUNCTION(qua_mi2s_sclk),
>> + LPI_FUNCTION(qua_mi2s_ws),
>> + LPI_FUNCTION(swr_rx_clk),
>> + LPI_FUNCTION(swr_rx_data),
>> + LPI_FUNCTION(swr_tx_clk),
>> + LPI_FUNCTION(swr_tx_data),
>> + LPI_FUNCTION(wsa_swr_clk),
>> + LPI_FUNCTION(wsa_swr_data),
>> +};
>> +
>> +static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
>> + .pins = sm8250_lpi_pins,
>> + .npins = ARRAY_SIZE(sm8250_lpi_pins),
>> + .groups = sm8250_groups,
>> + .ngroups = ARRAY_SIZE(sm8250_groups),
>> + .functions = sm8250_functions,
>> + .nfunctions = ARRAY_SIZE(sm8250_functions),
>> +};
>> +
>> +static const struct of_device_id lpi_pinctrl_of_match[] = {
>> + {
>> + .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
>> + .data = &sm8250_lpi_data,
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
>> +
>> +static struct platform_driver lpi_pinctrl_driver = {
>> + .driver = {
>> + .name = "qcom-sm8250-lpass-lpi-pinctrl",
>> + .of_match_table = lpi_pinctrl_of_match,
>> + },
>> + .probe = lpi_pinctrl_probe,
>> + .remove = lpi_pinctrl_remove,
>> +};
>> +
>> +module_platform_driver(lpi_pinctrl_driver);
>> +MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
>> +MODULE_LICENSE("GPL");
>> +
> Unnecessary empty line.
>
> Thanks,
> Bjorn
>
>> --
>> Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
>> is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
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2021-12-03 11:32 [PATCH v4 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2021-12-03 11:32 ` [PATCH v4 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 23:34 ` Rob Herring
2021-12-03 23:34 ` Rob Herring
2021-12-03 11:32 ` [PATCH v4 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-03 23:34 ` Rob Herring
2021-12-03 23:34 ` Rob Herring
2021-12-03 11:32 ` [PATCH v4 3/5] pinctrl: qcom: Move chip specific functions to right files Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-04 21:26 ` kernel test robot
2021-12-06 16:32 ` Bjorn Andersson
2021-12-06 16:32 ` Bjorn Andersson
2021-12-07 15:21 ` Srinivasa Rao Mandadapu
2021-12-07 15:21 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` [PATCH v4 4/5] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-06 2:35 ` Bjorn Andersson
2021-12-06 2:35 ` Bjorn Andersson
2021-12-07 15:16 ` Srinivasa Rao Mandadapu
2021-12-07 15:16 ` Srinivasa Rao Mandadapu
2021-12-03 11:32 ` [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
2021-12-03 11:32 ` Srinivasa Rao Mandadapu
2021-12-06 16:25 ` Bjorn Andersson
2021-12-06 16:25 ` Bjorn Andersson
2021-12-07 15:19 ` Srinivasa Rao Mandadapu
2021-12-07 15:19 ` Srinivasa Rao Mandadapu
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