* [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring
@ 2021-12-09 18:21 Ville Syrjala
2021-12-09 18:21 ` [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets Ville Syrjala
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Ville Syrjala @ 2021-12-09 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
A bit more prep work towards multiple FBC instances.
One thing that is still up in the air is the debugfs
layout. Haven't relly figured out what the best approach
would be, and whatever is chosen does require igt changes
as well.
Ville Syrjälä (3):
drm/i915/fbc: Parametrize FBC register offsets
drm/i915/fbc: Loop through FBC instances in various places
drm/i915/fbc: Introduce device info fbc_mask
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 232 +++++++++++-------
drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
.../drm/i915/display/skl_universal_plane.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/i915_pci.c | 22 +-
drivers/gpu/drm/i915/i915_reg.h | 34 +--
drivers/gpu/drm/i915/intel_device_info.c | 4 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 31 ++-
10 files changed, 206 insertions(+), 144 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
@ 2021-12-09 18:21 ` Ville Syrjala
2021-12-10 10:57 ` Jani Nikula
2021-12-09 18:21 ` [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places Ville Syrjala
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-12-09 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Parametrize ilk+ FBC register offsets based on the FBC instance.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++++++++++++-----------
drivers/gpu/drm/i915/display/intel_fbc.h | 6 +++++
drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++------------
drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++---------
4 files changed, 60 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8be01b93015f..8376f819071e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -85,6 +85,8 @@ struct intel_fbc {
struct drm_mm_node compressed_fb;
struct drm_mm_node compressed_llb;
+ enum fbc_id id;
+
u8 limit;
bool false_color;
@@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
struct intel_fbc_state *fbc_state = &fbc->state;
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
+ intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
fbc_state->fence_y_offset);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
}
@@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
u32 dpfc_ctl;
/* Disable compression */
- dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
+ dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
if (dpfc_ctl & DPFC_CTL_EN) {
dpfc_ctl &= ~DPFC_CTL_EN;
- intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
}
}
static bool ilk_fbc_is_active(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+ return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
}
static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
}
static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
+ intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
}
static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
{
struct drm_i915_private *i915 = fbc->i915;
- intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
- intel_de_posting_read(i915, MSG_FBC_REND_STATE);
+ intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
+ intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
}
static const struct intel_fbc_funcs snb_fbc_funcs = {
@@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
val |= FBC_STRIDE_OVERRIDE |
FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
- intel_de_write(i915, GLK_FBC_STRIDE, val);
+ intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
}
static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
@@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
if (i915->ggtt.num_fences)
snb_fbc_program_fence(fbc);
- intel_de_write(i915, ILK_DPFC_CONTROL,
+ intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
}
static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
{
- return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
+ return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
}
static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
bool enable)
{
- intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
+ intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
}
@@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
}
-static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
+static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
+ enum fbc_id fbc_id)
{
struct intel_fbc *fbc;
@@ -1628,6 +1631,7 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
if (!fbc)
return NULL;
+ fbc->id = fbc_id;
fbc->i915 = i915;
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
mutex_init(&fbc->lock);
@@ -1671,7 +1675,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
if (!HAS_FBC(i915))
return;
- fbc = intel_fbc_create(i915);
+ fbc = intel_fbc_create(i915, FBC_A);
if (!fbc)
return;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index b8d9cda85cfc..6ea269866aeb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -18,6 +18,12 @@ struct intel_fbc;
struct intel_plane;
struct intel_plane_state;
+enum fbc_id {
+ FBC_A,
+
+ I915_MAX_FBCS,
+};
+
int intel_fbc_atomic_check(struct intel_atomic_state *state);
bool intel_fbc_pre_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d27ba273cc68..698a023e70f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3386,10 +3386,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define FBC_LL_SIZE (1536)
/* Framebuffer compression for GM45+ */
-#define DPFC_CB_BASE _MMIO(0x3200)
-#define ILK_DPFC_CB_BASE _MMIO(0x43200)
-#define DPFC_CONTROL _MMIO(0x3208)
-#define ILK_DPFC_CONTROL _MMIO(0x43208)
+#define DPFC_CB_BASE _MMIO(0x3200)
+#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
+#define DPFC_CONTROL _MMIO(0x3208)
+#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
#define DPFC_CTL_EN REG_BIT(31)
#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
@@ -3407,28 +3407,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
-#define DPFC_RECOMP_CTL _MMIO(0x320c)
-#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
+#define DPFC_RECOMP_CTL _MMIO(0x320c)
+#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
#define DPFC_RECOMP_STALL_EN REG_BIT(27)
#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
-#define DPFC_STATUS _MMIO(0x3210)
-#define ILK_DPFC_STATUS _MMIO(0x43210)
+#define DPFC_STATUS _MMIO(0x3210)
+#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
-#define DPFC_STATUS2 _MMIO(0x3214)
-#define ILK_DPFC_STATUS2 _MMIO(0x43214)
+#define DPFC_STATUS2 _MMIO(0x3214)
+#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
-#define DPFC_FENCE_YOFF _MMIO(0x3218)
-#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
-#define DPFC_CHICKEN _MMIO(0x3224)
-#define ILK_DPFC_CHICKEN _MMIO(0x43224)
+#define DPFC_FENCE_YOFF _MMIO(0x3218)
+#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
+#define DPFC_CHICKEN _MMIO(0x3224)
+#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
-#define GLK_FBC_STRIDE _MMIO(0x43228)
+#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
#define FBC_STRIDE_OVERRIDE REG_BIT(15)
#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
@@ -3471,9 +3471,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE (1 << 31)
-#define MSG_FBC_REND_STATE _MMIO(0x50380)
+#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
#define FBC_REND_NUKE REG_BIT(2)
-#define FBC_REND_CACHE_CLEAN REG_BIT(1)
+#define FBC_REND_CACHE_CLEAN REG_BIT(1)
/*
* GPIO regs
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 434b1f8b7fe3..ac285b3e179b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -160,8 +160,9 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcHighMemBwCorruptionAvoidance:bxt
* Display WA #0883: bxt
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_DISABLE_DUMMY0);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
+ DPFC_DISABLE_DUMMY0);
}
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7451,8 +7452,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
{
/* Wa_1409120013:icl,ehl */
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
- DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/*Wa_14010594013:icl, ehl */
intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
@@ -7464,7 +7465,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
/* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/* Wa_1409825376:tgl (pre-prod)*/
@@ -7549,8 +7550,9 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcNukeOnHostModify:cfl
* Display WA #0873: cfl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7582,8 +7584,9 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcNukeOnHostModify:kbl
* Display WA #0873: kbl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7609,15 +7612,17 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
* WaFbcNukeOnHostModify:skl
* Display WA #0873: skl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_NUKE_ON_ANY_MODIFICATION);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
+ DPFC_NUKE_ON_ANY_MODIFICATION);
/*
* WaFbcHighMemBwCorruptionAvoidance:skl
* Display WA #0883: skl
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
- DPFC_DISABLE_DUMMY0);
+ intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
+ intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
+ DPFC_DISABLE_DUMMY0);
}
static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
2021-12-09 18:21 ` [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets Ville Syrjala
@ 2021-12-09 18:21 ` Ville Syrjala
2021-12-10 11:03 ` Jani Nikula
2021-12-09 18:21 ` [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask Ville Syrjala
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-12-09 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Convert i915->fbc into an array in preparation for
multiple FBC instances, and loop through all instances
in all places where the caller does not know which
instance(s) (if any) are relevant. This is the case
for eg. frontbuffer tracking and FIFO underrun hadling.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 166 +++++++++++-------
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 +-
4 files changed, 104 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 85950ff67609..731f446bdf20 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return dev_priv->fbc;
+ return dev_priv->fbc[FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8376f819071e..2f1a72f98c4b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -49,6 +49,13 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
+#define for_each_fbc_id(__fbc_id) \
+ for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
+
+#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
+ for_each_fbc_id(__fbc_id) \
+ for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
+
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
void (*deactivate)(struct intel_fbc *fbc);
@@ -812,16 +819,16 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
void intel_fbc_cleanup(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
- if (!fbc)
- return;
+ for_each_intel_fbc(i915, fbc, fbc_id) {
+ mutex_lock(&fbc->lock);
+ __intel_fbc_cleanup_cfb(fbc);
+ mutex_unlock(&fbc->lock);
- mutex_lock(&fbc->lock);
- __intel_fbc_cleanup_cfb(fbc);
- mutex_unlock(&fbc->lock);
-
- kfree(fbc);
+ kfree(fbc);
+ }
}
static bool stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1307,36 +1314,39 @@ static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
return fbc->possible_framebuffer_bits;
}
+static void __intel_fbc_invalidate(struct intel_fbc *fbc,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
+{
+ if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
+ return;
+
+ mutex_lock(&fbc->lock);
+
+ fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
+
+ if (fbc->state.plane && fbc->busy_bits)
+ intel_fbc_deactivate(fbc, "frontbuffer write");
+
+ mutex_unlock(&fbc->lock);
+}
+
void intel_fbc_invalidate(struct drm_i915_private *i915,
unsigned int frontbuffer_bits,
enum fb_op_origin origin)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
- if (!fbc)
- return;
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
- if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
- return;
-
- mutex_lock(&fbc->lock);
-
- fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
-
- if (fbc->state.plane && fbc->busy_bits)
- intel_fbc_deactivate(fbc, "frontbuffer write");
-
- mutex_unlock(&fbc->lock);
}
-void intel_fbc_flush(struct drm_i915_private *i915,
- unsigned int frontbuffer_bits, enum fb_op_origin origin)
+static void __intel_fbc_flush(struct intel_fbc *fbc,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
-
mutex_lock(&fbc->lock);
fbc->busy_bits &= ~frontbuffer_bits;
@@ -1356,6 +1366,17 @@ void intel_fbc_flush(struct drm_i915_private *i915,
mutex_unlock(&fbc->lock);
}
+void intel_fbc_flush(struct drm_i915_private *i915,
+ unsigned int frontbuffer_bits,
+ enum fb_op_origin origin)
+{
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
+
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_flush(fbc, frontbuffer_bits, origin);
+}
+
int intel_fbc_atomic_check(struct intel_atomic_state *state)
{
struct intel_plane_state *plane_state;
@@ -1483,15 +1504,15 @@ void intel_fbc_update(struct intel_atomic_state *state,
*/
void intel_fbc_global_disable(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
- if (!fbc)
- return;
-
- mutex_lock(&fbc->lock);
- if (fbc->state.plane)
- __intel_fbc_disable(fbc);
- mutex_unlock(&fbc->lock);
+ for_each_intel_fbc(i915, fbc, fbc_id) {
+ mutex_lock(&fbc->lock);
+ if (fbc->state.plane)
+ __intel_fbc_disable(fbc);
+ mutex_unlock(&fbc->lock);
+ }
}
static void intel_fbc_underrun_work_fn(struct work_struct *work)
@@ -1516,19 +1537,9 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
mutex_unlock(&fbc->lock);
}
-/*
- * intel_fbc_reset_underrun - reset FBC fifo underrun status.
- * @i915: the i915 device
- *
- * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
- * want to re-enable FBC after an underrun to increase test coverage.
- */
-void intel_fbc_reset_underrun(struct drm_i915_private *i915)
+static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
{
- struct intel_fbc *fbc = i915->fbc;
-
- if (!fbc)
- return;
+ struct drm_i915_private *i915 = fbc->i915;
cancel_work_sync(&fbc->underrun_work);
@@ -1544,6 +1555,38 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915)
mutex_unlock(&fbc->lock);
}
+/*
+ * intel_fbc_reset_underrun - reset FBC fifo underrun status.
+ * @i915: the i915 device
+ *
+ * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
+ * want to re-enable FBC after an underrun to increase test coverage.
+ */
+void intel_fbc_reset_underrun(struct drm_i915_private *i915)
+{
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
+
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_reset_underrun(fbc);
+}
+
+static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
+{
+ /*
+ * There's no guarantee that underrun_detected won't be set to true
+ * right after this check and before the work is scheduled, but that's
+ * not a problem since we'll check it again under the work function
+ * while FBC is locked. This check here is just to prevent us from
+ * unnecessarily scheduling the work, and it relies on the fact that we
+ * never switch underrun_detect back to false after it's true.
+ */
+ if (READ_ONCE(fbc->underrun_detected))
+ return;
+
+ schedule_work(&fbc->underrun_work);
+}
+
/**
* intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
* @i915: i915 device
@@ -1560,21 +1603,11 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915)
*/
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
- if (!fbc)
- return;
-
- /* There's no guarantee that underrun_detected won't be set to true
- * right after this check and before the work is scheduled, but that's
- * not a problem since we'll check it again under the work function
- * while FBC is locked. This check here is just to prevent us from
- * unnecessarily scheduling the work, and it relies on the fact that we
- * never switch underrun_detect back to false after it's true. */
- if (READ_ONCE(fbc->underrun_detected))
- return;
-
- schedule_work(&fbc->underrun_work);
+ for_each_intel_fbc(i915, fbc, fbc_id)
+ __intel_fbc_handle_fifo_underrun_irq(fbc);
}
/*
@@ -1685,7 +1718,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
if (intel_fbc_hw_is_active(fbc))
intel_fbc_hw_deactivate(fbc);
- i915->fbc = fbc;
+ i915->fbc[fbc->id] = fbc;
}
static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -1778,8 +1811,9 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
void intel_fbc_debugfs_register(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc = i915->fbc;
+ struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
- if (fbc)
+ for_each_intel_fbc(i915, fbc, fbc_id)
intel_fbc_debugfs_add(fbc);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d5359cf3d270..9e31eb54b9f4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1829,7 +1829,7 @@ static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
- return dev_priv->fbc;
+ return dev_priv->fbc[FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0f54a69b11d..7ae62e8e6d02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -70,6 +70,7 @@
#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
+#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "display/intel_global_state.h"
#include "display/intel_gmbus.h"
@@ -749,7 +750,7 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
- struct intel_fbc *fbc;
+ struct intel_fbc *fbc[I915_MAX_FBCS];
struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
2021-12-09 18:21 ` [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets Ville Syrjala
2021-12-09 18:21 ` [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places Ville Syrjala
@ 2021-12-09 18:21 ` Ville Syrjala
2021-12-10 11:14 ` Jani Nikula
2021-12-10 7:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More multi-FBC refactoring Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjala @ 2021-12-09 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Declare which FBC instances are present via a fbc_mask
in device info. For the moment there is just the one.
TODO: Need to figure out how to expose multiple FBC
instances in debugs. Just different file names, or move
the files under some subdirectory (per-crtc maybe), or
something else? This will need igt changes as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 42 +++++++++++--------
.../drm/i915/display/skl_universal_plane.c | 12 +++---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 22 +++++-----
drivers/gpu/drm/i915/intel_device_info.c | 4 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +-
6 files changed, 48 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2f1a72f98c4b..359aa8389e5a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -49,11 +49,12 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
-#define for_each_fbc_id(__fbc_id) \
- for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
+#define for_each_fbc_id(__dev_priv, __fbc_id) \
+ for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
+ for_each_if(INTEL_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
- for_each_fbc_id(__fbc_id) \
+ for_each_fbc_id((__dev_priv), (__fbc_id)) \
for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
struct intel_fbc_funcs {
@@ -1693,32 +1694,35 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
*/
void intel_fbc_init(struct drm_i915_private *i915)
{
- struct intel_fbc *fbc;
+ enum fbc_id fbc_id;
if (!drm_mm_initialized(&i915->mm.stolen))
- mkwrite_device_info(i915)->display.has_fbc = false;
+ mkwrite_device_info(i915)->fbc_mask = 0;
if (need_fbc_vtd_wa(i915))
- mkwrite_device_info(i915)->display.has_fbc = false;
+ mkwrite_device_info(i915)->fbc_mask = 0;
i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
i915->params.enable_fbc);
- if (!HAS_FBC(i915))
- return;
+ for_each_fbc_id(i915, fbc_id) {
+ struct intel_fbc *fbc;
- fbc = intel_fbc_create(i915, FBC_A);
- if (!fbc)
- return;
+ fbc = intel_fbc_create(i915, fbc_id);
+ if (!fbc)
+ continue;
- /* We still don't have any sort of hardware state readout for FBC, so
- * deactivate it in case the BIOS activated it to make sure software
- * matches the hardware state. */
- if (intel_fbc_hw_is_active(fbc))
- intel_fbc_hw_deactivate(fbc);
+ /*
+ * We still don't have any sort of hardware state readout
+ * for FBC, so deactivate it in case the BIOS activated it
+ * to make sure software matches the hardware state.
+ */
+ if (intel_fbc_hw_is_active(fbc))
+ intel_fbc_hw_deactivate(fbc);
- i915->fbc[fbc->id] = fbc;
+ i915->fbc[fbc->id] = fbc;
+ }
}
static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -1814,6 +1818,10 @@ void intel_fbc_debugfs_register(struct drm_i915_private *i915)
struct intel_fbc *fbc;
enum fbc_id fbc_id;
+ /*
+ * FIXME: need to figure out how to name/place
+ * the debugfs files for each FBC instance.
+ */
for_each_intel_fbc(i915, fbc, fbc_id)
intel_fbc_debugfs_add(fbc);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9e31eb54b9f4..c8c96accf353 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1817,19 +1817,21 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
}
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum plane_id plane_id)
+ enum fbc_id fbc_id, enum plane_id plane_id)
{
- if (!HAS_FBC(dev_priv))
+ if ((INTEL_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
return false;
- return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
+ return plane_id == PLANE_PRIMARY;
}
static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
{
- if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
- return dev_priv->fbc[FBC_A];
+ enum fbc_id fbc_id = pipe - PIPE_A + FBC_A;
+
+ if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
+ return dev_priv->fbc[fbc_id];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ae62e8e6d02..11bf7f4dc12e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1495,7 +1495,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
-#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
+#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->fbc_mask != 0)
#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 708a23415e9c..c64cc276f169 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -214,13 +214,13 @@ static const struct intel_device_info i845g_info = {
static const struct intel_device_info i85x_info = {
I830_FEATURES,
PLATFORM(INTEL_I85X),
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
};
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
};
#define GEN3_FEATURES \
@@ -258,7 +258,7 @@ static const struct intel_device_info i915gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -283,7 +283,7 @@ static const struct intel_device_info i945gm_info = {
.display.has_overlay = 1,
.display.overlay_needs_physical = 1,
.display.supports_tv = 1,
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
.hws_needs_physical = 1,
.unfenced_needs_alignment = 1,
};
@@ -342,7 +342,7 @@ static const struct intel_device_info i965gm_info = {
GEN4_FEATURES,
PLATFORM(INTEL_I965GM),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
.display.has_overlay = 1,
.display.supports_tv = 1,
.hws_needs_physical = 1,
@@ -360,7 +360,7 @@ static const struct intel_device_info gm45_info = {
GEN4_FEATURES,
PLATFORM(INTEL_GM45),
.is_mobile = 1,
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
.display.supports_tv = 1,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
.gpu_reset_clobbers_display = false,
@@ -393,7 +393,7 @@ static const struct intel_device_info ilk_m_info = {
PLATFORM(INTEL_IRONLAKE),
.is_mobile = 1,
.has_rps = true,
- .display.has_fbc = 1,
+ .fbc_mask = BIT(FBC_A),
};
#define GEN6_FEATURES \
@@ -401,7 +401,7 @@ static const struct intel_device_info ilk_m_info = {
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .fbc_mask = BIT(FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -452,7 +452,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
.display.has_hotplug = 1, \
- .display.has_fbc = 1, \
+ .fbc_mask = BIT(FBC_A), \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
.has_coherent_ggtt = true, \
.has_llc = 1, \
@@ -693,7 +693,7 @@ static const struct intel_device_info skl_gt4_info = {
.has_64bit_reloc = 1, \
.display.has_ddi = 1, \
.display.has_fpga_dbg = 1, \
- .display.has_fbc = 1, \
+ .fbc_mask = BIT(FBC_A), \
.display.has_hdcp = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
@@ -948,7 +948,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_dp_mst = 1, \
.display.has_dsb = 1, \
.display.has_dsc = 1, \
- .display.has_fbc = 1, \
+ .fbc_mask = BIT(FBC_A), \
.display.has_fpga_dbg = 1, \
.display.has_hdcp = 1, \
.display.has_hotplug = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a3446a2abcb2..284a8aac51ed 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -328,6 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
"Display fused off, disabling\n");
info->pipe_mask = 0;
info->cpu_transcoder_mask = 0;
+ info->fbc_mask = 0;
} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
drm_info(&dev_priv->drm, "PipeC fused off\n");
info->pipe_mask &= ~BIT(PIPE_C);
@@ -339,6 +340,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
info->pipe_mask &= ~BIT(PIPE_A);
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+ info->fbc_mask &= ~BIT(FBC_A);
}
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
info->pipe_mask &= ~BIT(PIPE_B);
@@ -359,7 +361,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->display.has_hdcp = 0;
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
- info->display.has_fbc = 0;
+ info->fbc_mask = 0;
if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
info->display.has_dmc = 0;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 213ae2c07126..89712019f073 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -156,7 +156,6 @@ enum intel_ppgtt_type {
func(has_dp_mst); \
func(has_dsb); \
func(has_dsc); \
- func(has_fbc); \
func(has_fpga_dbg); \
func(has_gmch); \
func(has_hdcp); \
@@ -198,6 +197,7 @@ struct intel_device_info {
u8 pipe_mask;
u8 cpu_transcoder_mask;
+ u8 fbc_mask;
u8 abox_mask;
--
2.32.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More multi-FBC refactoring
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
` (2 preceding siblings ...)
2021-12-09 18:21 ` [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask Ville Syrjala
@ 2021-12-10 7:30 ` Patchwork
2021-12-10 7:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-12-10 7:30 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
62abcc4d9d95 drm/i915/fbc: Parametrize FBC register offsets
8d70368946f6 drm/i915/fbc: Loop through FBC instances in various places
-:38: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__fbc_id' - possible side-effects?
#38: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:52:
+#define for_each_fbc_id(__fbc_id) \
+ for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
-:41: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#41: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:55:
+#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
+ for_each_fbc_id(__fbc_id) \
+ for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__fbc_id' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:55:
+#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
+ for_each_fbc_id(__fbc_id) \
+ for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
-:111: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#111: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1344:
+
+}
total: 1 errors, 0 warnings, 3 checks, 256 lines checked
4de4d56f03ea drm/i915/fbc: Introduce device info fbc_mask
-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__fbc_id' - possible side-effects?
#29: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:52:
+#define for_each_fbc_id(__dev_priv, __fbc_id) \
+ for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
+ for_each_if(INTEL_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
total: 0 errors, 0 warnings, 1 checks, 231 lines checked
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: More multi-FBC refactoring
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
` (3 preceding siblings ...)
2021-12-10 7:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More multi-FBC refactoring Patchwork
@ 2021-12-10 7:31 ` Patchwork
2021-12-10 7:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-10 22:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-12-10 7:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: More multi-FBC refactoring
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
` (4 preceding siblings ...)
2021-12-10 7:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-12-10 7:59 ` Patchwork
2021-12-10 22:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-12-10 7:59 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7743 bytes --]
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10987 -> Patchwork_21810
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/index.html
Participating hosts (43 -> 36)
------------------------------
Additional (2): fi-apl-guc fi-pnv-d510
Missing (9): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_21810 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271]) +18 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@sync-gfx0.html
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][3] -> [INCOMPLETE][4] ([i915#4006])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-apl-guc/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-apl-guc/igt@gem_lmem_swapping@basic.html
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][7] ([i915#1610])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-apl-guc/igt@i915_hangman@error-state-basic.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][8] -> [INCOMPLETE][9] ([i915#3921])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][10] -> [DMESG-FAIL][11] ([i915#295])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][12] -> [DMESG-WARN][13] ([i915#295]) +10 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][14] ([fdo#109271]) +57 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][15] ([i915#2426] / [i915#4312])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-apl-guc/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][16] ([i915#2722] / [i915#4312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-u2: [FAIL][17] ([i915#1888]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-tgl-u2/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][19] ([i915#3970]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-n3050: [DMESG-FAIL][21] ([i915#2927] / [i915#3428]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][23] ([i915#4269]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [FAIL][25] ([i915#4547]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3970]: https://gitlab.freedesktop.org/drm/intel/issues/3970
[i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
Build changes
-------------
* Linux: CI_DRM_10987 -> Patchwork_21810
CI-20190529: 20190529
CI_DRM_10987: f23f5bbad359e45b00ea1622c96872a02cd6b30f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6305: 136258e86a093fdb50a7a341de1c09ac9a076fea @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21810: 4de4d56f03eaee9989b2d9048499c45e2696eaad @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4de4d56f03ea drm/i915/fbc: Introduce device info fbc_mask
8d70368946f6 drm/i915/fbc: Loop through FBC instances in various places
62abcc4d9d95 drm/i915/fbc: Parametrize FBC register offsets
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/index.html
[-- Attachment #2: Type: text/html, Size: 9050 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets
2021-12-09 18:21 ` [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets Ville Syrjala
@ 2021-12-10 10:57 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2021-12-10 10:57 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Parametrize ilk+ FBC register offsets based on the FBC instance.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++++++++++++-----------
> drivers/gpu/drm/i915/display/intel_fbc.h | 6 +++++
> drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++------------
> drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++---------
> 4 files changed, 60 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 8be01b93015f..8376f819071e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -85,6 +85,8 @@ struct intel_fbc {
> struct drm_mm_node compressed_fb;
> struct drm_mm_node compressed_llb;
>
> + enum fbc_id id;
> +
> u8 limit;
>
> bool false_color;
> @@ -454,10 +456,10 @@ static void ilk_fbc_activate(struct intel_fbc *fbc)
> struct intel_fbc_state *fbc_state = &fbc->state;
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, ILK_DPFC_FENCE_YOFF,
> + intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
> fbc_state->fence_y_offset);
>
> - intel_de_write(i915, ILK_DPFC_CONTROL,
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
> }
>
> @@ -467,28 +469,28 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc)
> u32 dpfc_ctl;
>
> /* Disable compression */
> - dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL);
> + dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
> if (dpfc_ctl & DPFC_CTL_EN) {
> dpfc_ctl &= ~DPFC_CTL_EN;
> - intel_de_write(i915, ILK_DPFC_CONTROL, dpfc_ctl);
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
> }
> }
>
> static bool ilk_fbc_is_active(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> + return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
> }
>
> static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_STATUS) & DPFC_COMP_SEG_MASK;
> + return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
> }
>
> static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
> + intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
> }
>
> static const struct intel_fbc_funcs ilk_fbc_funcs = {
> @@ -524,8 +526,8 @@ static void snb_fbc_nuke(struct intel_fbc *fbc)
> {
> struct drm_i915_private *i915 = fbc->i915;
>
> - intel_de_write(i915, MSG_FBC_REND_STATE, FBC_REND_NUKE);
> - intel_de_posting_read(i915, MSG_FBC_REND_STATE);
> + intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
> + intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
> }
>
> static const struct intel_fbc_funcs snb_fbc_funcs = {
> @@ -547,7 +549,7 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
> val |= FBC_STRIDE_OVERRIDE |
> FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
>
> - intel_de_write(i915, GLK_FBC_STRIDE, val);
> + intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
> }
>
> static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
> @@ -598,19 +600,19 @@ static void ivb_fbc_activate(struct intel_fbc *fbc)
> if (i915->ggtt.num_fences)
> snb_fbc_program_fence(fbc);
>
> - intel_de_write(i915, ILK_DPFC_CONTROL,
> + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
> DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
> }
>
> static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
> {
> - return intel_de_read(fbc->i915, ILK_DPFC_STATUS2) & DPFC_COMP_SEG_MASK_IVB;
> + return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
> }
>
> static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
> bool enable)
> {
> - intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL,
> + intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
> DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
> }
>
> @@ -1620,7 +1622,8 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> }
>
> -static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
> +static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
> + enum fbc_id fbc_id)
> {
> struct intel_fbc *fbc;
>
> @@ -1628,6 +1631,7 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915)
> if (!fbc)
> return NULL;
>
> + fbc->id = fbc_id;
> fbc->i915 = i915;
> INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
> mutex_init(&fbc->lock);
> @@ -1671,7 +1675,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
> if (!HAS_FBC(i915))
> return;
>
> - fbc = intel_fbc_create(i915);
> + fbc = intel_fbc_create(i915, FBC_A);
> if (!fbc)
> return;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index b8d9cda85cfc..6ea269866aeb 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -18,6 +18,12 @@ struct intel_fbc;
> struct intel_plane;
> struct intel_plane_state;
>
> +enum fbc_id {
enum intel_fbc_id
> + FBC_A,
Maybe INTEL_FBC_A?
Yeah, not in line with e.g. PIPE_A and friends, but perhaps that's a
historical mistake better not repeated?
> +
> + I915_MAX_FBCS,
> +};
> +
> int intel_fbc_atomic_check(struct intel_atomic_state *state);
> bool intel_fbc_pre_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d27ba273cc68..698a023e70f5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3386,10 +3386,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define FBC_LL_SIZE (1536)
>
> /* Framebuffer compression for GM45+ */
> -#define DPFC_CB_BASE _MMIO(0x3200)
> -#define ILK_DPFC_CB_BASE _MMIO(0x43200)
> -#define DPFC_CONTROL _MMIO(0x3208)
> -#define ILK_DPFC_CONTROL _MMIO(0x43208)
> +#define DPFC_CB_BASE _MMIO(0x3200)
> +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> +#define DPFC_CONTROL _MMIO(0x3208)
> +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> #define DPFC_CTL_EN REG_BIT(31)
> #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
> #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> @@ -3407,28 +3407,28 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
> #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
> -#define DPFC_RECOMP_CTL _MMIO(0x320c)
> -#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
> +#define DPFC_RECOMP_CTL _MMIO(0x320c)
> +#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
> #define DPFC_RECOMP_STALL_EN REG_BIT(27)
> #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
> #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
> -#define DPFC_STATUS _MMIO(0x3210)
> -#define ILK_DPFC_STATUS _MMIO(0x43210)
> +#define DPFC_STATUS _MMIO(0x3210)
> +#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
> #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
> #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
> -#define DPFC_STATUS2 _MMIO(0x3214)
> -#define ILK_DPFC_STATUS2 _MMIO(0x43214)
> +#define DPFC_STATUS2 _MMIO(0x3214)
> +#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
> #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
> -#define DPFC_FENCE_YOFF _MMIO(0x3218)
> -#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
> -#define DPFC_CHICKEN _MMIO(0x3224)
> -#define ILK_DPFC_CHICKEN _MMIO(0x43224)
> +#define DPFC_FENCE_YOFF _MMIO(0x3218)
> +#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
> +#define DPFC_CHICKEN _MMIO(0x3224)
> +#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
> #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
> #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
> #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
> #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
>
> -#define GLK_FBC_STRIDE _MMIO(0x43228)
> +#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
> #define FBC_STRIDE_OVERRIDE REG_BIT(15)
> #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> @@ -3471,9 +3471,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define IPS_CTL _MMIO(0x43408)
> #define IPS_ENABLE (1 << 31)
>
> -#define MSG_FBC_REND_STATE _MMIO(0x50380)
> +#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
> #define FBC_REND_NUKE REG_BIT(2)
> -#define FBC_REND_CACHE_CLEAN REG_BIT(1)
> +#define FBC_REND_CACHE_CLEAN REG_BIT(1)
>
> /*
> * GPIO regs
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 434b1f8b7fe3..ac285b3e179b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -160,8 +160,9 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> * WaFbcHighMemBwCorruptionAvoidance:bxt
> * Display WA #0883: bxt
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> - DPFC_DISABLE_DUMMY0);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
> + DPFC_DISABLE_DUMMY0);
> }
>
> static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7451,8 +7452,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> /* Wa_1409120013:icl,ehl */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
> - DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
> /*Wa_14010594013:icl, ehl */
> intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> @@ -7464,7 +7465,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
> if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
> /* Wa_1409825376:tgl (pre-prod)*/
> @@ -7549,8 +7550,9 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> * WaFbcNukeOnHostModify:cfl
> * Display WA #0873: cfl
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> - DPFC_NUKE_ON_ANY_MODIFICATION);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
> + DPFC_NUKE_ON_ANY_MODIFICATION);
> }
>
> static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7582,8 +7584,9 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> * WaFbcNukeOnHostModify:kbl
> * Display WA #0873: kbl
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> - DPFC_NUKE_ON_ANY_MODIFICATION);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
> + DPFC_NUKE_ON_ANY_MODIFICATION);
> }
>
> static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7609,15 +7612,17 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> * WaFbcNukeOnHostModify:skl
> * Display WA #0873: skl
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> - DPFC_NUKE_ON_ANY_MODIFICATION);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
> + DPFC_NUKE_ON_ANY_MODIFICATION);
>
> /*
> * WaFbcHighMemBwCorruptionAvoidance:skl
> * Display WA #0883: skl
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
> - DPFC_DISABLE_DUMMY0);
> + intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A),
> + intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN(FBC_A)) |
> + DPFC_DISABLE_DUMMY0);
> }
>
> static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places
2021-12-09 18:21 ` [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places Ville Syrjala
@ 2021-12-10 11:03 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2021-12-10 11:03 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Convert i915->fbc into an array in preparation for
> multiple FBC instances, and loop through all instances
> in all places where the caller does not know which
> instance(s) (if any) are relevant. This is the case
> for eg. frontbuffer tracking and FIFO underrun hadling.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 166 +++++++++++-------
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> 4 files changed, 104 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 85950ff67609..731f446bdf20 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
> enum i9xx_plane_id i9xx_plane)
> {
> if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
> - return dev_priv->fbc;
> + return dev_priv->fbc[FBC_A];
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 8376f819071e..2f1a72f98c4b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -49,6 +49,13 @@
> #include "intel_fbc.h"
> #include "intel_frontbuffer.h"
>
> +#define for_each_fbc_id(__fbc_id) \
> + for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
> +
> +#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
> + for_each_fbc_id(__fbc_id) \
> + for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
> +
> struct intel_fbc_funcs {
> void (*activate)(struct intel_fbc *fbc);
> void (*deactivate)(struct intel_fbc *fbc);
> @@ -812,16 +819,16 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>
> void intel_fbc_cleanup(struct drm_i915_private *i915)
> {
> - struct intel_fbc *fbc = i915->fbc;
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> - if (!fbc)
> - return;
> + for_each_intel_fbc(i915, fbc, fbc_id) {
> + mutex_lock(&fbc->lock);
> + __intel_fbc_cleanup_cfb(fbc);
> + mutex_unlock(&fbc->lock);
>
> - mutex_lock(&fbc->lock);
> - __intel_fbc_cleanup_cfb(fbc);
> - mutex_unlock(&fbc->lock);
> -
> - kfree(fbc);
> + kfree(fbc);
> + }
> }
>
> static bool stride_is_valid(const struct intel_plane_state *plane_state)
> @@ -1307,36 +1314,39 @@ static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
> return fbc->possible_framebuffer_bits;
> }
>
> +static void __intel_fbc_invalidate(struct intel_fbc *fbc,
> + unsigned int frontbuffer_bits,
> + enum fb_op_origin origin)
> +{
> + if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
> + return;
> +
> + mutex_lock(&fbc->lock);
> +
> + fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
> +
> + if (fbc->state.plane && fbc->busy_bits)
> + intel_fbc_deactivate(fbc, "frontbuffer write");
> +
> + mutex_unlock(&fbc->lock);
> +}
> +
> void intel_fbc_invalidate(struct drm_i915_private *i915,
> unsigned int frontbuffer_bits,
> enum fb_op_origin origin)
> {
> - struct intel_fbc *fbc = i915->fbc;
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> - if (!fbc)
> - return;
> + for_each_intel_fbc(i915, fbc, fbc_id)
> + __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
>
> - if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
> - return;
> -
> - mutex_lock(&fbc->lock);
> -
> - fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
> -
> - if (fbc->state.plane && fbc->busy_bits)
> - intel_fbc_deactivate(fbc, "frontbuffer write");
> -
> - mutex_unlock(&fbc->lock);
> }
>
> -void intel_fbc_flush(struct drm_i915_private *i915,
> - unsigned int frontbuffer_bits, enum fb_op_origin origin)
> +static void __intel_fbc_flush(struct intel_fbc *fbc,
> + unsigned int frontbuffer_bits,
> + enum fb_op_origin origin)
> {
> - struct intel_fbc *fbc = i915->fbc;
> -
> - if (!fbc)
> - return;
> -
> mutex_lock(&fbc->lock);
>
> fbc->busy_bits &= ~frontbuffer_bits;
> @@ -1356,6 +1366,17 @@ void intel_fbc_flush(struct drm_i915_private *i915,
> mutex_unlock(&fbc->lock);
> }
>
> +void intel_fbc_flush(struct drm_i915_private *i915,
> + unsigned int frontbuffer_bits,
> + enum fb_op_origin origin)
> +{
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
> +
> + for_each_intel_fbc(i915, fbc, fbc_id)
> + __intel_fbc_flush(fbc, frontbuffer_bits, origin);
> +}
> +
> int intel_fbc_atomic_check(struct intel_atomic_state *state)
> {
> struct intel_plane_state *plane_state;
> @@ -1483,15 +1504,15 @@ void intel_fbc_update(struct intel_atomic_state *state,
> */
> void intel_fbc_global_disable(struct drm_i915_private *i915)
> {
> - struct intel_fbc *fbc = i915->fbc;
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> - if (!fbc)
> - return;
> -
> - mutex_lock(&fbc->lock);
> - if (fbc->state.plane)
> - __intel_fbc_disable(fbc);
> - mutex_unlock(&fbc->lock);
> + for_each_intel_fbc(i915, fbc, fbc_id) {
> + mutex_lock(&fbc->lock);
> + if (fbc->state.plane)
> + __intel_fbc_disable(fbc);
> + mutex_unlock(&fbc->lock);
> + }
> }
>
> static void intel_fbc_underrun_work_fn(struct work_struct *work)
> @@ -1516,19 +1537,9 @@ static void intel_fbc_underrun_work_fn(struct work_struct *work)
> mutex_unlock(&fbc->lock);
> }
>
> -/*
> - * intel_fbc_reset_underrun - reset FBC fifo underrun status.
> - * @i915: the i915 device
> - *
> - * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
> - * want to re-enable FBC after an underrun to increase test coverage.
> - */
> -void intel_fbc_reset_underrun(struct drm_i915_private *i915)
> +static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
> {
> - struct intel_fbc *fbc = i915->fbc;
> -
> - if (!fbc)
> - return;
> + struct drm_i915_private *i915 = fbc->i915;
>
> cancel_work_sync(&fbc->underrun_work);
>
> @@ -1544,6 +1555,38 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915)
> mutex_unlock(&fbc->lock);
> }
>
> +/*
> + * intel_fbc_reset_underrun - reset FBC fifo underrun status.
> + * @i915: the i915 device
> + *
> + * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
> + * want to re-enable FBC after an underrun to increase test coverage.
> + */
> +void intel_fbc_reset_underrun(struct drm_i915_private *i915)
> +{
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
> +
> + for_each_intel_fbc(i915, fbc, fbc_id)
> + __intel_fbc_reset_underrun(fbc);
> +}
> +
> +static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
> +{
> + /*
> + * There's no guarantee that underrun_detected won't be set to true
> + * right after this check and before the work is scheduled, but that's
> + * not a problem since we'll check it again under the work function
> + * while FBC is locked. This check here is just to prevent us from
> + * unnecessarily scheduling the work, and it relies on the fact that we
> + * never switch underrun_detect back to false after it's true.
> + */
> + if (READ_ONCE(fbc->underrun_detected))
> + return;
> +
> + schedule_work(&fbc->underrun_work);
> +}
> +
> /**
> * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
> * @i915: i915 device
> @@ -1560,21 +1603,11 @@ void intel_fbc_reset_underrun(struct drm_i915_private *i915)
> */
> void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
> {
> - struct intel_fbc *fbc = i915->fbc;
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> - if (!fbc)
> - return;
> -
> - /* There's no guarantee that underrun_detected won't be set to true
> - * right after this check and before the work is scheduled, but that's
> - * not a problem since we'll check it again under the work function
> - * while FBC is locked. This check here is just to prevent us from
> - * unnecessarily scheduling the work, and it relies on the fact that we
> - * never switch underrun_detect back to false after it's true. */
> - if (READ_ONCE(fbc->underrun_detected))
> - return;
> -
> - schedule_work(&fbc->underrun_work);
> + for_each_intel_fbc(i915, fbc, fbc_id)
> + __intel_fbc_handle_fifo_underrun_irq(fbc);
> }
>
> /*
> @@ -1685,7 +1718,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
> if (intel_fbc_hw_is_active(fbc))
> intel_fbc_hw_deactivate(fbc);
>
> - i915->fbc = fbc;
> + i915->fbc[fbc->id] = fbc;
> }
>
> static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> @@ -1778,8 +1811,9 @@ static void intel_fbc_debugfs_add(struct intel_fbc *fbc)
>
> void intel_fbc_debugfs_register(struct drm_i915_private *i915)
> {
> - struct intel_fbc *fbc = i915->fbc;
> + struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> - if (fbc)
> + for_each_intel_fbc(i915, fbc, fbc_id)
> intel_fbc_debugfs_add(fbc);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index d5359cf3d270..9e31eb54b9f4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1829,7 +1829,7 @@ static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> {
> if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> - return dev_priv->fbc;
> + return dev_priv->fbc[FBC_A];
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a0f54a69b11d..7ae62e8e6d02 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -70,6 +70,7 @@
> #include "display/intel_dmc.h"
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_dsb.h"
> +#include "display/intel_fbc.h"
> #include "display/intel_frontbuffer.h"
> #include "display/intel_global_state.h"
> #include "display/intel_gmbus.h"
> @@ -749,7 +750,7 @@ struct drm_i915_private {
> u32 pipestat_irq_mask[I915_MAX_PIPES];
>
> struct i915_hotplug hotplug;
> - struct intel_fbc *fbc;
> + struct intel_fbc *fbc[I915_MAX_FBCS];
> struct i915_drrs drrs;
> struct intel_opregion opregion;
> struct intel_vbt_data vbt;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask
2021-12-09 18:21 ` [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask Ville Syrjala
@ 2021-12-10 11:14 ` Jani Nikula
2021-12-10 11:39 ` Ville Syrjälä
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2021-12-10 11:14 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Declare which FBC instances are present via a fbc_mask
> in device info. For the moment there is just the one.
>
> TODO: Need to figure out how to expose multiple FBC
> instances in debugs. Just different file names, or move
> the files under some subdirectory (per-crtc maybe), or
> something else? This will need igt changes as well.
I think I'd prefer moving under crtc subdirectory. That exposes the pipe
<-> fbc relationship in a natural way so that the userspace doesn't have
to know, right?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 42 +++++++++++--------
> .../drm/i915/display/skl_universal_plane.c | 12 +++---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 22 +++++-----
> drivers/gpu/drm/i915/intel_device_info.c | 4 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 6 files changed, 48 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 2f1a72f98c4b..359aa8389e5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -49,11 +49,12 @@
> #include "intel_fbc.h"
> #include "intel_frontbuffer.h"
>
> -#define for_each_fbc_id(__fbc_id) \
> - for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
> +#define for_each_fbc_id(__dev_priv, __fbc_id) \
> + for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
> + for_each_if(INTEL_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
>
> #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
> - for_each_fbc_id(__fbc_id) \
> + for_each_fbc_id((__dev_priv), (__fbc_id)) \
> for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
>
> struct intel_fbc_funcs {
> @@ -1693,32 +1694,35 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
> */
> void intel_fbc_init(struct drm_i915_private *i915)
> {
> - struct intel_fbc *fbc;
> + enum fbc_id fbc_id;
>
> if (!drm_mm_initialized(&i915->mm.stolen))
> - mkwrite_device_info(i915)->display.has_fbc = false;
> + mkwrite_device_info(i915)->fbc_mask = 0;
>
> if (need_fbc_vtd_wa(i915))
> - mkwrite_device_info(i915)->display.has_fbc = false;
> + mkwrite_device_info(i915)->fbc_mask = 0;
>
> i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
> drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> i915->params.enable_fbc);
>
> - if (!HAS_FBC(i915))
> - return;
> + for_each_fbc_id(i915, fbc_id) {
> + struct intel_fbc *fbc;
>
> - fbc = intel_fbc_create(i915, FBC_A);
> - if (!fbc)
> - return;
> + fbc = intel_fbc_create(i915, fbc_id);
> + if (!fbc)
> + continue;
>
> - /* We still don't have any sort of hardware state readout for FBC, so
> - * deactivate it in case the BIOS activated it to make sure software
> - * matches the hardware state. */
> - if (intel_fbc_hw_is_active(fbc))
> - intel_fbc_hw_deactivate(fbc);
> + /*
> + * We still don't have any sort of hardware state readout
> + * for FBC, so deactivate it in case the BIOS activated it
> + * to make sure software matches the hardware state.
> + */
> + if (intel_fbc_hw_is_active(fbc))
> + intel_fbc_hw_deactivate(fbc);
>
> - i915->fbc[fbc->id] = fbc;
> + i915->fbc[fbc->id] = fbc;
> + }
> }
>
> static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> @@ -1814,6 +1818,10 @@ void intel_fbc_debugfs_register(struct drm_i915_private *i915)
> struct intel_fbc *fbc;
> enum fbc_id fbc_id;
>
> + /*
> + * FIXME: need to figure out how to name/place
> + * the debugfs files for each FBC instance.
> + */
> for_each_intel_fbc(i915, fbc, fbc_id)
> intel_fbc_debugfs_add(fbc);
> }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9e31eb54b9f4..c8c96accf353 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1817,19 +1817,21 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> }
>
> static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
> - enum pipe pipe, enum plane_id plane_id)
> + enum fbc_id fbc_id, enum plane_id plane_id)
> {
> - if (!HAS_FBC(dev_priv))
> + if ((INTEL_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
> return false;
>
> - return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
> + return plane_id == PLANE_PRIMARY;
> }
>
> static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> {
> - if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> - return dev_priv->fbc[FBC_A];
> + enum fbc_id fbc_id = pipe - PIPE_A + FBC_A;
I think this is magic enough that a small intel_fbc_for_pipe() helper
would be in order. Maybe just locally here if that's the only place
where the info is needed.
> +
> + if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
> + return dev_priv->fbc[fbc_id];
> else
> return NULL;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7ae62e8e6d02..11bf7f4dc12e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1495,7 +1495,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
>
> #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
> -#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
> +#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->fbc_mask != 0)
> #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 708a23415e9c..c64cc276f169 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -214,13 +214,13 @@ static const struct intel_device_info i845g_info = {
> static const struct intel_device_info i85x_info = {
> I830_FEATURES,
> PLATFORM(INTEL_I85X),
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> };
>
> static const struct intel_device_info i865g_info = {
> I845_FEATURES,
> PLATFORM(INTEL_I865G),
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> };
>
> #define GEN3_FEATURES \
> @@ -258,7 +258,7 @@ static const struct intel_device_info i915gm_info = {
> .display.has_overlay = 1,
> .display.overlay_needs_physical = 1,
> .display.supports_tv = 1,
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -283,7 +283,7 @@ static const struct intel_device_info i945gm_info = {
> .display.has_overlay = 1,
> .display.overlay_needs_physical = 1,
> .display.supports_tv = 1,
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> .hws_needs_physical = 1,
> .unfenced_needs_alignment = 1,
> };
> @@ -342,7 +342,7 @@ static const struct intel_device_info i965gm_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_I965GM),
> .is_mobile = 1,
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> .display.has_overlay = 1,
> .display.supports_tv = 1,
> .hws_needs_physical = 1,
> @@ -360,7 +360,7 @@ static const struct intel_device_info gm45_info = {
> GEN4_FEATURES,
> PLATFORM(INTEL_GM45),
> .is_mobile = 1,
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> .display.supports_tv = 1,
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> .gpu_reset_clobbers_display = false,
> @@ -393,7 +393,7 @@ static const struct intel_device_info ilk_m_info = {
> PLATFORM(INTEL_IRONLAKE),
> .is_mobile = 1,
> .has_rps = true,
> - .display.has_fbc = 1,
> + .fbc_mask = BIT(FBC_A),
> };
>
> #define GEN6_FEATURES \
> @@ -401,7 +401,7 @@ static const struct intel_device_info ilk_m_info = {
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> .display.has_hotplug = 1, \
> - .display.has_fbc = 1, \
> + .fbc_mask = BIT(FBC_A), \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> @@ -452,7 +452,7 @@ static const struct intel_device_info snb_m_gt2_info = {
> .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> .display.has_hotplug = 1, \
> - .display.has_fbc = 1, \
> + .fbc_mask = BIT(FBC_A), \
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> @@ -693,7 +693,7 @@ static const struct intel_device_info skl_gt4_info = {
> .has_64bit_reloc = 1, \
> .display.has_ddi = 1, \
> .display.has_fpga_dbg = 1, \
> - .display.has_fbc = 1, \
> + .fbc_mask = BIT(FBC_A), \
> .display.has_hdcp = 1, \
> .display.has_psr = 1, \
> .display.has_psr_hw_tracking = 1, \
> @@ -948,7 +948,7 @@ static const struct intel_device_info adl_s_info = {
> .display.has_dp_mst = 1, \
> .display.has_dsb = 1, \
> .display.has_dsc = 1, \
> - .display.has_fbc = 1, \
> + .fbc_mask = BIT(FBC_A), \
> .display.has_fpga_dbg = 1, \
> .display.has_hdcp = 1, \
> .display.has_hotplug = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a3446a2abcb2..284a8aac51ed 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -328,6 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> "Display fused off, disabling\n");
> info->pipe_mask = 0;
> info->cpu_transcoder_mask = 0;
> + info->fbc_mask = 0;
> } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> drm_info(&dev_priv->drm, "PipeC fused off\n");
> info->pipe_mask &= ~BIT(PIPE_C);
> @@ -339,6 +340,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> info->pipe_mask &= ~BIT(PIPE_A);
> info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> + info->fbc_mask &= ~BIT(FBC_A);
> }
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> info->pipe_mask &= ~BIT(PIPE_B);
> @@ -359,7 +361,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> info->display.has_hdcp = 0;
>
> if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> - info->display.has_fbc = 0;
> + info->fbc_mask = 0;
>
> if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> info->display.has_dmc = 0;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 213ae2c07126..89712019f073 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
> func(has_dp_mst); \
> func(has_dsb); \
> func(has_dsc); \
> - func(has_fbc); \
> func(has_fpga_dbg); \
> func(has_gmch); \
> func(has_hdcp); \
> @@ -198,6 +197,7 @@ struct intel_device_info {
>
> u8 pipe_mask;
> u8 cpu_transcoder_mask;
> + u8 fbc_mask;
I'd rather we started moving these under the display substruct instead
of the other way round.
Apart from the nitpicks looks good,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
BR,
Jani.
>
> u8 abox_mask;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask
2021-12-10 11:14 ` Jani Nikula
@ 2021-12-10 11:39 ` Ville Syrjälä
2021-12-10 12:18 ` Jani Nikula
0 siblings, 1 reply; 13+ messages in thread
From: Ville Syrjälä @ 2021-12-10 11:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Dec 10, 2021 at 01:14:22PM +0200, Jani Nikula wrote:
> On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Declare which FBC instances are present via a fbc_mask
> > in device info. For the moment there is just the one.
> >
> > TODO: Need to figure out how to expose multiple FBC
> > instances in debugs. Just different file names, or move
> > the files under some subdirectory (per-crtc maybe), or
> > something else? This will need igt changes as well.
>
> I think I'd prefer moving under crtc subdirectory. That exposes the pipe
> <-> fbc relationship in a natural way so that the userspace doesn't have
> to know, right?
I suppose. Although on i965-ivb that means having the same FBC
instance visible in all crtc dirs. But I guess that should be fine.
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 42 +++++++++++--------
> > .../drm/i915/display/skl_universal_plane.c | 12 +++---
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_pci.c | 22 +++++-----
> > drivers/gpu/drm/i915/intel_device_info.c | 4 +-
> > drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> > 6 files changed, 48 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 2f1a72f98c4b..359aa8389e5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -49,11 +49,12 @@
> > #include "intel_fbc.h"
> > #include "intel_frontbuffer.h"
> >
> > -#define for_each_fbc_id(__fbc_id) \
> > - for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++)
> > +#define for_each_fbc_id(__dev_priv, __fbc_id) \
> > + for ((__fbc_id) = FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
> > + for_each_if(INTEL_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
> >
> > #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
> > - for_each_fbc_id(__fbc_id) \
> > + for_each_fbc_id((__dev_priv), (__fbc_id)) \
> > for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
> >
> > struct intel_fbc_funcs {
> > @@ -1693,32 +1694,35 @@ static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
> > */
> > void intel_fbc_init(struct drm_i915_private *i915)
> > {
> > - struct intel_fbc *fbc;
> > + enum fbc_id fbc_id;
> >
> > if (!drm_mm_initialized(&i915->mm.stolen))
> > - mkwrite_device_info(i915)->display.has_fbc = false;
> > + mkwrite_device_info(i915)->fbc_mask = 0;
> >
> > if (need_fbc_vtd_wa(i915))
> > - mkwrite_device_info(i915)->display.has_fbc = false;
> > + mkwrite_device_info(i915)->fbc_mask = 0;
> >
> > i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
> > drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> > i915->params.enable_fbc);
> >
> > - if (!HAS_FBC(i915))
> > - return;
> > + for_each_fbc_id(i915, fbc_id) {
> > + struct intel_fbc *fbc;
> >
> > - fbc = intel_fbc_create(i915, FBC_A);
> > - if (!fbc)
> > - return;
> > + fbc = intel_fbc_create(i915, fbc_id);
> > + if (!fbc)
> > + continue;
> >
> > - /* We still don't have any sort of hardware state readout for FBC, so
> > - * deactivate it in case the BIOS activated it to make sure software
> > - * matches the hardware state. */
> > - if (intel_fbc_hw_is_active(fbc))
> > - intel_fbc_hw_deactivate(fbc);
> > + /*
> > + * We still don't have any sort of hardware state readout
> > + * for FBC, so deactivate it in case the BIOS activated it
> > + * to make sure software matches the hardware state.
> > + */
> > + if (intel_fbc_hw_is_active(fbc))
> > + intel_fbc_hw_deactivate(fbc);
> >
> > - i915->fbc[fbc->id] = fbc;
> > + i915->fbc[fbc->id] = fbc;
> > + }
> > }
> >
> > static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> > @@ -1814,6 +1818,10 @@ void intel_fbc_debugfs_register(struct drm_i915_private *i915)
> > struct intel_fbc *fbc;
> > enum fbc_id fbc_id;
> >
> > + /*
> > + * FIXME: need to figure out how to name/place
> > + * the debugfs files for each FBC instance.
> > + */
> > for_each_intel_fbc(i915, fbc, fbc_id)
> > intel_fbc_debugfs_add(fbc);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 9e31eb54b9f4..c8c96accf353 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -1817,19 +1817,21 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
> > }
> >
> > static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
> > - enum pipe pipe, enum plane_id plane_id)
> > + enum fbc_id fbc_id, enum plane_id plane_id)
> > {
> > - if (!HAS_FBC(dev_priv))
> > + if ((INTEL_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
> > return false;
> >
> > - return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
> > + return plane_id == PLANE_PRIMARY;
> > }
> >
> > static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id)
> > {
> > - if (skl_plane_has_fbc(dev_priv, pipe, plane_id))
> > - return dev_priv->fbc[FBC_A];
> > + enum fbc_id fbc_id = pipe - PIPE_A + FBC_A;
>
> I think this is magic enough that a small intel_fbc_for_pipe() helper
> would be in order. Maybe just locally here if that's the only place
> where the info is needed.
Sure.
>
> > +
> > + if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
> > + return dev_priv->fbc[fbc_id];
> > else
> > return NULL;
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7ae62e8e6d02..11bf7f4dc12e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1495,7 +1495,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
> >
> > #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
> > -#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
> > +#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->fbc_mask != 0)
> > #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
> >
> > #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 708a23415e9c..c64cc276f169 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -214,13 +214,13 @@ static const struct intel_device_info i845g_info = {
> > static const struct intel_device_info i85x_info = {
> > I830_FEATURES,
> > PLATFORM(INTEL_I85X),
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > };
> >
> > static const struct intel_device_info i865g_info = {
> > I845_FEATURES,
> > PLATFORM(INTEL_I865G),
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > };
> >
> > #define GEN3_FEATURES \
> > @@ -258,7 +258,7 @@ static const struct intel_device_info i915gm_info = {
> > .display.has_overlay = 1,
> > .display.overlay_needs_physical = 1,
> > .display.supports_tv = 1,
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > .hws_needs_physical = 1,
> > .unfenced_needs_alignment = 1,
> > };
> > @@ -283,7 +283,7 @@ static const struct intel_device_info i945gm_info = {
> > .display.has_overlay = 1,
> > .display.overlay_needs_physical = 1,
> > .display.supports_tv = 1,
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > .hws_needs_physical = 1,
> > .unfenced_needs_alignment = 1,
> > };
> > @@ -342,7 +342,7 @@ static const struct intel_device_info i965gm_info = {
> > GEN4_FEATURES,
> > PLATFORM(INTEL_I965GM),
> > .is_mobile = 1,
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > .display.has_overlay = 1,
> > .display.supports_tv = 1,
> > .hws_needs_physical = 1,
> > @@ -360,7 +360,7 @@ static const struct intel_device_info gm45_info = {
> > GEN4_FEATURES,
> > PLATFORM(INTEL_GM45),
> > .is_mobile = 1,
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > .display.supports_tv = 1,
> > .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
> > .gpu_reset_clobbers_display = false,
> > @@ -393,7 +393,7 @@ static const struct intel_device_info ilk_m_info = {
> > PLATFORM(INTEL_IRONLAKE),
> > .is_mobile = 1,
> > .has_rps = true,
> > - .display.has_fbc = 1,
> > + .fbc_mask = BIT(FBC_A),
> > };
> >
> > #define GEN6_FEATURES \
> > @@ -401,7 +401,7 @@ static const struct intel_device_info ilk_m_info = {
> > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
> > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
> > .display.has_hotplug = 1, \
> > - .display.has_fbc = 1, \
> > + .fbc_mask = BIT(FBC_A), \
> > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> > .has_coherent_ggtt = true, \
> > .has_llc = 1, \
> > @@ -452,7 +452,7 @@ static const struct intel_device_info snb_m_gt2_info = {
> > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
> > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
> > .display.has_hotplug = 1, \
> > - .display.has_fbc = 1, \
> > + .fbc_mask = BIT(FBC_A), \
> > .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> > .has_coherent_ggtt = true, \
> > .has_llc = 1, \
> > @@ -693,7 +693,7 @@ static const struct intel_device_info skl_gt4_info = {
> > .has_64bit_reloc = 1, \
> > .display.has_ddi = 1, \
> > .display.has_fpga_dbg = 1, \
> > - .display.has_fbc = 1, \
> > + .fbc_mask = BIT(FBC_A), \
> > .display.has_hdcp = 1, \
> > .display.has_psr = 1, \
> > .display.has_psr_hw_tracking = 1, \
> > @@ -948,7 +948,7 @@ static const struct intel_device_info adl_s_info = {
> > .display.has_dp_mst = 1, \
> > .display.has_dsb = 1, \
> > .display.has_dsc = 1, \
> > - .display.has_fbc = 1, \
> > + .fbc_mask = BIT(FBC_A), \
> > .display.has_fpga_dbg = 1, \
> > .display.has_hdcp = 1, \
> > .display.has_hotplug = 1, \
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index a3446a2abcb2..284a8aac51ed 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -328,6 +328,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > "Display fused off, disabling\n");
> > info->pipe_mask = 0;
> > info->cpu_transcoder_mask = 0;
> > + info->fbc_mask = 0;
> > } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> > drm_info(&dev_priv->drm, "PipeC fused off\n");
> > info->pipe_mask &= ~BIT(PIPE_C);
> > @@ -339,6 +340,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
> > info->pipe_mask &= ~BIT(PIPE_A);
> > info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
> > + info->fbc_mask &= ~BIT(FBC_A);
> > }
> > if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> > info->pipe_mask &= ~BIT(PIPE_B);
> > @@ -359,7 +361,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
> > info->display.has_hdcp = 0;
> >
> > if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> > - info->display.has_fbc = 0;
> > + info->fbc_mask = 0;
> >
> > if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
> > info->display.has_dmc = 0;
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 213ae2c07126..89712019f073 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
> > func(has_dp_mst); \
> > func(has_dsb); \
> > func(has_dsc); \
> > - func(has_fbc); \
> > func(has_fpga_dbg); \
> > func(has_gmch); \
> > func(has_hdcp); \
> > @@ -198,6 +197,7 @@ struct intel_device_info {
> >
> > u8 pipe_mask;
> > u8 cpu_transcoder_mask;
> > + u8 fbc_mask;
>
> I'd rather we started moving these under the display substruct instead
> of the other way round.
I guess I could throw in a prep patch that moves the other masks there.
Just looked a bit funny having one mask in there and all the others not
there.
> Apart from the nitpicks looks good,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Ta
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask
2021-12-10 11:39 ` Ville Syrjälä
@ 2021-12-10 12:18 ` Jani Nikula
0 siblings, 0 replies; 13+ messages in thread
From: Jani Nikula @ 2021-12-10 12:18 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, 10 Dec 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Dec 10, 2021 at 01:14:22PM +0200, Jani Nikula wrote:
>> On Thu, 09 Dec 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> > index 213ae2c07126..89712019f073 100644
>> > --- a/drivers/gpu/drm/i915/intel_device_info.h
>> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> > @@ -156,7 +156,6 @@ enum intel_ppgtt_type {
>> > func(has_dp_mst); \
>> > func(has_dsb); \
>> > func(has_dsc); \
>> > - func(has_fbc); \
>> > func(has_fpga_dbg); \
>> > func(has_gmch); \
>> > func(has_hdcp); \
>> > @@ -198,6 +197,7 @@ struct intel_device_info {
>> >
>> > u8 pipe_mask;
>> > u8 cpu_transcoder_mask;
>> > + u8 fbc_mask;
>>
>> I'd rather we started moving these under the display substruct instead
>> of the other way round.
>
> I guess I could throw in a prep patch that moves the other masks there.
> Just looked a bit funny having one mask in there and all the others not
> there.
Yeah. Another angle is this runtime info thing and finally making the
device info truly const, removing the silly mkwrite_device_info(), and
making INTEL_INFO() point at rodata.
One plan that I've had is having something like this:
struct intel_device_info {
const struct intel_runtime_info *__initial_runtime_info;
/* ... */
};
and copying __initial_runtime_info to i915->__runtime.
The downside is that it probably ends up in a four-way split with
display/non-display and runtime/const.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: More multi-FBC refactoring
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
` (5 preceding siblings ...)
2021-12-10 7:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-12-10 22:00 ` Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2021-12-10 22:00 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30263 bytes --]
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10987_full -> Patchwork_21810_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21810_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21810_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21810_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_cursor@pipe-a-viewport-size-64:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-glk9/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-glk2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
Known issues
------------
Here are the changes found in Patchwork_21810_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-tglb8/igt@gem_eio@in-flight-contexts-10ms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063] / [i915#3648])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-tglb2/igt@gem_eio@unwedge-stress.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl4/igt@gem_exec_capture@pi@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl10/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb3/igt@gem_exec_fair@basic-pace@bcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb1/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#118])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-glk5/igt@gem_exec_whisper@basic-contexts-all.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-glk7/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_pxp@create-regular-context-1:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#4270])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@gem_pxp@create-regular-context-1.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#3297])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][24] ([i915#3318])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111644] / [i915#1397] / [i915#2411])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][26] -> [INCOMPLETE][27] ([i915#151])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl4/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl9/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-frame-dump:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +23 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +7 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl7/igt@kms_chamelium@vga-edid-read.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][35] ([i915#1319])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl3/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][36] ([i915#2105])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271]) +65 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109279] / [i915#3359])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-snb: [PASS][41] -> [SKIP][42] ([fdo#109271]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-snb5/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-snb6/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#3319])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-sliding.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][44] -> [FAIL][45] ([i915#72])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#2346])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][48] -> [FAIL][49] ([i915#2346])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-skl: [PASS][50] -> [FAIL][51] ([i915#2346] / [i915#533])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-busy-flip:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#111825]) +6 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@kms_flip@2x-busy-flip.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#79])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][55] ([i915#180]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][56] -> [FAIL][57] ([i915#2122])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [PASS][58] -> [SKIP][59] ([i915#3701])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs:
- shard-apl: NOTRUN -> [DMESG-WARN][60] ([i915#1226])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl6/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
- shard-kbl: NOTRUN -> [DMESG-WARN][61] ([i915#1226])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl2/igt@kms_flip_tiling@flip-change-tiling@dp-1-pipe-a-y-to-yf-ccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271]) +21 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271]) +287 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][64] -> [DMESG-WARN][65] ([i915#180]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][68] ([i915#265])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][69] ([i915#265])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-apl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][73] -> [SKIP][74] ([fdo#109441])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_selftest@all@check_plane_state:
- shard-tglb: NOTRUN -> [INCOMPLETE][75] ([i915#4663])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@kms_selftest@all@check_plane_state.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][76] -> [DMESG-WARN][77] ([i915#180] / [i915#295])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#533]) +4 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109291])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html
* igt@sysfs_clients@fair-3:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#2994])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb8/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@recycle:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2994]) +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@sysfs_clients@recycle.html
* igt@sysfs_timeslice_duration@timeout@rcs0:
- shard-skl: [PASS][83] -> [FAIL][84] ([i915#3259])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl4/igt@sysfs_timeslice_duration@timeout@rcs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl10/igt@sysfs_timeslice_duration@timeout@rcs0.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][85] ([i915#2481] / [i915#3070]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb6/igt@gem_eio@unwedge-stress.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb4/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [SKIP][87] ([fdo#109271]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][89] ([i915#2190]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-tglb3/igt@gem_huc_copy@huc-copy.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][91] ([i915#198]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl8/igt@gem_softpin@noreloc-s3.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl6/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_backlight@fade_with_dpms:
- {shard-rkl}: [SKIP][93] ([i915#3012]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@i915_pm_backlight@fade_with_dpms.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@i915_pm_backlight@fade_with_dpms.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][95] ([i915#4281]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][97] ([fdo#109308]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@i915_pm_rpm@system-suspend-modeset.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- {shard-rkl}: ([SKIP][99], [SKIP][100]) ([i915#1845]) -> [PASS][101]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_big_fb@linear-32bpp-rotate-0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: ([SKIP][102], [PASS][103]) ([i915#1845]) -> [PASS][104] +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-a-ctm-max:
- {shard-rkl}: ([PASS][105], [SKIP][106]) ([i915#1149] / [i915#4098]) -> [PASS][107] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-6/igt@kms_color@pipe-a-ctm-max.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_color@pipe-a-ctm-max.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_color@pipe-a-ctm-max.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [DMESG-WARN][108] ([i915#1982]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-skl1/igt@kms_color@pipe-b-ctm-0-75.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-skl8/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_color@pipe-b-gamma:
- {shard-rkl}: ([SKIP][110], [SKIP][111]) ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][112]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_color@pipe-b-gamma.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_color@pipe-b-gamma.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_color@pipe-b-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- {shard-rkl}: ([SKIP][113], [SKIP][114]) ([fdo#112022] / [i915#4070]) -> [PASS][115]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen:
- {shard-rkl}: [SKIP][116] ([fdo#112022]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x128-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-random:
- {shard-rkl}: [SKIP][118] ([fdo#112022] / [i915#4070]) -> [PASS][119] +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent:
- {shard-rkl}: ([PASS][120], [SKIP][121]) ([fdo#112022]) -> [PASS][122] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-alpha-transparent.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge:
- shard-kbl: [FAIL][123] ([i915#3435]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl1/igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl2/igt@kms_cursor_edge_walk@pipe-a-128x128-right-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- {shard-rkl}: ([SKIP][125], [SKIP][126]) ([fdo#111825] / [i915#4070]) -> [PASS][127]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
- {shard-rkl}: [SKIP][128] ([fdo#111825] / [i915#4070]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][130] ([i915#180] / [i915#636]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-iclb: [SKIP][132] ([i915#3701]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: ([PASS][134], [SKIP][135]) ([i915#4098]) -> [PASS][136] +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][137] ([i915#4098]) -> [PASS][138] +4 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt:
- {shard-rkl}: [SKIP][139] ([i915#1849]) -> [PASS][140] +2 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
* igt@kms_invalid_mode@bad-vsync-end:
- {shard-rkl}: [SKIP][141] ([i915#4278]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-1/igt@kms_invalid_mode@bad-vsync-end.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/shard-rkl-6/igt@kms_invalid_mode@bad-vsync-end.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- {shard-rkl}: ([SKIP][143], [SKIP][144]) ([i915#1849] / [i915#4098]) -> [PASS][145] +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10987/shard-rkl-4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/C
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21810/index.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-12-10 22:00 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-09 18:21 [Intel-gfx] [PATCH 0/3] drm/i915/fbc: More multi-FBC refactoring Ville Syrjala
2021-12-09 18:21 ` [Intel-gfx] [PATCH 1/3] drm/i915/fbc: Parametrize FBC register offsets Ville Syrjala
2021-12-10 10:57 ` Jani Nikula
2021-12-09 18:21 ` [Intel-gfx] [PATCH 2/3] drm/i915/fbc: Loop through FBC instances in various places Ville Syrjala
2021-12-10 11:03 ` Jani Nikula
2021-12-09 18:21 ` [Intel-gfx] [PATCH 3/3] drm/i915/fbc: Introduce device info fbc_mask Ville Syrjala
2021-12-10 11:14 ` Jani Nikula
2021-12-10 11:39 ` Ville Syrjälä
2021-12-10 12:18 ` Jani Nikula
2021-12-10 7:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: More multi-FBC refactoring Patchwork
2021-12-10 7:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-12-10 7:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-12-10 22:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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