* [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*
@ 2022-01-12 11:17 Jani Nikula
2022-01-12 13:57 ` Ville Syrjälä
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jani Nikula @ 2022-01-12 11:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Prefer acronym-based naming to be in line with the rest of the driver.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 13 +++-----
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++---------
drivers/gpu/drm/i915/display/intel_display.c | 6 ++--
.../drm/i915/display/intel_display_power.c | 11 +++----
drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 8 ++---
drivers/gpu/drm/i915/gt/intel_llc.c | 9 +++---
drivers/gpu/drm/i915/gt/intel_rc6.c | 5 ++-
drivers/gpu/drm/i915/gt/intel_rps.c | 8 ++---
drivers/gpu/drm/i915/gt/selftest_llc.c | 5 ++-
drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++-
drivers/gpu/drm/i915/intel_dram.c | 6 ++--
drivers/gpu/drm/i915/intel_pcode.c | 31 +++++++------------
drivers/gpu/drm/i915/intel_pcode.h | 12 +++----
drivers/gpu/drm/i915/intel_pm.c | 20 ++++++------
15 files changed, 70 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 2da4aacc956b..c35bad21b657 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -75,10 +75,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
u16 dclk;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
- &val, &val2);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
+ &val, &val2);
if (ret)
return ret;
@@ -102,10 +101,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
int ret;
int i;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1f13398e8ac2..7e20967307df 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -805,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- ret = sandybridge_pcode_write(dev_priv,
- BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+ ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
drm_err(&dev_priv->drm,
"failed to inform pcode about cdclk change\n");
@@ -834,8 +833,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
- sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level);
+ snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level);
intel_de_write(dev_priv, CDCLK_FREQ,
DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1138,8 +1137,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_posting_read(dev_priv, CDCLK_CTL);
/* inform PCU of the change */
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
intel_update_cdclk(dev_priv);
}
@@ -1717,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* BSpec requires us to wait up to 150usec, but that leads to
* timeouts; the 2ms used here is based on experiment.
*/
- ret = sandybridge_pcode_write_timeout(dev_priv,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 150, 2);
-
+ ret = snb_pcode_write_timeout(dev_priv,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 150, 2);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
@@ -1781,8 +1779,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
if (DISPLAY_VER(dev_priv) >= 11) {
- ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
} else {
/*
* The timeout isn't specified, the 2ms used here is based on
@@ -1790,10 +1788,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* FIXME: Waiting for the request completion could be delayed
* until the next PCODE request based on BSpec.
*/
- ret = sandybridge_pcode_write_timeout(dev_priv,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level,
- 150, 2);
+ ret = snb_pcode_write_timeout(dev_priv,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level,
+ 150, 2);
}
if (ret) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf7ce684dd8e..01e9b5baecd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1118,8 +1118,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
if (IS_BROADWELL(dev_priv)) {
- drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
- IPS_ENABLE | IPS_PCODE_CONTROL));
+ drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
+ IPS_ENABLE | IPS_PCODE_CONTROL));
/* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
* mailbox." Moreover, the mailbox may return a bogus state,
@@ -1149,7 +1149,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
if (IS_BROADWELL(dev_priv)) {
drm_WARN_ON(dev,
- sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
+ snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fba35fb6d2df..ee4617299e64 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -683,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
int ret, tries = 0;
while (1) {
- ret = sandybridge_pcode_write_timeout(i915,
- ICL_PCODE_EXIT_TCCOLD,
- 0, 250, 1);
+ ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+ 250, 1);
if (ret != -EAGAIN || ++tries == 3)
break;
msleep(1);
@@ -4053,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
* Spec states that we should timeout the request after 200us
* but the function below will timeout after 500us
*/
- ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
- &high_val);
+ ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
if (ret == 0) {
if (block &&
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
@@ -5469,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
- if (sandybridge_pcode_write(dev_priv,
- GEN6_PCODE_WRITE_D_COMP, val))
+ if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
drm_dbg_kms(&dev_priv->drm,
"Failed to write to D_COMP\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4509fe7438e8..e1ecf38db0ef 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
* Mailbox interface.
*/
if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
- ret = sandybridge_pcode_write(dev_priv,
- SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to initiate HDCP key load (%d)\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 404dfa7673c6..6c5c1d0363bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -134,8 +134,7 @@ static int gen6_drpc(struct seq_file *m)
}
if (GRAPHICS_VER(i915) <= 7)
- sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
- &rc6vids, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -557,9 +556,8 @@ static int llc_show(struct seq_file *m, void *data)
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
- sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &ia_freq, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(rps,
(gpu_freq *
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 08d7d5ae263a..63f18830c611 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -140,11 +140,10 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
unsigned int ia_freq, ring_freq;
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
- sandybridge_pcode_write(i915,
- GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
- ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
- ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
- gpu_freq);
+ snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+ ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
+ ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
+ gpu_freq);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 31ebe3f1765d..bb0d6e363f5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -268,8 +268,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_HW_ENABLE;
rc6vids = 0;
- ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
- &rc6vids, NULL);
+ ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
if (GRAPHICS_VER(i915) == 6 && ret) {
drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
} else if (GRAPHICS_VER(i915) == 6 &&
@@ -279,7 +278,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
rc6vids &= 0xffff00;
rc6vids |= GEN6_ENCODE_RC6_VID(450);
- ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+ ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
if (ret)
drm_err(&i915->drm,
"Couldn't fix incorrect rc6 voltage\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index bd35e45d3aaa..8a13bc005b45 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1091,9 +1091,8 @@ static void gen6_rps_init(struct intel_rps *rps)
IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
u32 ddcc_status = 0;
- if (sandybridge_pcode_read(i915,
- HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
- &ddcc_status, NULL) == 0)
+ if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ &ddcc_status, NULL) == 0)
rps->efficient_freq =
clamp_t(u8,
(ddcc_status >> 8) & 0xff,
@@ -1941,8 +1940,7 @@ void intel_rps_init(struct intel_rps *rps)
if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
u32 params = 0;
- sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
- ¶ms, NULL);
+ snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
if (params & BIT(31)) { /* OC supported */
drm_dbg(&i915->drm,
"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index 459b775f163a..2cd184ab32b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -31,9 +31,8 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
val = gpu_freq;
- if (sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &val, NULL)) {
+ if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &val, NULL)) {
pr_err("Failed to read freq table[%d], range [%d, %d]\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
err = -ENXIO;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index bd170ba1cf00..e1e5dd5f7638 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -519,9 +519,8 @@ static void show_pcu_config(struct intel_rps *rps)
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
int ia_freq = gpu_freq;
- sandybridge_pcode_read(i915,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &ia_freq, NULL);
+ snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &ia_freq, NULL);
pr_info("%5d %5d %5d\n",
gpu_freq * 50,
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 84bb212bae4b..3e26ccabf7f9 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -389,10 +389,8 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index e8c886e4e78d..db4403f63cac 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -51,11 +51,10 @@ static int gen7_check_mailbox_status(u32 mbox)
}
}
-static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
- u32 mbox, u32 *val, u32 *val1,
- int fast_timeout_us,
- int slow_timeout_ms,
- bool is_read)
+static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
+ u32 *val, u32 *val1,
+ int fast_timeout_us, int slow_timeout_ms,
+ bool is_read)
{
struct intel_uncore *uncore = &i915->uncore;
@@ -94,15 +93,12 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
return gen6_check_mailbox_status(mbox);
}
-int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
- u32 *val, u32 *val1)
+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
{
int err;
mutex_lock(&i915->sb_lock);
- err = __sandybridge_pcode_rw(i915, mbox, val, val1,
- 500, 20,
- true);
+ err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
mutex_unlock(&i915->sb_lock);
if (err) {
@@ -114,17 +110,14 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
return err;
}
-int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
- u32 mbox, u32 val,
- int fast_timeout_us,
- int slow_timeout_ms)
+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+ int fast_timeout_us, int slow_timeout_ms)
{
int err;
mutex_lock(&i915->sb_lock);
- err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
- fast_timeout_us, slow_timeout_ms,
- false);
+ err = __snb_pcode_rw(i915, mbox, &val, NULL,
+ fast_timeout_us, slow_timeout_ms, false);
mutex_unlock(&i915->sb_lock);
if (err) {
@@ -140,9 +133,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
- *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
- 500, 0,
- true);
+ *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
return *status || ((request & reply_mask) == reply);
}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 50806649d4b6..0962a17fac48 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -10,13 +10,11 @@
struct drm_i915_private;
-int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
- u32 *val, u32 *val1);
-int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
- u32 val, int fast_timeout_us,
- int slow_timeout_ms);
-#define sandybridge_pcode_write(i915, mbox, val) \
- sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
+int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
+int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+ int fast_timeout_us, int slow_timeout_ms);
+#define snb_pcode_write(i915, mbox, val) \
+ snb_pcode_write_timeout(i915, mbox, val, 500, 0)
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4ecd995c5cc7..9eec905545b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2890,9 +2890,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- ret = sandybridge_pcode_read(dev_priv,
- GEN9_PCODE_READ_MEM_LATENCY,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ &val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
@@ -2910,9 +2909,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- ret = sandybridge_pcode_read(dev_priv,
- GEN9_PCODE_READ_MEM_LATENCY,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ &val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
"SKL Mailbox read error = %d\n", ret);
@@ -3702,9 +3700,9 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = sandybridge_pcode_read(dev_priv,
- GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
- &val, NULL);
+ ret = snb_pcode_read(dev_priv,
+ GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+ &val, NULL);
if (!ret) {
dev_priv->sagv_block_time_us = val;
return;
@@ -3751,8 +3749,8 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
return 0;
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
- ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
- GEN9_SAGV_ENABLE);
+ ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
--
2.30.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*
2022-01-12 11:17 [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* Jani Nikula
@ 2022-01-12 13:57 ` Ville Syrjälä
2022-01-13 13:24 ` Jani Nikula
2022-01-12 14:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2) Patchwork
2022-01-12 19:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2022-01-12 13:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 12, 2022 at 01:17:40PM +0200, Jani Nikula wrote:
> Prefer acronym-based naming to be in line with the rest of the driver.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 13 +++-----
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++---------
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++--
> .../drm/i915/display/intel_display_power.c | 11 +++----
> drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 8 ++---
> drivers/gpu/drm/i915/gt/intel_llc.c | 9 +++---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 ++-
> drivers/gpu/drm/i915/gt/intel_rps.c | 8 ++---
> drivers/gpu/drm/i915/gt/selftest_llc.c | 5 ++-
> drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++-
> drivers/gpu/drm/i915/intel_dram.c | 6 ++--
> drivers/gpu/drm/i915/intel_pcode.c | 31 +++++++------------
> drivers/gpu/drm/i915/intel_pcode.h | 12 +++----
> drivers/gpu/drm/i915/intel_pm.c | 20 ++++++------
> 15 files changed, 70 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 2da4aacc956b..c35bad21b657 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -75,10 +75,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> u16 dclk;
> int ret;
>
> - ret = sandybridge_pcode_read(dev_priv,
> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> - &val, &val2);
> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> + &val, &val2);
> if (ret)
> return ret;
>
> @@ -102,10 +101,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
> int ret;
> int i;
>
> - ret = sandybridge_pcode_read(dev_priv,
> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
> - &val, NULL);
> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 1f13398e8ac2..7e20967307df 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -805,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> "trying to change cdclk frequency with cdclk not enabled\n"))
> return;
>
> - ret = sandybridge_pcode_write(dev_priv,
> - BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> + ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> if (ret) {
> drm_err(&dev_priv->drm,
> "failed to inform pcode about cdclk change\n");
> @@ -834,8 +833,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
> LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
>
> - sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> - cdclk_config->voltage_level);
> + snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> + cdclk_config->voltage_level);
>
> intel_de_write(dev_priv, CDCLK_FREQ,
> DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1138,8 +1137,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> intel_de_posting_read(dev_priv, CDCLK_CTL);
>
> /* inform PCU of the change */
> - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_config->voltage_level);
> + snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_config->voltage_level);
>
> intel_update_cdclk(dev_priv);
> }
> @@ -1717,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> * BSpec requires us to wait up to 150usec, but that leads to
> * timeouts; the 2ms used here is based on experiment.
> */
> - ret = sandybridge_pcode_write_timeout(dev_priv,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - 0x80000000, 150, 2);
> -
> + ret = snb_pcode_write_timeout(dev_priv,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + 0x80000000, 150, 2);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> @@ -1781,8 +1779,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> - ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_config->voltage_level);
> + ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_config->voltage_level);
> } else {
> /*
> * The timeout isn't specified, the 2ms used here is based on
> @@ -1790,10 +1788,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> * FIXME: Waiting for the request completion could be delayed
> * until the next PCODE request based on BSpec.
> */
> - ret = sandybridge_pcode_write_timeout(dev_priv,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - cdclk_config->voltage_level,
> - 150, 2);
> + ret = snb_pcode_write_timeout(dev_priv,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + cdclk_config->voltage_level,
> + 150, 2);
> }
>
> if (ret) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bf7ce684dd8e..01e9b5baecd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1118,8 +1118,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
> drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
>
> if (IS_BROADWELL(dev_priv)) {
> - drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> - IPS_ENABLE | IPS_PCODE_CONTROL));
> + drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> + IPS_ENABLE | IPS_PCODE_CONTROL));
> /* Quoting Art Runyan: "its not safe to expect any particular
> * value in IPS_CTL bit 31 after enabling IPS through the
> * mailbox." Moreover, the mailbox may return a bogus state,
> @@ -1149,7 +1149,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
>
> if (IS_BROADWELL(dev_priv)) {
> drm_WARN_ON(dev,
> - sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> + snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> /*
> * Wait for PCODE to finish disabling IPS. The BSpec specified
> * 42ms timeout value leads to occasional timeouts so use 100ms
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index fba35fb6d2df..ee4617299e64 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -683,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
> int ret, tries = 0;
>
> while (1) {
> - ret = sandybridge_pcode_write_timeout(i915,
> - ICL_PCODE_EXIT_TCCOLD,
> - 0, 250, 1);
> + ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
> + 250, 1);
> if (ret != -EAGAIN || ++tries == 3)
> break;
> msleep(1);
> @@ -4053,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> * Spec states that we should timeout the request after 200us
> * but the function below will timeout after 500us
> */
> - ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
> - &high_val);
> + ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
> if (ret == 0) {
> if (block &&
> (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> @@ -5469,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
> {
> if (IS_HASWELL(dev_priv)) {
> - if (sandybridge_pcode_write(dev_priv,
> - GEN6_PCODE_WRITE_D_COMP, val))
> + if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
> drm_dbg_kms(&dev_priv->drm,
> "Failed to write to D_COMP\n");
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 4509fe7438e8..e1ecf38db0ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
> * Mailbox interface.
> */
> if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
> - ret = sandybridge_pcode_write(dev_priv,
> - SKL_PCODE_LOAD_HDCP_KEYS, 1);
> + ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
> if (ret) {
> drm_err(&dev_priv->drm,
> "Failed to initiate HDCP key load (%d)\n",
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 404dfa7673c6..6c5c1d0363bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -134,8 +134,7 @@ static int gen6_drpc(struct seq_file *m)
> }
>
> if (GRAPHICS_VER(i915) <= 7)
> - sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> - &rc6vids, NULL);
> + snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
>
> seq_printf(m, "RC1e Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> @@ -557,9 +556,8 @@ static int llc_show(struct seq_file *m, void *data)
> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
> for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
> ia_freq = gpu_freq;
> - sandybridge_pcode_read(i915,
> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
> - &ia_freq, NULL);
> + snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
> + &ia_freq, NULL);
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(rps,
> (gpu_freq *
> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
> index 08d7d5ae263a..63f18830c611 100644
> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> @@ -140,11 +140,10 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
> unsigned int ia_freq, ring_freq;
>
> calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
> - sandybridge_pcode_write(i915,
> - GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
> - ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
> - ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
> - gpu_freq);
> + snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
> + ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
> + ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
> + gpu_freq);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 31ebe3f1765d..bb0d6e363f5d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -268,8 +268,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> GEN6_RC_CTL_HW_ENABLE;
>
> rc6vids = 0;
> - ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> - &rc6vids, NULL);
> + ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
> if (GRAPHICS_VER(i915) == 6 && ret) {
> drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
> } else if (GRAPHICS_VER(i915) == 6 &&
> @@ -279,7 +278,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
> rc6vids &= 0xffff00;
> rc6vids |= GEN6_ENCODE_RC6_VID(450);
> - ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
> + ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
> if (ret)
> drm_err(&i915->drm,
> "Couldn't fix incorrect rc6 voltage\n");
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index bd35e45d3aaa..8a13bc005b45 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1091,9 +1091,8 @@ static void gen6_rps_init(struct intel_rps *rps)
> IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
> u32 ddcc_status = 0;
>
> - if (sandybridge_pcode_read(i915,
> - HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
> - &ddcc_status, NULL) == 0)
> + if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
> + &ddcc_status, NULL) == 0)
> rps->efficient_freq =
> clamp_t(u8,
> (ddcc_status >> 8) & 0xff,
> @@ -1941,8 +1940,7 @@ void intel_rps_init(struct intel_rps *rps)
> if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> u32 params = 0;
>
> - sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
> - ¶ms, NULL);
> + snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
> if (params & BIT(31)) { /* OC supported */
> drm_dbg(&i915->drm,
> "Overclocking supported, max: %dMHz, overclock: %dMHz\n",
> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
> index 459b775f163a..2cd184ab32b1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
> @@ -31,9 +31,8 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
>
> val = gpu_freq;
> - if (sandybridge_pcode_read(i915,
> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
> - &val, NULL)) {
> + if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
> + &val, NULL)) {
> pr_err("Failed to read freq table[%d], range [%d, %d]\n",
> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
> err = -ENXIO;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> index bd170ba1cf00..e1e5dd5f7638 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> @@ -519,9 +519,8 @@ static void show_pcu_config(struct intel_rps *rps)
> for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
> int ia_freq = gpu_freq;
>
> - sandybridge_pcode_read(i915,
> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
> - &ia_freq, NULL);
> + snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
> + &ia_freq, NULL);
>
> pr_info("%5d %5d %5d\n",
> gpu_freq * 50,
> diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
> index 84bb212bae4b..3e26ccabf7f9 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -389,10 +389,8 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
> u32 val = 0;
> int ret;
>
> - ret = sandybridge_pcode_read(dev_priv,
> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
> - &val, NULL);
> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
> index e8c886e4e78d..db4403f63cac 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -51,11 +51,10 @@ static int gen7_check_mailbox_status(u32 mbox)
> }
> }
>
> -static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> - u32 mbox, u32 *val, u32 *val1,
> - int fast_timeout_us,
> - int slow_timeout_ms,
> - bool is_read)
> +static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
> + u32 *val, u32 *val1,
> + int fast_timeout_us, int slow_timeout_ms,
> + bool is_read)
> {
> struct intel_uncore *uncore = &i915->uncore;
>
> @@ -94,15 +93,12 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> return gen6_check_mailbox_status(mbox);
> }
>
> -int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
> - u32 *val, u32 *val1)
> +int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
> {
> int err;
>
> mutex_lock(&i915->sb_lock);
> - err = __sandybridge_pcode_rw(i915, mbox, val, val1,
> - 500, 20,
> - true);
> + err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
> mutex_unlock(&i915->sb_lock);
>
> if (err) {
> @@ -114,17 +110,14 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
> return err;
> }
>
> -int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
> - u32 mbox, u32 val,
> - int fast_timeout_us,
> - int slow_timeout_ms)
> +int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
> + int fast_timeout_us, int slow_timeout_ms)
> {
> int err;
>
> mutex_lock(&i915->sb_lock);
> - err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
> - fast_timeout_us, slow_timeout_ms,
> - false);
> + err = __snb_pcode_rw(i915, mbox, &val, NULL,
> + fast_timeout_us, slow_timeout_ms, false);
> mutex_unlock(&i915->sb_lock);
>
> if (err) {
> @@ -140,9 +133,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
> u32 request, u32 reply_mask, u32 reply,
> u32 *status)
> {
> - *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
> - 500, 0,
> - true);
> + *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
>
> return *status || ((request & reply_mask) == reply);
> }
> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
> index 50806649d4b6..0962a17fac48 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -10,13 +10,11 @@
>
> struct drm_i915_private;
>
> -int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
> - u32 *val, u32 *val1);
> -int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
> - u32 val, int fast_timeout_us,
> - int slow_timeout_ms);
> -#define sandybridge_pcode_write(i915, mbox, val) \
> - sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
> +int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
> +int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
> + int fast_timeout_us, int slow_timeout_ms);
> +#define snb_pcode_write(i915, mbox, val) \
> + snb_pcode_write_timeout(i915, mbox, val, 500, 0)
>
> int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4ecd995c5cc7..9eec905545b9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2890,9 +2890,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> - ret = sandybridge_pcode_read(dev_priv,
> - GEN9_PCODE_READ_MEM_LATENCY,
> - &val, NULL);
> + ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
> + &val, NULL);
>
> if (ret) {
> drm_err(&dev_priv->drm,
> @@ -2910,9 +2909,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>
> /* read the second set of memory latencies[4:7] */
> val = 1; /* data0 to be programmed to 1 for second set */
> - ret = sandybridge_pcode_read(dev_priv,
> - GEN9_PCODE_READ_MEM_LATENCY,
> - &val, NULL);
> + ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
> + &val, NULL);
> if (ret) {
> drm_err(&dev_priv->drm,
> "SKL Mailbox read error = %d\n", ret);
> @@ -3702,9 +3700,9 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> u32 val = 0;
> int ret;
>
> - ret = sandybridge_pcode_read(dev_priv,
> - GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> - &val, NULL);
> + ret = snb_pcode_read(dev_priv,
> + GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> + &val, NULL);
> if (!ret) {
> dev_priv->sagv_block_time_us = val;
> return;
> @@ -3751,8 +3749,8 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
> return 0;
>
> drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
> - ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
> - GEN9_SAGV_ENABLE);
> + ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
> + GEN9_SAGV_ENABLE);
>
> /* We don't need to wait for SAGV when enabling */
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2)
2022-01-12 11:17 [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* Jani Nikula
2022-01-12 13:57 ` Ville Syrjälä
@ 2022-01-12 14:34 ` Patchwork
2022-01-12 19:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-01-12 14:34 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6662 bytes --]
== Series Details ==
Series: drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2)
URL : https://patchwork.freedesktop.org/series/98440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11073 -> Patchwork_21981
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/index.html
Participating hosts (44 -> 44)
------------------------------
Additional (2): bat-adlp-4 fi-pnv-d510
Missing (2): fi-bsw-cyan bat-jsl-2
Known issues
------------
Here are the changes found in Patchwork_21981 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][1] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@core_hotunplug@unbind-rebind.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][3] ([i915#3282])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][4] -> [DMESG-FAIL][5] ([i915#4494])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][6] -> [INCOMPLETE][7] ([i915#3921])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#4103]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([fdo#109285])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#4269])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3291] / [i915#3708]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][14] ([fdo#109271]) +57 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
- bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#3301] / [i915#3708])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-adlp-4/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-ilk-650: [DMESG-WARN][16] ([i915#164]) -> [PASS][17] +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/fi-ilk-650/igt@core_hotunplug@unbind-rebind.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/fi-ilk-650/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-1115g4: [FAIL][18] ([i915#1888]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][20] ([i915#4494]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#164]: https://gitlab.freedesktop.org/drm/intel/issues/164
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
Build changes
-------------
* Linux: CI_DRM_11073 -> Patchwork_21981
CI-20190529: 20190529
CI_DRM_11073: 1b0b054967d58d23d1621487a1b1995787371d23 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6326: ec75f64fcbcf4aac58fbf1bf629e8f59b19db4ce @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21981: d1a00133d4f1d6f19c540029dd6740c0dd10bd93 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d1a00133d4f1 drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/index.html
[-- Attachment #2: Type: text/html, Size: 7714 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2)
2022-01-12 11:17 [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* Jani Nikula
2022-01-12 13:57 ` Ville Syrjälä
2022-01-12 14:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2) Patchwork
@ 2022-01-12 19:19 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-01-12 19:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30287 bytes --]
== Series Details ==
Series: drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2)
URL : https://patchwork.freedesktop.org/series/98440/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11073_full -> Patchwork_21981_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21981_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21981_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21981_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-iclb: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb3/igt@i915_pm_rpm@system-suspend-modeset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb5/igt@i915_pm_rpm@system-suspend-modeset.html
Known issues
------------
Here are the changes found in Patchwork_21981_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19]) -> ([PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43]) ([i915#4337])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl5/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl4/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl4/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl10/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl10/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl10/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl9/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl8/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl8/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl7/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl5/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl10/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl10/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl10/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][44] ([i915#3002])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@gem_create@create-massive.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][45] -> [FAIL][46] ([i915#232])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-tglb6/igt@gem_eio@unwedge-stress.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb8/igt@gem_eio@unwedge-stress.html
- shard-iclb: [PASS][47] -> [TIMEOUT][48] ([i915#2481] / [i915#3070])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb5/igt@gem_eio@unwedge-stress.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][49] -> [SKIP][50] ([i915#4525])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][51] -> [INCOMPLETE][52] ([i915#4547])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl9/igt@gem_exec_capture@pi@bcs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl10/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][53] ([i915#2842])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][54] -> [FAIL][55] ([i915#2842]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-kbl4/igt@gem_exec_fair@basic-none-vip@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][56] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#4613]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][58] ([i915#2658]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#3323])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb4/igt@gem_userptr_blits@dmabuf-sync.html
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#3323])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][61] ([i915#3318])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][62] -> [DMESG-WARN][63] ([i915#180]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: NOTRUN -> [DMESG-WARN][64] ([i915#1436] / [i915#716])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#2527] / [i915#2856])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb7/igt@gen9_exec_parse@shadow-peek.html
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#2856])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb4/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][67] ([i915#454])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3777])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#3777]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#3743])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#3886])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +19 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [fdo#111827])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl2/igt@kms_chamelium@dp-hpd-storm.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +26 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color@pipe-d-invalid-degamma-lut-sizes:
- shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271]) +33 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_color@pipe-d-invalid-degamma-lut-sizes.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [fdo#111827]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_color_chamelium@pipe-d-ctm-limited-range:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [fdo#111827])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk5/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#109284] / [fdo#111827])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb7/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#3359]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk5/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: [PASS][81] -> [FAIL][82] ([i915#2370])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][83] ([i915#2346] / [i915#533])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][84] -> [INCOMPLETE][85] ([i915#636])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][86] -> [FAIL][87] ([i915#2122])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#109274] / [fdo#111825])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb7/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [PASS][89] -> [FAIL][90] ([i915#79])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][91] ([i915#3701])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#2587])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#109280] / [fdo#111825])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271]) +328 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: NOTRUN -> [FAIL][95] ([i915#1188])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +26 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl6/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][97] ([fdo#108145] / [i915#265]) +6 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][98] -> [FAIL][99] ([fdo#108145] / [i915#265])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#658])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][101] -> [SKIP][102] ([fdo#109441]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][103] -> [DMESG-WARN][104] ([i915#180] / [i915#295])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#533]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2437])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2437])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_pcopy@test_semaphore:
- shard-tglb: NOTRUN -> [SKIP][108] ([fdo#109291])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb3/igt@prime_nv_pcopy@test_semaphore.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994]) +3 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl8/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-0:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2994])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl6/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [TIMEOUT][111] ([i915#3070]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb6/igt@gem_eio@in-flight-contexts-10ms.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][113] ([i915#4525]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][115] ([i915#2842]) -> [PASS][116] +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][117] ([i915#2842]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-skl: [DMESG-WARN][119] ([i915#1982]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl6/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][121] ([i915#2190]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-tglb8/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][123] ([i915#1436] / [i915#716]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk5/igt@gen9_exec_parse@allowed-all.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-glk: [DMESG-WARN][125] ([i915#118]) -> [PASS][126] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk2/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk8/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][127] ([i915#2122]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [SKIP][129] ([i915#3701]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: [FAIL][131] ([i915#2546]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][133] ([i915#180]) -> [PASS][134] +2 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [INCOMPLETE][135] ([i915#2828]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][137] ([i915#31]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-apl2/igt@kms_setmode@basic.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-apl6/igt@kms_setmode@basic.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][139] ([i915#4525]) -> [FAIL][140] ([i915#4916])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [FAIL][141] ([i915#2876]) -> [FAIL][142] ([i915#2842])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][143] ([i915#2849]) -> [FAIL][144] ([i915#2842])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][145] ([i915#2684]) -> [WARN][146] ([i915#1804] / [i915#2684])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][147] ([fdo#111068] / [i915#658]) -> [SKIP][148] ([i915#2920]) +1 similar issue
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][149] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][150] ([i915#4688])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [SKIP][151] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][152] ([i915#4148])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-iclb5/igt@kms_psr2_su@page_flip-xrgb8888.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@runner@aborted:
- shard-skl: ([FAIL][153], [FAIL][154]) ([i915#3002] / [i915#4312]) -> ([FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158]) ([i915#1436] / [i915#3002] / [i915#4312])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl9/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11073/shard-skl6/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl4/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl7/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl9/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/shard-skl10/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21981/index.html
[-- Attachment #2: Type: text/html, Size: 35181 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*
2022-01-12 13:57 ` Ville Syrjälä
@ 2022-01-13 13:24 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2022-01-13 13:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 12 Jan 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jan 12, 2022 at 01:17:40PM +0200, Jani Nikula wrote:
>> Prefer acronym-based naming to be in line with the rest of the driver.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pushed, thanks for the review.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_bw.c | 13 +++-----
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++---------
>> drivers/gpu/drm/i915/display/intel_display.c | 6 ++--
>> .../drm/i915/display/intel_display_power.c | 11 +++----
>> drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
>> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 8 ++---
>> drivers/gpu/drm/i915/gt/intel_llc.c | 9 +++---
>> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 ++-
>> drivers/gpu/drm/i915/gt/intel_rps.c | 8 ++---
>> drivers/gpu/drm/i915/gt/selftest_llc.c | 5 ++-
>> drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++-
>> drivers/gpu/drm/i915/intel_dram.c | 6 ++--
>> drivers/gpu/drm/i915/intel_pcode.c | 31 +++++++------------
>> drivers/gpu/drm/i915/intel_pcode.h | 12 +++----
>> drivers/gpu/drm/i915/intel_pm.c | 20 ++++++------
>> 15 files changed, 70 insertions(+), 102 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 2da4aacc956b..c35bad21b657 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -75,10 +75,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>> u16 dclk;
>> int ret;
>>
>> - ret = sandybridge_pcode_read(dev_priv,
>> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> - ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
>> - &val, &val2);
>> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> + ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
>> + &val, &val2);
>> if (ret)
>> return ret;
>>
>> @@ -102,10 +101,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
>> int ret;
>> int i;
>>
>> - ret = sandybridge_pcode_read(dev_priv,
>> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> - ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
>> - &val, NULL);
>> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> + ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
>> if (ret)
>> return ret;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 1f13398e8ac2..7e20967307df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -805,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>> "trying to change cdclk frequency with cdclk not enabled\n"))
>> return;
>>
>> - ret = sandybridge_pcode_write(dev_priv,
>> - BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
>> + ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
>> if (ret) {
>> drm_err(&dev_priv->drm,
>> "failed to inform pcode about cdclk change\n");
>> @@ -834,8 +833,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
>> LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
>> drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
>>
>> - sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
>> - cdclk_config->voltage_level);
>> + snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
>> + cdclk_config->voltage_level);
>>
>> intel_de_write(dev_priv, CDCLK_FREQ,
>> DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>> @@ -1138,8 +1137,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>> intel_de_posting_read(dev_priv, CDCLK_CTL);
>>
>> /* inform PCU of the change */
>> - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>> - cdclk_config->voltage_level);
>> + snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>> + cdclk_config->voltage_level);
>>
>> intel_update_cdclk(dev_priv);
>> }
>> @@ -1717,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>> * BSpec requires us to wait up to 150usec, but that leads to
>> * timeouts; the 2ms used here is based on experiment.
>> */
>> - ret = sandybridge_pcode_write_timeout(dev_priv,
>> - HSW_PCODE_DE_WRITE_FREQ_REQ,
>> - 0x80000000, 150, 2);
>> -
>> + ret = snb_pcode_write_timeout(dev_priv,
>> + HSW_PCODE_DE_WRITE_FREQ_REQ,
>> + 0x80000000, 150, 2);
>> if (ret) {
>> drm_err(&dev_priv->drm,
>> "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
>> @@ -1781,8 +1779,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
>>
>> if (DISPLAY_VER(dev_priv) >= 11) {
>> - ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>> - cdclk_config->voltage_level);
>> + ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>> + cdclk_config->voltage_level);
>> } else {
>> /*
>> * The timeout isn't specified, the 2ms used here is based on
>> @@ -1790,10 +1788,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>> * FIXME: Waiting for the request completion could be delayed
>> * until the next PCODE request based on BSpec.
>> */
>> - ret = sandybridge_pcode_write_timeout(dev_priv,
>> - HSW_PCODE_DE_WRITE_FREQ_REQ,
>> - cdclk_config->voltage_level,
>> - 150, 2);
>> + ret = snb_pcode_write_timeout(dev_priv,
>> + HSW_PCODE_DE_WRITE_FREQ_REQ,
>> + cdclk_config->voltage_level,
>> + 150, 2);
>> }
>>
>> if (ret) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index bf7ce684dd8e..01e9b5baecd2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -1118,8 +1118,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>> drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
>>
>> if (IS_BROADWELL(dev_priv)) {
>> - drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
>> - IPS_ENABLE | IPS_PCODE_CONTROL));
>> + drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
>> + IPS_ENABLE | IPS_PCODE_CONTROL));
>> /* Quoting Art Runyan: "its not safe to expect any particular
>> * value in IPS_CTL bit 31 after enabling IPS through the
>> * mailbox." Moreover, the mailbox may return a bogus state,
>> @@ -1149,7 +1149,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
>>
>> if (IS_BROADWELL(dev_priv)) {
>> drm_WARN_ON(dev,
>> - sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
>> + snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
>> /*
>> * Wait for PCODE to finish disabling IPS. The BSpec specified
>> * 42ms timeout value leads to occasional timeouts so use 100ms
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index fba35fb6d2df..ee4617299e64 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -683,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
>> int ret, tries = 0;
>>
>> while (1) {
>> - ret = sandybridge_pcode_write_timeout(i915,
>> - ICL_PCODE_EXIT_TCCOLD,
>> - 0, 250, 1);
>> + ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
>> + 250, 1);
>> if (ret != -EAGAIN || ++tries == 3)
>> break;
>> msleep(1);
>> @@ -4053,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
>> * Spec states that we should timeout the request after 200us
>> * but the function below will timeout after 500us
>> */
>> - ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
>> - &high_val);
>> + ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
>> if (ret == 0) {
>> if (block &&
>> (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
>> @@ -5469,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
>> static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
>> {
>> if (IS_HASWELL(dev_priv)) {
>> - if (sandybridge_pcode_write(dev_priv,
>> - GEN6_PCODE_WRITE_D_COMP, val))
>> + if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
>> drm_dbg_kms(&dev_priv->drm,
>> "Failed to write to D_COMP\n");
>> } else {
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> index 4509fe7438e8..e1ecf38db0ef 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> @@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
>> * Mailbox interface.
>> */
>> if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
>> - ret = sandybridge_pcode_write(dev_priv,
>> - SKL_PCODE_LOAD_HDCP_KEYS, 1);
>> + ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
>> if (ret) {
>> drm_err(&dev_priv->drm,
>> "Failed to initiate HDCP key load (%d)\n",
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> index 404dfa7673c6..6c5c1d0363bf 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
>> @@ -134,8 +134,7 @@ static int gen6_drpc(struct seq_file *m)
>> }
>>
>> if (GRAPHICS_VER(i915) <= 7)
>> - sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> - &rc6vids, NULL);
>> + snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
>>
>> seq_printf(m, "RC1e Enabled: %s\n",
>> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>> @@ -557,9 +556,8 @@ static int llc_show(struct seq_file *m, void *data)
>> wakeref = intel_runtime_pm_get(gt->uncore->rpm);
>> for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
>> ia_freq = gpu_freq;
>> - sandybridge_pcode_read(i915,
>> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> - &ia_freq, NULL);
>> + snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> + &ia_freq, NULL);
>> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
>> intel_gpu_freq(rps,
>> (gpu_freq *
>> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
>> index 08d7d5ae263a..63f18830c611 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
>> @@ -140,11 +140,10 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
>> unsigned int ia_freq, ring_freq;
>>
>> calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
>> - sandybridge_pcode_write(i915,
>> - GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
>> - ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
>> - ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
>> - gpu_freq);
>> + snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
>> + ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
>> + ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
>> + gpu_freq);
>> }
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> index 31ebe3f1765d..bb0d6e363f5d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> @@ -268,8 +268,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> GEN6_RC_CTL_HW_ENABLE;
>>
>> rc6vids = 0;
>> - ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> - &rc6vids, NULL);
>> + ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
>> if (GRAPHICS_VER(i915) == 6 && ret) {
>> drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
>> } else if (GRAPHICS_VER(i915) == 6 &&
>> @@ -279,7 +278,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
>> rc6vids &= 0xffff00;
>> rc6vids |= GEN6_ENCODE_RC6_VID(450);
>> - ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
>> + ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
>> if (ret)
>> drm_err(&i915->drm,
>> "Couldn't fix incorrect rc6 voltage\n");
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index bd35e45d3aaa..8a13bc005b45 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -1091,9 +1091,8 @@ static void gen6_rps_init(struct intel_rps *rps)
>> IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
>> u32 ddcc_status = 0;
>>
>> - if (sandybridge_pcode_read(i915,
>> - HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
>> - &ddcc_status, NULL) == 0)
>> + if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
>> + &ddcc_status, NULL) == 0)
>> rps->efficient_freq =
>> clamp_t(u8,
>> (ddcc_status >> 8) & 0xff,
>> @@ -1941,8 +1940,7 @@ void intel_rps_init(struct intel_rps *rps)
>> if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> u32 params = 0;
>>
>> - sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
>> - ¶ms, NULL);
>> + snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
>> if (params & BIT(31)) { /* OC supported */
>> drm_dbg(&i915->drm,
>> "Overclocking supported, max: %dMHz, overclock: %dMHz\n",
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> index 459b775f163a..2cd184ab32b1 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> @@ -31,9 +31,8 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
>>
>> val = gpu_freq;
>> - if (sandybridge_pcode_read(i915,
>> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> - &val, NULL)) {
>> + if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> + &val, NULL)) {
>> pr_err("Failed to read freq table[%d], range [%d, %d]\n",
>> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
>> err = -ENXIO;
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> index bd170ba1cf00..e1e5dd5f7638 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> @@ -519,9 +519,8 @@ static void show_pcu_config(struct intel_rps *rps)
>> for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
>> int ia_freq = gpu_freq;
>>
>> - sandybridge_pcode_read(i915,
>> - GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> - &ia_freq, NULL);
>> + snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
>> + &ia_freq, NULL);
>>
>> pr_info("%5d %5d %5d\n",
>> gpu_freq * 50,
>> diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
>> index 84bb212bae4b..3e26ccabf7f9 100644
>> --- a/drivers/gpu/drm/i915/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/intel_dram.c
>> @@ -389,10 +389,8 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
>> u32 val = 0;
>> int ret;
>>
>> - ret = sandybridge_pcode_read(dev_priv,
>> - ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> - ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
>> - &val, NULL);
>> + ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
>> + ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
>> if (ret)
>> return ret;
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
>> index e8c886e4e78d..db4403f63cac 100644
>> --- a/drivers/gpu/drm/i915/intel_pcode.c
>> +++ b/drivers/gpu/drm/i915/intel_pcode.c
>> @@ -51,11 +51,10 @@ static int gen7_check_mailbox_status(u32 mbox)
>> }
>> }
>>
>> -static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>> - u32 mbox, u32 *val, u32 *val1,
>> - int fast_timeout_us,
>> - int slow_timeout_ms,
>> - bool is_read)
>> +static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
>> + u32 *val, u32 *val1,
>> + int fast_timeout_us, int slow_timeout_ms,
>> + bool is_read)
>> {
>> struct intel_uncore *uncore = &i915->uncore;
>>
>> @@ -94,15 +93,12 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>> return gen6_check_mailbox_status(mbox);
>> }
>>
>> -int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
>> - u32 *val, u32 *val1)
>> +int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
>> {
>> int err;
>>
>> mutex_lock(&i915->sb_lock);
>> - err = __sandybridge_pcode_rw(i915, mbox, val, val1,
>> - 500, 20,
>> - true);
>> + err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
>> mutex_unlock(&i915->sb_lock);
>>
>> if (err) {
>> @@ -114,17 +110,14 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
>> return err;
>> }
>>
>> -int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
>> - u32 mbox, u32 val,
>> - int fast_timeout_us,
>> - int slow_timeout_ms)
>> +int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
>> + int fast_timeout_us, int slow_timeout_ms)
>> {
>> int err;
>>
>> mutex_lock(&i915->sb_lock);
>> - err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
>> - fast_timeout_us, slow_timeout_ms,
>> - false);
>> + err = __snb_pcode_rw(i915, mbox, &val, NULL,
>> + fast_timeout_us, slow_timeout_ms, false);
>> mutex_unlock(&i915->sb_lock);
>>
>> if (err) {
>> @@ -140,9 +133,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
>> u32 request, u32 reply_mask, u32 reply,
>> u32 *status)
>> {
>> - *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
>> - 500, 0,
>> - true);
>> + *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
>>
>> return *status || ((request & reply_mask) == reply);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
>> index 50806649d4b6..0962a17fac48 100644
>> --- a/drivers/gpu/drm/i915/intel_pcode.h
>> +++ b/drivers/gpu/drm/i915/intel_pcode.h
>> @@ -10,13 +10,11 @@
>>
>> struct drm_i915_private;
>>
>> -int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
>> - u32 *val, u32 *val1);
>> -int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>> - u32 val, int fast_timeout_us,
>> - int slow_timeout_ms);
>> -#define sandybridge_pcode_write(i915, mbox, val) \
>> - sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
>> +int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
>> +int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
>> + int fast_timeout_us, int slow_timeout_ms);
>> +#define snb_pcode_write(i915, mbox, val) \
>> + snb_pcode_write_timeout(i915, mbox, val, 500, 0)
>>
>> int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>> u32 reply_mask, u32 reply, int timeout_base_ms);
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4ecd995c5cc7..9eec905545b9 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -2890,9 +2890,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>>
>> /* read the first set of memory latencies[0:3] */
>> val = 0; /* data0 to be programmed to 0 for first set */
>> - ret = sandybridge_pcode_read(dev_priv,
>> - GEN9_PCODE_READ_MEM_LATENCY,
>> - &val, NULL);
>> + ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
>> + &val, NULL);
>>
>> if (ret) {
>> drm_err(&dev_priv->drm,
>> @@ -2910,9 +2909,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>>
>> /* read the second set of memory latencies[4:7] */
>> val = 1; /* data0 to be programmed to 1 for second set */
>> - ret = sandybridge_pcode_read(dev_priv,
>> - GEN9_PCODE_READ_MEM_LATENCY,
>> - &val, NULL);
>> + ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
>> + &val, NULL);
>> if (ret) {
>> drm_err(&dev_priv->drm,
>> "SKL Mailbox read error = %d\n", ret);
>> @@ -3702,9 +3700,9 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
>> u32 val = 0;
>> int ret;
>>
>> - ret = sandybridge_pcode_read(dev_priv,
>> - GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
>> - &val, NULL);
>> + ret = snb_pcode_read(dev_priv,
>> + GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
>> + &val, NULL);
>> if (!ret) {
>> dev_priv->sagv_block_time_us = val;
>> return;
>> @@ -3751,8 +3749,8 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
>> return 0;
>>
>> drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
>> - ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
>> - GEN9_SAGV_ENABLE);
>> + ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
>> + GEN9_SAGV_ENABLE);
>>
>> /* We don't need to wait for SAGV when enabling */
>>
>> --
>> 2.30.2
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-01-13 13:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-12 11:17 [Intel-gfx] [PATCH RESEND] drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* Jani Nikula
2022-01-12 13:57 ` Ville Syrjälä
2022-01-13 13:24 ` Jani Nikula
2022-01-12 14:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* (rev2) Patchwork
2022-01-12 19:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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