* [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp()
@ 2022-01-19 12:21 Ville Syrjala
2022-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Ville Syrjala @ 2022-01-19 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
dg2_ddi_pre_enable_dp() has outlived its usefulness so eliminate
it.
The one thing that tgl_ddi_pre_enable_dp() is missing that we
need is intel_ddi_config_transcoder_dp2(). So we'll bring that
over.
tgl_ddi_pre_enable_dp() does also have a few things that
dg2_ddi_pre_enable_dp() didn't have:
- icl_program_mg_dp_mode() -> nop due to intel_phy_is_tc()==false on DG2
- intel_ddi_power_up_lanes() -> nop due to intel_phy_is_combo()==false on DG2
- intel_ddi_mso_configure() -> only matters for MSO panels
Another slight difference is that dg2_ddi_pre_enable_dp() was
missing a bigjoiner check around intel_dsc_enable(), which
tgl_ddi_pre_enable_dp() does have.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 117 +----------------------
1 file changed, 4 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e93eac926a5..2f20abc5122d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2289,116 +2289,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
OVERLAP_PIXELS_MASK, dss1);
}
-static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
- struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
-{
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
-
- intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
- crtc_state->lane_count);
-
- /*
- * We only configure what the register value will be here. Actual
- * enabling happens during link training farther down.
- */
- intel_ddi_init_dp_buf_reg(encoder, crtc_state);
-
- /*
- * 1. Enable Power Wells
- *
- * This was handled at the beginning of intel_atomic_commit_tail(),
- * before we called down into this function.
- */
-
- /* 2. Enable Panel Power if PPS is required */
- intel_pps_on(intel_dp);
-
- /*
- * 3. Enable the port PLL.
- */
- intel_ddi_enable_clock(encoder, crtc_state);
-
- /* 4. Enable IO power */
- if (!intel_tc_port_in_tbt_alt_mode(dig_port))
- dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
- dig_port->ddi_io_power_domain);
-
- /*
- * 5. The rest of the below are substeps under the bspec's "Enable and
- * Train Display Port" step. Note that steps that are specific to
- * MST will be handled by intel_mst_pre_enable_dp() before/after it
- * calls into this function. Also intel_mst_pre_enable_dp() only calls
- * us when active_mst_links==0, so any steps designated for "single
- * stream or multi-stream master transcoder" can just be performed
- * unconditionally here.
- */
-
- /*
- * 5.a Configure Transcoder Clock Select to direct the Port clock to the
- * Transcoder.
- */
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
-
- /* 5.b Configure transcoder for DP 2.0 128b/132b */
- intel_ddi_config_transcoder_dp2(encoder, crtc_state);
-
- /*
- * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
- * Transport Select
- */
- intel_ddi_config_transcoder_func(encoder, crtc_state);
-
- /*
- * 5.d Configure & enable DP_TP_CTL with link training pattern 1
- * selected
- *
- * This will be handled by the intel_dp_start_link_train() farther
- * down this function.
- */
-
- /* 5.e Configure voltage swing and related IO settings */
- encoder->set_signal_levels(encoder, crtc_state);
-
- if (!is_mst)
- intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
-
- intel_dp_configure_protocol_converter(intel_dp, crtc_state);
- intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
- /*
- * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
- * in the FEC_CONFIGURATION register to 1 before initiating link
- * training
- */
- intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
- intel_dp_check_frl_training(intel_dp);
- intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
-
- /*
- * 5.h Follow DisplayPort specification training sequence (see notes for
- * failure handling)
- * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
- * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
- * (timeout after 800 us)
- */
- intel_dp_start_link_train(intel_dp, crtc_state);
-
- /* 5.j Set DP_TP_CTL link training to Normal */
- if (!is_trans_port_sync_mode(crtc_state))
- intel_dp_stop_link_train(intel_dp, crtc_state);
-
- /* 5.k Configure and enable FEC if needed */
- intel_ddi_enable_fec(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
-
- intel_dsc_enable(crtc_state);
-}
-
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -2472,6 +2362,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
*/
intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ if (HAS_DP20(dev_priv))
+ intel_ddi_config_transcoder_dp2(encoder, crtc_state);
+
/*
* 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
* Transport Select
@@ -2612,9 +2505,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_DG2(dev_priv))
- dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
- else if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
--
2.32.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 12:21 [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp() Ville Syrjala
@ 2022-01-19 13:08 ` Patchwork
2022-01-19 13:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-01-19 13:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Nuke dg2_ddi_pre_enable_dp()
URL : https://patchwork.freedesktop.org/series/99041/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9cb5445f65a3 drm/i915: Nuke dg2_ddi_pre_enable_dp()
-:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#19:
- intel_ddi_power_up_lanes() -> nop due to intel_phy_is_combo()==false on DG2
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 12:21 [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp() Ville Syrjala
2022-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-01-19 13:41 ` Patchwork
2022-01-19 15:17 ` [Intel-gfx] [PATCH] " Jani Nikula
2022-01-19 15:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-01-19 13:41 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3804 bytes --]
== Series Details ==
Series: drm/i915: Nuke dg2_ddi_pre_enable_dp()
URL : https://patchwork.freedesktop.org/series/99041/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11104 -> Patchwork_22022
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/index.html
Participating hosts (46 -> 41)
------------------------------
Missing (5): shard-tglu fi-bsw-cyan fi-pnv-d510 bat-jsl-2 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22022 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][1] -> [INCOMPLETE][2] ([i915#4418])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#4269])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][5] -> [FAIL][6] ([i915#4547])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- bat-dg1-6: NOTRUN -> [FAIL][7] ([i915#4214] / [i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/bat-dg1-6/igt@runner@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#4312])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/fi-skl-6600u/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-FAIL][9] ([i915#295]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][11] ([i915#295]) -> [PASS][12] +10 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4214]: https://gitlab.freedesktop.org/drm/intel/issues/4214
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
Build changes
-------------
* Linux: CI_DRM_11104 -> Patchwork_22022
CI-20190529: 20190529
CI_DRM_11104: 78b8a3e2f4543ecf92fe5a59dbd0255503c97dcc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22022: 9cb5445f65a3da28d449ed175505f9db29940290 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9cb5445f65a3 drm/i915: Nuke dg2_ddi_pre_enable_dp()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/index.html
[-- Attachment #2: Type: text/html, Size: 4705 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 12:21 [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp() Ville Syrjala
2022-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-01-19 13:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-19 15:17 ` Jani Nikula
2022-01-19 19:09 ` Navare, Manasi
2022-01-19 15:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2022-01-19 15:17 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 19 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> dg2_ddi_pre_enable_dp() has outlived its usefulness so eliminate
> it.
>
> The one thing that tgl_ddi_pre_enable_dp() is missing that we
> need is intel_ddi_config_transcoder_dp2(). So we'll bring that
> over.
>
> tgl_ddi_pre_enable_dp() does also have a few things that
> dg2_ddi_pre_enable_dp() didn't have:
> - icl_program_mg_dp_mode() -> nop due to intel_phy_is_tc()==false on DG2
> - intel_ddi_power_up_lanes() -> nop due to intel_phy_is_combo()==false on DG2
> - intel_ddi_mso_configure() -> only matters for MSO panels
>
> Another slight difference is that dg2_ddi_pre_enable_dp() was
> missing a bigjoiner check around intel_dsc_enable(), which
> tgl_ddi_pre_enable_dp() does have.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
The modeset step bspec references could use a cleanup too. If they
aren't stable number&letter combos for *one* platform, let alone many,
we should probably just remove them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 117 +----------------------
> 1 file changed, 4 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e93eac926a5..2f20abc5122d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2289,116 +2289,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
> OVERLAP_PIXELS_MASK, dss1);
> }
>
> -static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
> - struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> -{
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> - bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> -
> - intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> - crtc_state->lane_count);
> -
> - /*
> - * We only configure what the register value will be here. Actual
> - * enabling happens during link training farther down.
> - */
> - intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> -
> - /*
> - * 1. Enable Power Wells
> - *
> - * This was handled at the beginning of intel_atomic_commit_tail(),
> - * before we called down into this function.
> - */
> -
> - /* 2. Enable Panel Power if PPS is required */
> - intel_pps_on(intel_dp);
> -
> - /*
> - * 3. Enable the port PLL.
> - */
> - intel_ddi_enable_clock(encoder, crtc_state);
> -
> - /* 4. Enable IO power */
> - if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
> - dig_port->ddi_io_power_domain);
> -
> - /*
> - * 5. The rest of the below are substeps under the bspec's "Enable and
> - * Train Display Port" step. Note that steps that are specific to
> - * MST will be handled by intel_mst_pre_enable_dp() before/after it
> - * calls into this function. Also intel_mst_pre_enable_dp() only calls
> - * us when active_mst_links==0, so any steps designated for "single
> - * stream or multi-stream master transcoder" can just be performed
> - * unconditionally here.
> - */
> -
> - /*
> - * 5.a Configure Transcoder Clock Select to direct the Port clock to the
> - * Transcoder.
> - */
> - intel_ddi_enable_pipe_clock(encoder, crtc_state);
> -
> - /* 5.b Configure transcoder for DP 2.0 128b/132b */
> - intel_ddi_config_transcoder_dp2(encoder, crtc_state);
> -
> - /*
> - * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
> - * Transport Select
> - */
> - intel_ddi_config_transcoder_func(encoder, crtc_state);
> -
> - /*
> - * 5.d Configure & enable DP_TP_CTL with link training pattern 1
> - * selected
> - *
> - * This will be handled by the intel_dp_start_link_train() farther
> - * down this function.
> - */
> -
> - /* 5.e Configure voltage swing and related IO settings */
> - encoder->set_signal_levels(encoder, crtc_state);
> -
> - if (!is_mst)
> - intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> -
> - intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> - /*
> - * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> - * in the FEC_CONFIGURATION register to 1 before initiating link
> - * training
> - */
> - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> - intel_dp_check_frl_training(intel_dp);
> - intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> -
> - /*
> - * 5.h Follow DisplayPort specification training sequence (see notes for
> - * failure handling)
> - * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
> - * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
> - * (timeout after 800 us)
> - */
> - intel_dp_start_link_train(intel_dp, crtc_state);
> -
> - /* 5.j Set DP_TP_CTL link training to Normal */
> - if (!is_trans_port_sync_mode(crtc_state))
> - intel_dp_stop_link_train(intel_dp, crtc_state);
> -
> - /* 5.k Configure and enable FEC if needed */
> - intel_ddi_enable_fec(encoder, crtc_state);
> -
> - intel_dsc_dp_pps_write(encoder, crtc_state);
> -
> - intel_dsc_enable(crtc_state);
> -}
> -
> static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> @@ -2472,6 +2362,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> */
> intel_ddi_enable_pipe_clock(encoder, crtc_state);
>
> + if (HAS_DP20(dev_priv))
> + intel_ddi_config_transcoder_dp2(encoder, crtc_state);
> +
> /*
> * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
> * Transport Select
> @@ -2612,9 +2505,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_DG2(dev_priv))
> - dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> - else if (DISPLAY_VER(dev_priv) >= 12)
> + if (DISPLAY_VER(dev_priv) >= 12)
> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> else
> hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 12:21 [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp() Ville Syrjala
` (2 preceding siblings ...)
2022-01-19 15:17 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2022-01-19 15:38 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-01-19 15:38 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30261 bytes --]
== Series Details ==
Series: drm/i915: Nuke dg2_ddi_pre_enable_dp()
URL : https://patchwork.freedesktop.org/series/99041/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11104_full -> Patchwork_22022_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22022_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22022_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22022_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-fences-interruptible@b-vga1:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-snb5/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-snb6/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html
* igt@syncobj_timeline@wait-all-snapshot:
- shard-skl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl8/igt@syncobj_timeline@wait-all-snapshot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl3/igt@syncobj_timeline@wait-all-snapshot.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-tglu}: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@runner@aborted:
- {shard-tglu}: ([FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10]) ([i915#3002] / [i915#3690] / [i915#4312]) -> ([FAIL][11], [FAIL][12]) ([i915#3002] / [i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-4/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-2/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-3/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-2/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-6/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_22022_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@kms:
- shard-skl: [PASS][13] -> [TIMEOUT][14] ([i915#3063])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl8/igt@gem_eio@kms.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl3/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][15] -> [SKIP][16] ([i915#4525]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][17] ([i915#4547])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl8/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2846])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk5/igt@gem_exec_fair@basic-deadline.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][20] -> [FAIL][21] ([i915#2842]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][22] ([i915#2842])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#112283])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@gem_exec_params@secure-non-master.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#4613]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl6/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@verify-random:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#4613])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][26] ([i915#2658]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl1/igt@gem_softpin@noreloc-s3.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@gem_softpin@noreloc-s3.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#2527] / [i915#2856])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][30] -> [SKIP][31] ([i915#4281])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [PASS][32] -> [DMESG-WARN][33] ([i915#118]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk3/igt@kms_big_fb@linear-32bpp-rotate-180.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk8/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][35] ([i915#3743])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +11 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl10/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#3689] / [i915#3886])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#3886])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +15 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl8/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109279] / [i915#3359])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x512-rapid-movement.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#2346])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271]) +240 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl8/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][47] -> [INCOMPLETE][48] ([i915#180])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][49] -> [FAIL][50] ([i915#79]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][51] -> [FAIL][52] ([i915#2122]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][53] ([i915#3701])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271]) +17 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109280] / [fdo#111825]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271]) +30 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][57] -> [FAIL][58] ([i915#1188])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109278])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][61] -> [FAIL][62] ([fdo#108145] / [i915#265])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl6/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109441]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][67] ([i915#180])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2437])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl1/igt@kms_writeback@writeback-pixel-formats.html
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2437])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_test@i915_blt_fill_nv_read:
- shard-tglb: NOTRUN -> [SKIP][71] ([fdo#109291])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@prime_nv_test@i915_blt_fill_nv_read.html
* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@recycle:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2994]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl7/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][74] ([i915#232]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglb1/igt@gem_eio@unwedge-stress.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][76] ([i915#4525]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb7/igt@gem_exec_balancer@parallel-balancer.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][78] ([i915#2842]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [FAIL][80] ([i915#2842]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][82] ([i915#2842]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-apl: [FAIL][84] ([i915#2842]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][86] ([i915#2842]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][88] ([i915#2842]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb1/igt@gem_exec_fair@basic-pace@vecs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][90] ([i915#2190]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglb2/igt@gem_huc_copy@huc-copy.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- {shard-tglu}: [INCOMPLETE][92] -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-3/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][94] ([i915#454]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][96] ([i915#402]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [DMESG-WARN][98] ([i915#118]) -> [PASS][99] +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk1/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk1/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- {shard-tglu}: [FAIL][100] ([i915#3743]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][102] ([i915#180] / [i915#636]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
- shard-skl: [FAIL][104] ([i915#2122]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl10/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][106] ([i915#79]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][108] ([i915#3701]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][110] ([i915#1188]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl9/igt@kms_hdr@bpc-switch.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl9/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl2/igt@kms_hdr@bpc-switch-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][114] ([i915#31]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl2/igt@kms_setmode@basic.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@kms_setmode@basic.html
* igt@perf@polling-parameterized:
- shard-glk: [FAIL][116] ([i915#1542]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-glk7/igt@perf@polling-parameterized.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-glk2/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][118] ([i915#4916]) -> [SKIP][119] ([i915#4525])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][120] ([i915#2849]) -> [FAIL][121] ([i915#2842])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][122] ([i915#2680]) -> [WARN][123] ([i915#2684])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][124] ([i915#79]) -> [FAIL][125] ([i915#2122])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][126] ([fdo#111068] / [i915#658]) -> [SKIP][127] ([i915#2920]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][128], [FAIL][129], [FAIL][130]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#92]) -> ([FAIL][131], [FAIL][132]) ([i915#3002] / [i915#4312])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl6/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl6/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-kbl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl4/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-kbl6/igt@runner@aborted.html
- shard-apl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl4/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl2/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11104/shard-apl1/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl8/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.o
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22022/index.html
[-- Attachment #2: Type: text/html, Size: 33696 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 15:17 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2022-01-19 19:09 ` Navare, Manasi
2022-01-19 19:47 ` Ville Syrjälä
0 siblings, 1 reply; 7+ messages in thread
From: Navare, Manasi @ 2022-01-19 19:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Jan 19, 2022 at 05:17:05PM +0200, Jani Nikula wrote:
> On Wed, 19 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > dg2_ddi_pre_enable_dp() has outlived its usefulness so eliminate
> > it.
> >
> > The one thing that tgl_ddi_pre_enable_dp() is missing that we
> > need is intel_ddi_config_transcoder_dp2(). So we'll bring that
> > over.
> >
> > tgl_ddi_pre_enable_dp() does also have a few things that
> > dg2_ddi_pre_enable_dp() didn't have:
> > - icl_program_mg_dp_mode() -> nop due to intel_phy_is_tc()==false on DG2
> > - intel_ddi_power_up_lanes() -> nop due to intel_phy_is_combo()==false on DG2
> > - intel_ddi_mso_configure() -> only matters for MSO panels
> >
> > Another slight difference is that dg2_ddi_pre_enable_dp() was
> > missing a bigjoiner check around intel_dsc_enable(), which
> > tgl_ddi_pre_enable_dp() does have.
Thanks Ville for this patch, I was just comparing differences between dg2_pre_enable_dp and tgl_pre_enable_dp
in regards to a bug and there is totally no need for two functions with the checks you have here.
For the bigjoiner check aroind intel_dsc_enable(), I think the function intel_dsc_dp_pps_write(encoder, crtc_state);
also needs to be moved into that check.
And then this functions needs to be called from icl_ddi_bigjoiner_pre_enable() where we call intel_dsc_enable
With that:
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> The modeset step bspec references could use a cleanup too. If they
> aren't stable number&letter combos for *one* platform, let alone many,
> we should probably just remove them.
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 117 +----------------------
> > 1 file changed, 4 insertions(+), 113 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e93eac926a5..2f20abc5122d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -2289,116 +2289,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
> > OVERLAP_PIXELS_MASK, dss1);
> > }
> >
> > -static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > - struct intel_encoder *encoder,
> > - const struct intel_crtc_state *crtc_state,
> > - const struct drm_connector_state *conn_state)
> > -{
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > - struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > - bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> > -
> > - intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> > - crtc_state->lane_count);
> > -
> > - /*
> > - * We only configure what the register value will be here. Actual
> > - * enabling happens during link training farther down.
> > - */
> > - intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> > -
> > - /*
> > - * 1. Enable Power Wells
> > - *
> > - * This was handled at the beginning of intel_atomic_commit_tail(),
> > - * before we called down into this function.
> > - */
> > -
> > - /* 2. Enable Panel Power if PPS is required */
> > - intel_pps_on(intel_dp);
> > -
> > - /*
> > - * 3. Enable the port PLL.
> > - */
> > - intel_ddi_enable_clock(encoder, crtc_state);
> > -
> > - /* 4. Enable IO power */
> > - if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
> > - dig_port->ddi_io_power_domain);
> > -
> > - /*
> > - * 5. The rest of the below are substeps under the bspec's "Enable and
> > - * Train Display Port" step. Note that steps that are specific to
> > - * MST will be handled by intel_mst_pre_enable_dp() before/after it
> > - * calls into this function. Also intel_mst_pre_enable_dp() only calls
> > - * us when active_mst_links==0, so any steps designated for "single
> > - * stream or multi-stream master transcoder" can just be performed
> > - * unconditionally here.
> > - */
> > -
> > - /*
> > - * 5.a Configure Transcoder Clock Select to direct the Port clock to the
> > - * Transcoder.
> > - */
> > - intel_ddi_enable_pipe_clock(encoder, crtc_state);
> > -
> > - /* 5.b Configure transcoder for DP 2.0 128b/132b */
> > - intel_ddi_config_transcoder_dp2(encoder, crtc_state);
> > -
> > - /*
> > - * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
> > - * Transport Select
> > - */
> > - intel_ddi_config_transcoder_func(encoder, crtc_state);
> > -
> > - /*
> > - * 5.d Configure & enable DP_TP_CTL with link training pattern 1
> > - * selected
> > - *
> > - * This will be handled by the intel_dp_start_link_train() farther
> > - * down this function.
> > - */
> > -
> > - /* 5.e Configure voltage swing and related IO settings */
> > - encoder->set_signal_levels(encoder, crtc_state);
> > -
> > - if (!is_mst)
> > - intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> > -
> > - intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> > - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> > - /*
> > - * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> > - * in the FEC_CONFIGURATION register to 1 before initiating link
> > - * training
> > - */
> > - intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
> > - intel_dp_check_frl_training(intel_dp);
> > - intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
> > -
> > - /*
> > - * 5.h Follow DisplayPort specification training sequence (see notes for
> > - * failure handling)
> > - * 5.i If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
> > - * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
> > - * (timeout after 800 us)
> > - */
> > - intel_dp_start_link_train(intel_dp, crtc_state);
> > -
> > - /* 5.j Set DP_TP_CTL link training to Normal */
> > - if (!is_trans_port_sync_mode(crtc_state))
> > - intel_dp_stop_link_train(intel_dp, crtc_state);
> > -
> > - /* 5.k Configure and enable FEC if needed */
> > - intel_ddi_enable_fec(encoder, crtc_state);
> > -
> > - intel_dsc_dp_pps_write(encoder, crtc_state);
> > -
> > - intel_dsc_enable(crtc_state);
> > -}
> > -
> > static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > @@ -2472,6 +2362,9 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > */
> > intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >
> > + if (HAS_DP20(dev_priv))
> > + intel_ddi_config_transcoder_dp2(encoder, crtc_state);
> > +
> > /*
> > * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
> > * Transport Select
> > @@ -2612,9 +2505,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >
> > - if (IS_DG2(dev_priv))
> > - dg2_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> > - else if (DISPLAY_VER(dev_priv) >= 12)
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> > else
> > hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp()
2022-01-19 19:09 ` Navare, Manasi
@ 2022-01-19 19:47 ` Ville Syrjälä
0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2022-01-19 19:47 UTC (permalink / raw)
To: Navare, Manasi; +Cc: intel-gfx
On Wed, Jan 19, 2022 at 11:09:47AM -0800, Navare, Manasi wrote:
> On Wed, Jan 19, 2022 at 05:17:05PM +0200, Jani Nikula wrote:
> > On Wed, 19 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > dg2_ddi_pre_enable_dp() has outlived its usefulness so eliminate
> > > it.
> > >
> > > The one thing that tgl_ddi_pre_enable_dp() is missing that we
> > > need is intel_ddi_config_transcoder_dp2(). So we'll bring that
> > > over.
> > >
> > > tgl_ddi_pre_enable_dp() does also have a few things that
> > > dg2_ddi_pre_enable_dp() didn't have:
> > > - icl_program_mg_dp_mode() -> nop due to intel_phy_is_tc()==false on DG2
> > > - intel_ddi_power_up_lanes() -> nop due to intel_phy_is_combo()==false on DG2
> > > - intel_ddi_mso_configure() -> only matters for MSO panels
> > >
> > > Another slight difference is that dg2_ddi_pre_enable_dp() was
> > > missing a bigjoiner check around intel_dsc_enable(), which
> > > tgl_ddi_pre_enable_dp() does have.
>
> Thanks Ville for this patch, I was just comparing differences between dg2_pre_enable_dp and tgl_pre_enable_dp
> in regards to a bug and there is totally no need for two functions with the checks you have here.
>
> For the bigjoiner check aroind intel_dsc_enable(), I think the function intel_dsc_dp_pps_write(encoder, crtc_state);
> also needs to be moved into that check.
> And then this functions needs to be called from icl_ddi_bigjoiner_pre_enable() where we call intel_dsc_enable
The video DIP lives in the transcoder so we don't want to write it
twice.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-01-19 19:47 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-19 12:21 [Intel-gfx] [PATCH] drm/i915: Nuke dg2_ddi_pre_enable_dp() Ville Syrjala
2022-01-19 13:08 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-01-19 13:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-19 15:17 ` [Intel-gfx] [PATCH] " Jani Nikula
2022-01-19 19:09 ` Navare, Manasi
2022-01-19 19:47 ` Ville Syrjälä
2022-01-19 15:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
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