* [PATCH] drm/i915: avoid concurrent writes to aux_inv
@ 2022-02-26 1:50 ` fei.yang
0 siblings, 0 replies; 5+ messages in thread
From: fei.yang @ 2022-02-26 1:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Fei Yang, chris.p.wilson, dri-devel
From: Fei Yang <fei.yang@intel.com>
GPU hangs have been observed when multiple engines write to the same aux_inv
register at the same time. To avoid this each engine should only invalidate
its own auxiliary table. The function gen12_emit_flush_xcs() currently
invalidate the auxiliary table for all engines because the rq->engine is not
necessarily the engine eventually carrying out the request, and potentially
the engine could even be a virtual one (with engine->instance being -1).
With this patch, auxiliary table invalidation is done only for the engine
executing the request. And the mmio address for the aux_inv register is set
after the engine instance becomes certain.
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 +++----------------
.../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/i915_request.h | 2 +
3 files changed, 45 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 1f8cf4f790b2..9e39d04f46cc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -165,30 +165,6 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
-static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
-{
- static const i915_reg_t vd[] = {
- GEN12_VD0_AUX_NV,
- GEN12_VD1_AUX_NV,
- GEN12_VD2_AUX_NV,
- GEN12_VD3_AUX_NV,
- };
-
- static const i915_reg_t ve[] = {
- GEN12_VE0_AUX_NV,
- GEN12_VE1_AUX_NV,
- };
-
- if (engine->class == VIDEO_DECODE_CLASS)
- return vd[engine->instance];
-
- if (engine->class == VIDEO_ENHANCEMENT_CLASS)
- return ve[engine->instance];
-
- GEM_BUG_ON("unknown aux_inv reg\n");
- return INVALID_MMIO_REG;
-}
-
static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
@@ -280,7 +256,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE)
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
- cmd += 2 * hweight32(aux_inv) + 2;
+ cmd += 4;
cs = intel_ring_begin(rq, cmd);
if (IS_ERR(cs))
@@ -311,14 +287,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
*cs++ = 0; /* value */
if (aux_inv) { /* hsdes: 1809175790 */
- struct intel_engine_cs *engine;
- unsigned int tmp;
-
- *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
- for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
- *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
- *cs++ = AUX_INV;
- }
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ rq->vd_ve_aux_inv = cs;
+ *cs++ = 0; /* address to be set at submission to HW */
+ *cs++ = AUX_INV;
*cs++ = MI_NOOP;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 961d795220a3..f56726c861b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1253,6 +1253,34 @@ static bool completed(const struct i915_request *rq)
return __i915_request_is_complete(rq);
}
+static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
+{
+ static const i915_reg_t vd[] = {
+ GEN12_VD0_AUX_NV,
+ GEN12_VD1_AUX_NV,
+ GEN12_VD2_AUX_NV,
+ GEN12_VD3_AUX_NV,
+ };
+
+ static const i915_reg_t ve[] = {
+ GEN12_VE0_AUX_NV,
+ GEN12_VE1_AUX_NV,
+ };
+
+ if (engine->class == VIDEO_DECODE_CLASS) {
+ GEM_BUG_ON(engine->instance >= ARRAY_SIZE(vd));
+ return vd[engine->instance];
+ }
+
+ if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
+ GEM_BUG_ON(engine->instance >= ARRAY_SIZE(ve));
+ return ve[engine->instance];
+ }
+
+ GEM_BUG_ON("unknown aux_inv reg\n");
+ return INVALID_MMIO_REG;
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1533,6 +1561,16 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (__i915_request_submit(rq)) {
+ /* hsdes: 1809175790 */
+ if (rq->vd_ve_aux_inv &&
+ (engine->class == VIDEO_DECODE_CLASS ||
+ engine->class == VIDEO_ENHANCEMENT_CLASS)) {
+ *rq->vd_ve_aux_inv =
+ i915_mmio_reg_offset(
+ aux_inv_reg(engine));
+ rq->vd_ve_aux_inv = NULL;
+ rq->execution_mask = engine->mask;
+ }
if (!merge) {
*port++ = i915_request_get(last);
last = NULL;
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 28b1f9db5487..69de32e5e15d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -350,6 +350,8 @@ struct i915_request {
struct list_head link;
unsigned long delay;
} mock;)
+
+ u32 *vd_ve_aux_inv;
};
#define I915_FENCE_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv
@ 2022-02-26 1:50 ` fei.yang
0 siblings, 0 replies; 5+ messages in thread
From: fei.yang @ 2022-02-26 1:50 UTC (permalink / raw)
To: intel-gfx; +Cc: chris.p.wilson, dri-devel
From: Fei Yang <fei.yang@intel.com>
GPU hangs have been observed when multiple engines write to the same aux_inv
register at the same time. To avoid this each engine should only invalidate
its own auxiliary table. The function gen12_emit_flush_xcs() currently
invalidate the auxiliary table for all engines because the rq->engine is not
necessarily the engine eventually carrying out the request, and potentially
the engine could even be a virtual one (with engine->instance being -1).
With this patch, auxiliary table invalidation is done only for the engine
executing the request. And the mmio address for the aux_inv register is set
after the engine instance becomes certain.
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 +++----------------
.../drm/i915/gt/intel_execlists_submission.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/i915_request.h | 2 +
3 files changed, 45 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 1f8cf4f790b2..9e39d04f46cc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -165,30 +165,6 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
-static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
-{
- static const i915_reg_t vd[] = {
- GEN12_VD0_AUX_NV,
- GEN12_VD1_AUX_NV,
- GEN12_VD2_AUX_NV,
- GEN12_VD3_AUX_NV,
- };
-
- static const i915_reg_t ve[] = {
- GEN12_VE0_AUX_NV,
- GEN12_VE1_AUX_NV,
- };
-
- if (engine->class == VIDEO_DECODE_CLASS)
- return vd[engine->instance];
-
- if (engine->class == VIDEO_ENHANCEMENT_CLASS)
- return ve[engine->instance];
-
- GEM_BUG_ON("unknown aux_inv reg\n");
- return INVALID_MMIO_REG;
-}
-
static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
@@ -280,7 +256,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE)
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
- cmd += 2 * hweight32(aux_inv) + 2;
+ cmd += 4;
cs = intel_ring_begin(rq, cmd);
if (IS_ERR(cs))
@@ -311,14 +287,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
*cs++ = 0; /* value */
if (aux_inv) { /* hsdes: 1809175790 */
- struct intel_engine_cs *engine;
- unsigned int tmp;
-
- *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
- for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
- *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
- *cs++ = AUX_INV;
- }
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ rq->vd_ve_aux_inv = cs;
+ *cs++ = 0; /* address to be set at submission to HW */
+ *cs++ = AUX_INV;
*cs++ = MI_NOOP;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 961d795220a3..f56726c861b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1253,6 +1253,34 @@ static bool completed(const struct i915_request *rq)
return __i915_request_is_complete(rq);
}
+static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
+{
+ static const i915_reg_t vd[] = {
+ GEN12_VD0_AUX_NV,
+ GEN12_VD1_AUX_NV,
+ GEN12_VD2_AUX_NV,
+ GEN12_VD3_AUX_NV,
+ };
+
+ static const i915_reg_t ve[] = {
+ GEN12_VE0_AUX_NV,
+ GEN12_VE1_AUX_NV,
+ };
+
+ if (engine->class == VIDEO_DECODE_CLASS) {
+ GEM_BUG_ON(engine->instance >= ARRAY_SIZE(vd));
+ return vd[engine->instance];
+ }
+
+ if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
+ GEM_BUG_ON(engine->instance >= ARRAY_SIZE(ve));
+ return ve[engine->instance];
+ }
+
+ GEM_BUG_ON("unknown aux_inv reg\n");
+ return INVALID_MMIO_REG;
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1533,6 +1561,16 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (__i915_request_submit(rq)) {
+ /* hsdes: 1809175790 */
+ if (rq->vd_ve_aux_inv &&
+ (engine->class == VIDEO_DECODE_CLASS ||
+ engine->class == VIDEO_ENHANCEMENT_CLASS)) {
+ *rq->vd_ve_aux_inv =
+ i915_mmio_reg_offset(
+ aux_inv_reg(engine));
+ rq->vd_ve_aux_inv = NULL;
+ rq->execution_mask = engine->mask;
+ }
if (!merge) {
*port++ = i915_request_get(last);
last = NULL;
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index 28b1f9db5487..69de32e5e15d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -350,6 +350,8 @@ struct i915_request {
struct list_head link;
unsigned long delay;
} mock;)
+
+ u32 *vd_ve_aux_inv;
};
#define I915_FENCE_GFP (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: avoid concurrent writes to aux_inv
2022-02-26 1:50 ` [Intel-gfx] " fei.yang
(?)
@ 2022-02-26 3:56 ` Patchwork
-1 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-02-26 3:56 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv
URL : https://patchwork.freedesktop.org/series/100772/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2d74b0515d73 drm/i915: avoid concurrent writes to aux_inv
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6:
GPU hangs have been observed when multiple engines write to the same aux_inv
-:130: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#130: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:1569:
+ i915_mmio_reg_offset(
total: 0 errors, 1 warnings, 1 checks, 114 lines checked
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: avoid concurrent writes to aux_inv
2022-02-26 1:50 ` [Intel-gfx] " fei.yang
(?)
(?)
@ 2022-02-26 3:57 ` Patchwork
-1 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-02-26 3:57 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv
URL : https://patchwork.freedesktop.org/series/100772/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: avoid concurrent writes to aux_inv
2022-02-26 1:50 ` [Intel-gfx] " fei.yang
` (2 preceding siblings ...)
(?)
@ 2022-02-26 4:20 ` Patchwork
-1 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-02-26 4:20 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2678 bytes --]
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv
URL : https://patchwork.freedesktop.org/series/100772/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11290 -> Patchwork_22423
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22423 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22423, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22423/index.html
Participating hosts (41 -> 17)
------------------------------
ERROR: It appears as if the changes made in Patchwork_22423 prevented too many machines from booting.
Missing (24): fi-kbl-soraka fi-bdw-gvtdvm fi-apl-guc fi-skl-6600u fi-bxt-dsi fi-bsw-n3050 fi-glk-dsi fi-kbl-7500u fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u fi-skl-guc fi-cfl-8700k fi-glk-j4005 fi-ehl-2 bat-jsl-2 bat-jsl-1 fi-jsl-1 fi-bsw-cyan fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka
Known issues
------------
Here are the changes found in Patchwork_22423 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][1] ([i915#3576]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/bat-adlp-6/igt@kms_busy@basic@flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22423/bat-adlp-6/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
Build changes
-------------
* Linux: CI_DRM_11290 -> Patchwork_22423
CI-20190529: 20190529
CI_DRM_11290: e4658cb77436a0a406de83fef483b52f84e17208 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6359: 57049558c452272b27eeb099fac07e55a924bbf9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22423: 2d74b0515d735ff44ad36fc6849a32a38893b649 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2d74b0515d73 drm/i915: avoid concurrent writes to aux_inv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22423/index.html
[-- Attachment #2: Type: text/html, Size: 3102 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-26 4:20 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-26 1:50 [PATCH] drm/i915: avoid concurrent writes to aux_inv fei.yang
2022-02-26 1:50 ` [Intel-gfx] " fei.yang
2022-02-26 3:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-02-26 3:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-26 4:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.