* [PATCH 1/3] drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock
@ 2022-03-01 12:28 Prike Liang
2022-03-01 12:28 ` [PATCH 2/3] drm/amdgpu: enable gfx power gating for GC 10.3.7 Prike Liang
2022-03-01 12:28 ` [PATCH 3/3] drm/amdgpu: enable gfxoff routine " Prike Liang
0 siblings, 2 replies; 4+ messages in thread
From: Prike Liang @ 2022-03-01 12:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Prike Liang, ray.huang
This will enable the following block clock gating.
- MC
- SDMA
- HDP
- ATHUB
- IH
- VCN/JPEG
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index f6aeef759ee1..05487894120a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -946,7 +946,17 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_GFX_RLC_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
- AMD_CG_SUPPORT_GFX_FGCG;
+ AMD_CG_SUPPORT_GFX_FGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_IH_CG |
+ AMD_CG_SUPPORT_VCN_MGCG |
+ AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amdgpu: enable gfx power gating for GC 10.3.7
2022-03-01 12:28 [PATCH 1/3] drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock Prike Liang
@ 2022-03-01 12:28 ` Prike Liang
2022-03-01 12:28 ` [PATCH 3/3] drm/amdgpu: enable gfxoff routine " Prike Liang
1 sibling, 0 replies; 4+ messages in thread
From: Prike Liang @ 2022-03-01 12:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Prike Liang, ray.huang
Enable gfx power gating for GC 10.3.7.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index fd7ded7799e2..e048635435a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8348,6 +8348,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 6):
+ case IP_VERSION(10, 3, 7):
data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
break;
@@ -8417,6 +8418,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 6):
+ case IP_VERSION(10, 3, 7):
gfx_v10_cntl_pg(adev, enable);
amdgpu_gfx_off_ctrl(adev, enable);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 05487894120a..e19f14c3ef59 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -959,7 +959,8 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
- AMD_PG_SUPPORT_JPEG;
+ AMD_PG_SUPPORT_JPEG |
+ AMD_PG_SUPPORT_GFX_PG;
adev->external_rev_id = adev->rev_id + 0x01;
break;
default:
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amdgpu: enable gfxoff routine for GC 10.3.7
2022-03-01 12:28 [PATCH 1/3] drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock Prike Liang
2022-03-01 12:28 ` [PATCH 2/3] drm/amdgpu: enable gfx power gating for GC 10.3.7 Prike Liang
@ 2022-03-01 12:28 ` Prike Liang
2022-03-01 14:00 ` Alex Deucher
1 sibling, 1 reply; 4+ messages in thread
From: Prike Liang @ 2022-03-01 12:28 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Prike Liang, ray.huang
Enable gfxoff routine for GC 10.3.7.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e048635435a2..92fdccc4a905 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6557,6 +6557,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
case IP_VERSION(10, 3, 5):
case IP_VERSION(10, 3, 6):
case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 7):
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -7857,6 +7858,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
case IP_VERSION(10, 3, 5):
case IP_VERSION(10, 3, 6):
case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 7):
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
/* wait for RLC_SAFE_MODE */
@@ -7894,6 +7896,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
case IP_VERSION(10, 3, 5):
case IP_VERSION(10, 3, 6):
case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 7):
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
break;
default:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 261a3749c089..05783b9b4b9a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -751,6 +751,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
+ case IP_VERSION(13, 0, 8):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0;
if (enable)
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu: enable gfxoff routine for GC 10.3.7
2022-03-01 12:28 ` [PATCH 3/3] drm/amdgpu: enable gfxoff routine " Prike Liang
@ 2022-03-01 14:00 ` Alex Deucher
0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-03-01 14:00 UTC (permalink / raw)
To: Prike Liang; +Cc: Deucher, Alexander, Huang Rui, amd-gfx list
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
On Tue, Mar 1, 2022 at 7:30 AM Prike Liang <Prike.Liang@amd.com> wrote:
>
> Enable gfxoff routine for GC 10.3.7.
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index e048635435a2..92fdccc4a905 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6557,6 +6557,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
> case IP_VERSION(10, 3, 5):
> case IP_VERSION(10, 3, 6):
> case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 3, 7):
> tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
> tmp &= 0xffffff00;
> tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
> @@ -7857,6 +7858,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
> case IP_VERSION(10, 3, 5):
> case IP_VERSION(10, 3, 6):
> case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 3, 7):
> WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
>
> /* wait for RLC_SAFE_MODE */
> @@ -7894,6 +7896,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
> case IP_VERSION(10, 3, 5):
> case IP_VERSION(10, 3, 6):
> case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 3, 7):
> WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
> break;
> default:
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 261a3749c089..05783b9b4b9a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -751,6 +751,7 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
> switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 1):
> case IP_VERSION(13, 0, 3):
> + case IP_VERSION(13, 0, 8):
> if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> return 0;
> if (enable)
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-03-01 14:00 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-01 12:28 [PATCH 1/3] drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblock Prike Liang
2022-03-01 12:28 ` [PATCH 2/3] drm/amdgpu: enable gfx power gating for GC 10.3.7 Prike Liang
2022-03-01 12:28 ` [PATCH 3/3] drm/amdgpu: enable gfxoff routine " Prike Liang
2022-03-01 14:00 ` Alex Deucher
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