[igt-dev] [PATCH i-g-t 0/6] Add i915 blt library + gem_ccs test

[igt-dev] [PATCH i-g-t 0/6] Add i915 blt library + gem_ccs test

[Zbigniew Kempczyński]

Enable DG2+ testing of flatccs.

Idea of library comes from Ayaz, just implementation differs due
to some reasons discovered during different tiling testing.

v3: rebased on top of local DG2 pciids
v4: fix tile64 - set mip tail
v5: use gem-pool in ctrl-surf-copy
    use uc mocs (Ayaz)
    address review comments (Kamil)

Cc: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>

Apoorva Singh (1):
  lib/i915: Introduce library intel_mocs

Chris Wilson (1):
  i915/gem_engine_topology: Add helpers for checking driver capabilities

Zbigniew Kempczyński (4):
  lib/i915/gem_create: Introduce gem-pool bo cache
  tests/api_intel_allocator: Verify gem-pool is working as expected
  lib/i915_blt: Add library for blitter
  tests/gem_ccs: Verify uncompressed and compressed blits

 .../igt-gpu-tools/igt-gpu-tools-docs.xml      |    2 +
 lib/i915/gem_create.c                         |  271 +++++
 lib/i915/gem_create.h                         |    4 +
 lib/i915/gem_engine_topology.c                |   39 +
 lib/i915/gem_engine_topology.h                |    5 +
 lib/i915/i915_blt.c                           | 1082 +++++++++++++++++
 lib/i915/i915_blt.h                           |  196 +++
 lib/i915/intel_mocs.c                         |   56 +
 lib/i915/intel_mocs.h                         |   25 +
 lib/igt_core.c                                |    2 +
 lib/meson.build                               |    2 +
 tests/i915/api_intel_allocator.c              |   58 +
 tests/i915/gem_ccs.c                          |  487 ++++++++
 tests/meson.build                             |    1 +
 14 files changed, 2230 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h
 create mode 100644 tests/i915/gem_ccs.c

-- 
2.32.0

[igt-dev] [PATCH i-g-t 1/6] lib/i915/gem_create: Introduce gem-pool bo cache

[Zbigniew Kempczyński]

Handling batchbuffers with softpin requires tracking its state otherwise
we can write to inflight batchbuffer and encounter gpu hang. Gem pool
adds such tracking (similar to libdrm bo cache) and provides free and
ready to use bo. If pool has no free bo new one is created what means pool
can be growing during test execution. When test completes freeing buffers
and memory is called from igt_core so no additional cleanup is necessary.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 .../igt-gpu-tools/igt-gpu-tools-docs.xml      |   1 +
 lib/i915/gem_create.c                         | 271 ++++++++++++++++++
 lib/i915/gem_create.h                         |   4 +
 lib/igt_core.c                                |   2 +
 4 files changed, 278 insertions(+)

diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index 0dc5a0b7e7..c22e70b712 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -56,6 +56,7 @@
   </chapter>
   <chapter>
     <title>igt/i915 API Reference</title>
+    <xi:include href="xml/gem_create.xml"/>
     <xi:include href="xml/gem_context.xml"/>
     <xi:include href="xml/gem_engine_topology.xml"/>
     <xi:include href="xml/gem_scheduler.xml"/>
diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c
index b2e8d5595f..605c45139d 100644
--- a/lib/i915/gem_create.c
+++ b/lib/i915/gem_create.c
@@ -4,12 +4,25 @@
  */
 
 #include <errno.h>
+#include <pthread.h>
 
+#include "drmtest.h"
 #include "gem_create.h"
 #include "i915_drm.h"
 #include "igt_core.h"
+#include "igt_list.h"
+#include "igt_map.h"
 #include "ioctl_wrappers.h"
 
+/**
+ * SECTION:gem_create
+ * @short_description: Helpers for dealing with objects creation
+ * @title: GEM Create
+ *
+ * This helper library contains functions used for handling creating gem
+ * objects.
+ */
+
 int __gem_create(int fd, uint64_t *size, uint32_t *handle)
 {
 	struct drm_i915_gem_create create = {
@@ -88,3 +101,261 @@ uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext)
 
 	return handle;
 }
+
+static struct igt_map *pool;
+static pthread_mutex_t pool_mutex = PTHREAD_MUTEX_INITIALIZER;
+
+struct pool_entry {
+	int fd;
+	uint32_t handle;
+	uint64_t size;		/* requested bo size */
+	uint64_t bo_size;	/* created bo size */
+	uint32_t region;
+	struct igt_list_head link;
+};
+
+struct pool_list {
+	uint64_t size;
+	struct igt_list_head list;
+};
+
+static struct pool_entry *find_or_create(int fd, struct pool_list *pl,
+					 uint64_t size, uint32_t region)
+{
+	struct pool_entry *pe;
+	bool found = false;
+
+	igt_list_for_each_entry(pe, &pl->list, link) {
+		if (pe->fd == fd && pe->size == size && pe->region == region &&
+		    !gem_bo_busy(fd, pe->handle)) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found) {
+		pe = calloc(1, sizeof(*pe));
+		if (!pe)
+			goto out;
+
+		pe->fd = fd;
+		pe->bo_size = size;
+		if (__gem_create_in_memory_regions(fd, &pe->handle, &pe->bo_size, region)) {
+			free(pe);
+			pe = NULL;
+			goto out;
+		}
+		pe->size = size;
+		pe->region = region;
+
+		igt_list_add_tail(&pe->link, &pl->list);
+	}
+
+out:
+	return pe;
+}
+
+/**
+ * gem_create_from_pool:
+ * @fd: open i915 drm file descriptor
+ * @size: pointer to size, on input it points to requested bo size,
+ * on output created bo size will be stored there
+ * @region: region in which bo should be created
+ *
+ * Function returns bo handle which is free to use (not busy). Internally
+ * it iterates over previously allocated bo and returns first free. If there
+ * are no free bo a new one is created.
+ *
+ * Returns: bo handle + created bo size (via pointer to size)
+ */
+uint32_t gem_create_from_pool(int fd, uint64_t *size, uint32_t region)
+{
+	struct pool_list *pl;
+	struct pool_entry *pe;
+
+	pthread_mutex_lock(&pool_mutex);
+
+	pl = igt_map_search(pool, size);
+	if (!pl) {
+		pl = calloc(1, sizeof(*pl));
+		if (!pl)
+			goto out;
+
+		IGT_INIT_LIST_HEAD(&pl->list);
+		pl->size = *size;
+		igt_map_insert(pool, &pl->size, pl);
+	}
+	pe = find_or_create(fd, pl, *size, region);
+
+out:
+	pthread_mutex_unlock(&pool_mutex);
+
+	igt_assert(pl && pe);
+
+	return pe->handle;
+}
+
+static void __pool_list_free_func(struct igt_map_entry *entry)
+{
+	free(entry->data);
+}
+
+static void __destroy_pool(struct igt_map *map, pthread_mutex_t *mutex)
+{
+	struct igt_map_entry *pos;
+	const struct pool_list *pl;
+	struct pool_entry *pe, *tmp;
+
+	if (!map)
+		return;
+
+	pthread_mutex_lock(mutex);
+
+	igt_map_foreach(map, pos) {
+		pl = pos->key;
+		igt_list_for_each_entry_safe(pe, tmp, &pl->list, link) {
+			gem_close(pe->fd, pe->handle);
+			igt_list_del(&pe->link);
+			free(pe);
+		}
+	}
+
+	pthread_mutex_unlock(mutex);
+
+	igt_map_destroy(map, __pool_list_free_func);
+}
+
+void gem_pool_dump(void)
+{
+	struct igt_map_entry *pos;
+	const struct pool_list *pl;
+	struct pool_entry *pe;
+
+	if (!pool)
+		return;
+
+	pthread_mutex_lock(&pool_mutex);
+
+	igt_debug("[pool]\n");
+	igt_map_foreach(pool, pos) {
+		pl = pos->key;
+		igt_debug("bucket [%llx]\n", (long long) pl->size);
+		igt_list_for_each_entry(pe, &pl->list, link)
+			igt_debug(" - handle: %u, size: %llx, bo_size: %llx, region: %x\n",
+				  pe->handle, (long long) pe->size,
+				  (long long) pe->bo_size, pe->region);
+	}
+
+	pthread_mutex_unlock(&pool_mutex);
+}
+
+#define GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001ULL
+static inline uint32_t hash_pool(const void *val)
+{
+	uint64_t hash = *(uint64_t *) val;
+
+	hash = hash * GOLDEN_RATIO_PRIME_64;
+	return hash >> 32;
+}
+
+static int equal_pool(const void *a, const void *b)
+{
+	struct pool_list *p1 = (struct pool_list *) a;
+	struct pool_list *p2 = (struct pool_list *) b;
+
+	return p1->size == p2->size;
+}
+
+/**
+ * gem_pool_init:
+ *
+ * Function initializes bo pool (kind of bo cache). Main purpose of it is to
+ * support working with softpin to achieve pipelined execution on gpu (without
+ * stalls).
+ *
+ * For example imagine code as follows:
+ *
+ * |[<!-- language="C" -->
+ * uint32_t bb = gem_create(fd, 4096);
+ * uint32_t *bbptr = gem_mmap__device_coherent(fd, bb, ...)
+ * uint32_t *cmd = bbptr;
+ * ...
+ * *cmd++ = ...gpu commands...
+ * ...
+ * *cmd++ = MI_BATCH_BUFFER_END;
+ * ...
+ * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- first execbuf
+ *
+ * cmd = bbptr;
+ * ...
+ * *cmd++ = ... next gpu commands...
+ * ...
+ * *cmd++ = MI_BATCH_BUFFER_END;
+ * ...
+ * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- second execbuf
+ * ]|
+ *
+ * Above code is prone to gpu hang because when bb was submitted to gpu
+ * we immediately started writing to it. If gpu started executing commands
+ * from first execbuf we're overwriting it leading to unpredicted behavior
+ * (partially execute from first and second commands or we get gpu hang).
+ * To avoid this we can sync after first execbuf but we will get stall
+ * in execution. For some tests it might be accepted but such "isolated"
+ * execution hides bugs (synchronization, cache flushes, etc).
+ *
+ * So, to achive pipelined execution we need to use another bb. If we would
+ * like to enqueue more work which is serialized we would need more bbs
+ * (depends on execution speed). Handling this manually is cumbersome as
+ * we need to track all bb and their status (busy or free).
+ *
+ * Solution to above is gem pool. It returns first handle of requested size
+ * which is not busy (or create a new one if there's none or all of bo are
+ * in use). Here's an example how to use it:
+ *
+ * |[<!-- language="C" -->
+ * uint64_t bbsize = 4096;
+ * uint32_t bb = gem_create_from_pool(fd, &bbsize, REGION_SMEM);
+ * uint32_t *bbptr = gem_mmap__device_coherent(fd, bb, ...)
+ * uint32_t *cmd = bbptr;
+ * ...
+ * *cmd++ = ...gpu commands...
+ * ...
+ * *cmd++ = MI_BATCH_BUFFER_END;
+ * gem_munmap(bbptr, bbsize);
+ * ...
+ * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- first execbuf
+ *
+ * bbsize = 4096;
+ * bb = gem_create_from_pool(fd, &bbsize, REGION_SMEM);
+ * cmd = bbptr;
+ * ...
+ * *cmd++ = ... next gpu commands...
+ * ...
+ * *cmd++ = MI_BATCH_BUFFER_END;
+ * gem_munmap(bbptr, bbsize);
+ * ...
+ * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- second execbuf
+ * ]|
+ *
+ * Assuming first execbuf is executed we will get new bb handle when we call
+ * gem_create_from_pool(). When test completes pool is freed automatically
+ * in igt core (all handles will be closed, memory will be freed and gem pool
+ * will be reinitialized for next test).
+ *
+ * Some explanation is needed why we need to put pointer to size instead of
+ * passing absolute value. On discrete regarding memory placement (region)
+ * object created in the memory can be bigger than requested. Especially when
+ * we use allocator to handle vm space and we allocate vma with requested
+ * size (which is smaller than bo created) we can overlap with next allocation
+ * and get -ENOSPC.
+ */
+void gem_pool_init(void)
+{
+	pthread_mutex_init(&pool_mutex, NULL);
+	__destroy_pool(pool, &pool_mutex);
+	pool = igt_map_create(hash_pool, equal_pool);
+}
+
+igt_constructor {
+	gem_pool_init();
+}
diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h
index c2b531b4d7..c32a815d60 100644
--- a/lib/i915/gem_create.h
+++ b/lib/i915/gem_create.h
@@ -16,4 +16,8 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
                      struct i915_user_extension *ext);
 uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext);
 
+void gem_pool_init(void);
+void gem_pool_dump(void);
+uint32_t gem_create_from_pool(int fd, uint64_t *size, uint32_t region);
+
 #endif /* GEM_CREATE_H */
diff --git a/lib/igt_core.c b/lib/igt_core.c
index f2c701deab..6dad3c8485 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -58,6 +58,7 @@
 #include <glib.h>
 
 #include "drmtest.h"
+#include "i915/gem_create.h"
 #include "intel_allocator.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
@@ -1428,6 +1429,7 @@ __noreturn static void exit_subtest(const char *result)
 	 */
 	intel_allocator_init();
 	intel_bb_reinit_allocator();
+	gem_pool_init();
 
 	if (!in_dynamic_subtest)
 		_igt_dynamic_tests_executed = -1;
-- 
2.32.0

[igt-dev] [PATCH i-g-t 2/6] tests/api_intel_allocator: Verify gem-pool is working as expected

[Zbigniew Kempczyński]

Simple check which acquires buffer objects from gem-pool. It verifies:
- object reuse (previously created is completed in execbuf)
- object creation (submitting batches when spinner is executing).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 tests/i915/api_intel_allocator.c | 58 ++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c
index a652caf4ec..a7929e9b13 100644
--- a/tests/i915/api_intel_allocator.c
+++ b/tests/i915/api_intel_allocator.c
@@ -692,6 +692,60 @@ static void fork_reopen_allocator(int fd, uint8_t type)
 	intel_allocator_multiprocess_stop();
 }
 
+static uint32_t single_exec_from_pool(int i915, uint64_t ahnd, uint64_t size)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj = {};
+	uint32_t bb = gem_create_from_pool(i915, &size, REGION_SMEM);
+	uint32_t *bbptr;
+
+	bbptr = gem_mmap__device_coherent(i915, bb, 0, size, PROT_WRITE);
+	*bbptr = MI_BATCH_BUFFER_END;
+	gem_munmap(bbptr, size);
+	obj.offset = get_offset(ahnd, bb, size, 0);
+	if (ahnd)
+		obj.flags = EXEC_OBJECT_PINNED;
+	obj.handle = bb;
+	execbuf.buffer_count = 1;
+	execbuf.buffers_ptr = to_user_pointer(&obj);
+	gem_execbuf(i915, &execbuf);
+
+	return bb;
+}
+
+static void gem_pool(int i915)
+{
+	uint32_t bb[4];
+	uint64_t ahnd = get_reloc_ahnd(i915, 0);
+	igt_spin_t *spin;
+
+	bb[0] = single_exec_from_pool(i915, ahnd, 4096);
+	gem_sync(i915, bb[0]);
+	bb[1] = single_exec_from_pool(i915, ahnd, 4096);
+	igt_assert(bb[0] == bb[1]);
+
+	bb[2] = single_exec_from_pool(i915, ahnd, 8192);
+	gem_sync(i915, bb[2]);
+	bb[3] = single_exec_from_pool(i915, ahnd, 8192);
+	igt_assert(bb[2] == bb[3]);
+	igt_assert(bb[0] != bb[2]);
+
+	spin = igt_spin_new(i915,
+			    .ahnd = ahnd,
+			    .engine = I915_EXEC_DEFAULT);
+	bb[0] = single_exec_from_pool(i915, ahnd, 4096);
+	bb[1] = single_exec_from_pool(i915, ahnd, 4096);
+	bb[2] = single_exec_from_pool(i915, ahnd, 8192);
+	bb[3] = single_exec_from_pool(i915, ahnd, 8192);
+	igt_spin_free(i915, spin);
+	igt_assert(bb[0] != bb[1]);
+	igt_assert(bb[2] != bb[3]);
+
+	put_ahnd(ahnd);
+
+	gem_pool_dump();
+}
+
 struct allocators {
 	const char *name;
 	uint8_t type;
@@ -790,6 +844,10 @@ igt_main
 	igt_subtest_f("execbuf-with-allocator")
 		execbuf_with_allocator(fd);
 
+	igt_describe("Verifies creating and executing bb from gem pool");
+	igt_subtest_f("gem-pool")
+		gem_pool(fd);
+
 	igt_fixture
 		close(fd);
 }
-- 
2.32.0

[igt-dev] [PATCH i-g-t 3/6] lib/i915: Introduce library intel_mocs

[Zbigniew Kempczyński]

From: Apoorva Singh <apoorva1.singh@intel.com>

Add new library intel_mocs for mocs settings.

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/i915/intel_mocs.c | 56 +++++++++++++++++++++++++++++++++++++++++++
 lib/i915/intel_mocs.h | 25 +++++++++++++++++++
 lib/meson.build       |  1 +
 3 files changed, 82 insertions(+)
 create mode 100644 lib/i915/intel_mocs.c
 create mode 100644 lib/i915/intel_mocs.h

diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
new file mode 100644
index 0000000000..63ead1118f
--- /dev/null
+++ b/lib/i915/intel_mocs.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "igt.h"
+#include "i915/gem.h"
+#include "intel_mocs.h"
+
+static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
+{
+	uint16_t devid = intel_get_drm_devid(fd);
+
+	/*
+	 * Gen >= 12 onwards don't have a setting for PTE,
+	 * so using I915_MOCS_PTE as mocs index may leads to
+	 * some undefined MOCS behavior.
+	 * This helper function is providing current UC as well
+	 * as WB MOCS index based on platform.
+	 */
+	if (IS_DG1(devid)) {
+		mocs->uc_index = DG1_MOCS_UC_IDX;
+		mocs->wb_index = DG1_MOCS_WB_IDX;
+	} else if (IS_DG2(devid)) {
+		mocs->uc_index = DG2_MOCS_UC_IDX;
+		mocs->wb_index = DG2_MOCS_WB_IDX;
+
+	} else if (IS_GEN12(devid)) {
+		mocs->uc_index = GEN12_MOCS_UC_IDX;
+		mocs->wb_index = GEN12_MOCS_WB_IDX;
+	} else {
+		mocs->uc_index = I915_MOCS_PTE;
+		mocs->wb_index = I915_MOCS_CACHED;
+		igt_info("C1\n");
+	}
+}
+
+/* BitField [6:1] represents index to MOCS Tables
+ * BitField [0] represents Encryption/Decryption
+ */
+
+uint8_t intel_get_wb_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.wb_index << 1;
+}
+
+uint8_t intel_get_uc_mocs(int fd)
+{
+	struct drm_i915_mocs_index mocs;
+
+	get_mocs_index(fd, &mocs);
+	return mocs.uc_index << 1;
+}
diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
new file mode 100644
index 0000000000..c05569f426
--- /dev/null
+++ b/lib/i915/intel_mocs.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_MOCS_H
+#define _INTEL_MOCS_H
+
+#define DG1_MOCS_UC_IDX			1
+#define DG1_MOCS_WB_IDX			5
+#define DG2_MOCS_UC_IDX			1
+#define DG2_MOCS_WB_IDX			3
+#define GEN12_MOCS_UC_IDX			3
+#define GEN12_MOCS_WB_IDX			2
+#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
+#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
+
+struct drm_i915_mocs_index {
+	uint8_t uc_index;
+	uint8_t wb_index;
+};
+
+uint8_t intel_get_wb_mocs(int fd);
+uint8_t intel_get_uc_mocs(int fd);
+#endif /* _INTEL_MOCS_H */
diff --git a/lib/meson.build b/lib/meson.build
index 3e43316d1e..a5fe91dc99 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,7 @@ lib_sources = [
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
 	'i915/intel_memory_region.c',
+	'i915/intel_mocs.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
-- 
2.32.0

[igt-dev] [PATCH i-g-t 4/6] i915/gem_engine_topology: Add helpers for checking driver capabilities

[Zbigniew Kempczyński]

From: Chris Wilson <chris.p.wilson@intel.com>

If driver is able to report capabilities we want to use them in easy way.
For example it can support blitter "block_copy" (XY_BLOCK_COPY_BLT
command) and reports it in sysfs. We add then capabilities helpers to
read these properties. Helpers allows checking does driver knows
capability (by checking sysfs "known_capabilities" file) and supports it
(by checking sysfs "capabilities" file). Dedicated helper was added to
verify "block_copy" capability.

Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
---
 lib/i915/gem_engine_topology.c | 39 ++++++++++++++++++++++++++++++++++
 lib/i915/gem_engine_topology.h |  5 +++++
 2 files changed, 44 insertions(+)

diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
index bd12d0bc98..ca3333c252 100644
--- a/lib/i915/gem_engine_topology.c
+++ b/lib/i915/gem_engine_topology.c
@@ -534,6 +534,45 @@ void gem_engine_properties_restore(int fd, const struct gem_engine_properties *s
 	}
 }
 
+static bool
+__gem_engine_has_capability(int i915, const char *engine,
+			    const char *attr, const char *cap)
+{
+	char buf[4096] = {};
+	FILE *file;
+
+	file = __open_attr(igt_sysfs_open(i915), "r",
+			   "engine", engine, attr, NULL);
+	if (!file)
+		return NULL;
+
+	fread(buf, 1, sizeof(buf) - 1, file);
+	fclose(file);
+
+	return strstr(buf, cap);
+}
+
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "capabilities", cap);
+}
+
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
+{
+	return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
+}
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
+{
+	if (engine->class != I915_ENGINE_CLASS_COPY)
+		return false;
+
+	if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
+		return intel_gen(intel_get_drm_devid(i915)) >= 12;
+
+	return gem_engine_has_capability(i915, engine->name, "block_copy");
+}
+
 uint32_t gem_engine_mmio_base(int i915, const char *engine)
 {
 	unsigned int mmio = 0;
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
index b413aa8aba..987f2bf944 100644
--- a/lib/i915/gem_engine_topology.h
+++ b/lib/i915/gem_engine_topology.h
@@ -133,6 +133,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
 
 uint32_t gem_engine_mmio_base(int i915, const char *engine);
 
+bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
+bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
+
+bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
+
 void dyn_sysfs_engines(int i915, int engines, const char *file,
 		       void (*test)(int i915, int engine));
 
-- 
2.32.0

[igt-dev] [PATCH i-g-t 5/6] lib/i915_blt: Add library for blitter

[Zbigniew Kempczyński]

Blitter commands became complicated thus manual bitshifting is error
prone and hard debugable - XY_BLOCK_COPY_BLT is the best example -
in extended version (for DG2+) it takes 20 dwords of command data.
To avoid mistakes and dozens of arguments for command library provides
input data in more structured form.

Currently supported commands:
- XY_BLOCK_COPY_BLT:
  a)  TGL/DG1 uses shorter version of command which doesn't support
      compression
  b)  DG2+ command is extended and supports compression
- XY_CTRL_SURF_COPY_BLT
- XY_FAST_COPY_BLT

Source, destination and batchbuffer are provided to blitter functions
as objects (structs). This increases readability and allows use same
object in many functions. Only drawback of such attitude is some fields
used in one function may be ignored in another. As an example is
blt_copy_object which contains a lot of information about gem object.
In block-copy all of data are used but in fast-copy only some of them
(fast-copy doesn't support compression).

v2-v3: address review comments (Kamil)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 .../igt-gpu-tools/igt-gpu-tools-docs.xml      |    1 +
 lib/i915/i915_blt.c                           | 1082 +++++++++++++++++
 lib/i915/i915_blt.h                           |  196 +++
 lib/meson.build                               |    1 +
 4 files changed, 1280 insertions(+)
 create mode 100644 lib/i915/i915_blt.c
 create mode 100644 lib/i915/i915_blt.h

diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index c22e70b712..1774256530 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -61,6 +61,7 @@
     <xi:include href="xml/gem_engine_topology.xml"/>
     <xi:include href="xml/gem_scheduler.xml"/>
     <xi:include href="xml/gem_submission.xml"/>
+    <xi:include href="xml/i915_blt.xml"/>
     <xi:include href="xml/intel_ctx.xml"/>
   </chapter>
   <xi:include href="xml/igt_test_programs.xml"/>
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
new file mode 100644
index 0000000000..8d46e51fb7
--- /dev/null
+++ b/lib/i915/i915_blt.c
@@ -0,0 +1,1082 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include <cairo.h>
+#include "drm.h"
+#include "igt.h"
+#include "gem_create.h"
+#include "i915_blt.h"
+
+#define BITRANGE(start, end) (end - start + 1)
+
+enum blt_special_mode {
+	SM_NONE,
+	SM_FULL_RESOLVE,
+	SM_PARTIAL_RESOLVE,
+	SM_RESERVED,
+};
+
+enum blt_aux_mode {
+	AM_AUX_NONE,
+	AM_AUX_CCS_E = 5,
+};
+
+enum blt_target_mem {
+	TM_LOCAL_MEM,
+	TM_SYSTEM_MEM,
+};
+
+struct gen12_block_copy_data {
+	struct {
+		uint32_t length:			BITRANGE(0, 7);
+		uint32_t rsvd1:				BITRANGE(8, 8);
+		uint32_t multisamples:			BITRANGE(9, 11);
+		uint32_t special_mode:			BITRANGE(12, 13);
+		uint32_t rsvd0:				BITRANGE(14, 18);
+		uint32_t color_depth:			BITRANGE(19, 21);
+		uint32_t opcode:			BITRANGE(22, 28);
+		uint32_t client:			BITRANGE(29, 31);
+	} dw00;
+
+	struct {
+		uint32_t dst_pitch:			BITRANGE(0, 17);
+		uint32_t dst_aux_mode:			BITRANGE(18, 20);
+		uint32_t dst_mocs:			BITRANGE(21, 27);
+		uint32_t dst_ctrl_surface_type:		BITRANGE(28, 28);
+		uint32_t dst_compression:		BITRANGE(29, 29);
+		uint32_t dst_tiling:			BITRANGE(30, 31);
+	} dw01;
+
+	struct {
+		int32_t dst_x1:				BITRANGE(0, 15);
+		int32_t dst_y1:				BITRANGE(16, 31);
+	} dw02;
+
+	struct {
+		int32_t dst_x2:				BITRANGE(0, 15);
+		int32_t dst_y2:				BITRANGE(16, 31);
+	} dw03;
+
+	struct {
+		uint32_t dst_address_lo;
+	} dw04;
+
+	struct {
+		uint32_t dst_address_hi;
+	} dw05;
+
+	struct {
+		uint32_t dst_x_offset:			BITRANGE(0, 13);
+		uint32_t rsvd1:				BITRANGE(14, 15);
+		uint32_t dst_y_offset:			BITRANGE(16, 29);
+		uint32_t rsvd0:				BITRANGE(30, 30);
+		uint32_t dst_target_memory:		BITRANGE(31, 31);
+	} dw06;
+
+	struct {
+		int32_t src_x1:				BITRANGE(0, 15);
+		int32_t src_y1:				BITRANGE(16, 31);
+	} dw07;
+
+	struct {
+		uint32_t src_pitch:			BITRANGE(0, 17);
+		uint32_t src_aux_mode:			BITRANGE(18, 20);
+		uint32_t src_mocs:			BITRANGE(21, 27);
+		uint32_t src_ctrl_surface_type:		BITRANGE(28, 28);
+		uint32_t src_compression:		BITRANGE(29, 29);
+		uint32_t src_tiling:			BITRANGE(30, 31);
+	} dw08;
+
+	struct {
+		uint32_t src_address_lo;
+	} dw09;
+
+	struct {
+		uint32_t src_address_hi;
+	} dw10;
+
+	struct {
+		uint32_t src_x_offset:			BITRANGE(0, 13);
+		uint32_t rsvd1:				BITRANGE(14, 15);
+		uint32_t src_y_offset:			BITRANGE(16, 29);
+		uint32_t rsvd0:				BITRANGE(30, 30);
+		uint32_t src_target_memory:		BITRANGE(31, 31);
+	} dw11;
+};
+
+struct gen12_block_copy_data_ext {
+	struct {
+		uint32_t src_compression_format:	BITRANGE(0, 4);
+		uint32_t src_clear_value_enable:	BITRANGE(5, 5);
+		uint32_t src_clear_address_low:		BITRANGE(6, 31);
+	} dw12;
+
+	union {
+		/* DG2, XEHP */
+		uint32_t src_clear_address_hi0;
+		/* Others */
+		uint32_t src_clear_address_hi1;
+	} dw13;
+
+	struct {
+		uint32_t dst_compression_format:	BITRANGE(0, 4);
+		uint32_t dst_clear_value_enable:	BITRANGE(5, 5);
+		uint32_t dst_clear_address_low:		BITRANGE(6, 31);
+	} dw14;
+
+	union {
+		/* DG2, XEHP */
+		uint32_t dst_clear_address_hi0;
+		/* Others */
+		uint32_t dst_clear_address_hi1;
+	} dw15;
+
+	struct {
+		uint32_t dst_surface_height:		BITRANGE(0, 13);
+		uint32_t dst_surface_width:		BITRANGE(14, 27);
+		uint32_t rsvd0:				BITRANGE(28, 28);
+		uint32_t dst_surface_type:		BITRANGE(29, 31);
+	} dw16;
+
+	struct {
+		uint32_t dst_lod:			BITRANGE(0, 3);
+		uint32_t dst_surface_qpitch:		BITRANGE(4, 18);
+		uint32_t rsvd0:				BITRANGE(19, 20);
+		uint32_t dst_surface_depth:		BITRANGE(21, 31);
+	} dw17;
+
+	struct {
+		uint32_t dst_horizontal_align:		BITRANGE(0, 1);
+		uint32_t rsvd0:				BITRANGE(2, 2);
+		uint32_t dst_vertical_align:		BITRANGE(3, 4);
+		uint32_t rsvd1:				BITRANGE(5, 7);
+		uint32_t dst_mip_tail_start_lod:	BITRANGE(8, 11);
+		uint32_t rsvd2:				BITRANGE(12, 17);
+		uint32_t dst_depth_stencil_resource:	BITRANGE(18, 18);
+		uint32_t rsvd3:				BITRANGE(19, 20);
+		uint32_t dst_array_index:		BITRANGE(21, 31);
+	} dw18;
+
+	struct {
+		uint32_t src_surface_height:		BITRANGE(0, 13);
+		uint32_t src_surface_width:		BITRANGE(14, 27);
+		uint32_t rsvd0:				BITRANGE(28, 28);
+		uint32_t src_surface_type:		BITRANGE(29, 31);
+	} dw19;
+
+	struct {
+		uint32_t src_lod:			BITRANGE(0, 3);
+		uint32_t src_surface_qpitch:		BITRANGE(4, 18);
+		uint32_t rsvd0:				BITRANGE(19, 20);
+		uint32_t src_surface_depth:		BITRANGE(21, 31);
+	} dw20;
+
+	struct {
+		uint32_t src_horizontal_align:		BITRANGE(0, 1);
+		uint32_t rsvd0:				BITRANGE(2, 2);
+		uint32_t src_vertical_align:		BITRANGE(3, 4);
+		uint32_t rsvd1:				BITRANGE(5, 7);
+		uint32_t src_mip_tail_start_lod:	BITRANGE(8, 11);
+		uint32_t rsvd2:				BITRANGE(12, 17);
+		uint32_t src_depth_stencil_resource:	BITRANGE(18, 18);
+		uint32_t rsvd3:				BITRANGE(19, 20);
+		uint32_t src_array_index:		BITRANGE(21, 31);
+	} dw21;
+};
+
+/**
+ * blt_supports_compression:
+ * @i915: drm fd
+ *
+ * Function checks if HW supports flatccs compression in blitter commands
+ * on @i915 device.
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_supports_compression(int i915)
+{
+	uint32_t devid = intel_get_drm_devid(i915);
+
+	return HAS_FLATCCS(devid);
+}
+
+/**
+ * blt_supports_tiling:
+ * @i915: drm fd
+ * @tiling: tiling id
+ *
+ * Function checks if blitter supports @tiling on @i915 device.
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_supports_tiling(int i915, enum blt_tiling tiling)
+{
+	uint32_t devid = intel_get_drm_devid(i915);
+
+	if (tiling == T_XMAJOR) {
+		if (IS_TIGERLAKE(devid) || IS_DG1(devid))
+			return false;
+		else
+			return true;
+	}
+
+	if (tiling == T_YMAJOR) {
+		if (IS_TIGERLAKE(devid) || IS_DG1(devid))
+			return true;
+		else
+			return false;
+	}
+
+	return true;
+}
+
+/**
+ * blt_tiling_name:
+ * @tiling: tiling id
+ *
+ * Returns:
+ * name of @tiling passed. Useful to build test names.
+ */
+const char *blt_tiling_name(enum blt_tiling tiling)
+{
+	switch (tiling) {
+	case T_LINEAR: return "linear";
+	case T_XMAJOR: return "xmajor";
+	case T_YMAJOR: return "ymajor";
+	case T_TILE4:  return "tile4";
+	case T_TILE64: return "tile64";
+	}
+
+	igt_warn("invalid tiling passed: %d\n", tiling);
+	return NULL;
+}
+
+static int __block_tiling(enum blt_tiling tiling)
+{
+	switch (tiling) {
+	case T_LINEAR: return 0;
+	case T_XMAJOR: return 1;
+	case T_YMAJOR: return 1;
+	case T_TILE4:  return 2;
+	case T_TILE64: return 3;
+	}
+
+	igt_warn("invalid tiling passed: %d\n", tiling);
+	return 0;
+}
+
+static int __special_mode(const struct blt_copy_data *blt)
+{
+	if (blt->src.handle == blt->dst.handle &&
+	    blt->src.compression && !blt->dst.compression)
+		return SM_FULL_RESOLVE;
+
+
+	return SM_NONE;
+}
+
+static int __memory_type(uint32_t region)
+{
+	igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
+		     IS_SYSTEM_MEMORY_REGION(region),
+		     "Invalid region: %x\n", region);
+
+	if (IS_DEVICE_MEMORY_REGION(region))
+		return TM_LOCAL_MEM;
+	return TM_SYSTEM_MEM;
+}
+
+static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
+{
+	if (obj->compression == COMPRESSION_ENABLED) {
+		igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region),
+			     "XY_BLOCK_COPY_BLT supports compression "
+			     "on device memory only\n");
+		return AM_AUX_CCS_E;
+	}
+
+	return AM_AUX_NONE;
+}
+
+static void fill_data(struct gen12_block_copy_data *data,
+		      const struct blt_copy_data *blt,
+		      uint64_t src_offset, uint64_t dst_offset,
+		      bool extended_command)
+{
+	data->dw00.client = 0x2;
+	data->dw00.opcode = 0x41;
+	data->dw00.color_depth = blt->color_depth;
+	data->dw00.special_mode = __special_mode(blt);
+	data->dw00.length = extended_command ? 20 : 10;
+
+	data->dw01.dst_pitch = blt->dst.pitch - 1;
+	data->dw01.dst_aux_mode = __aux_mode(&blt->dst);
+	data->dw01.dst_mocs = blt->dst.mocs;
+	data->dw01.dst_compression = blt->dst.compression;
+	data->dw01.dst_tiling = __block_tiling(blt->dst.tiling);
+
+	if (blt->dst.compression)
+		data->dw01.dst_ctrl_surface_type = blt->dst.compression_type;
+
+	data->dw02.dst_x1 = blt->dst.x1;
+	data->dw02.dst_y1 = blt->dst.y1;
+
+	data->dw03.dst_x2 = blt->dst.x2;
+	data->dw03.dst_y2 = blt->dst.y2;
+
+	data->dw04.dst_address_lo = dst_offset;
+	data->dw05.dst_address_hi = dst_offset >> 32;
+
+	data->dw06.dst_x_offset = blt->dst.x_offset;
+	data->dw06.dst_y_offset = blt->dst.y_offset;
+	data->dw06.dst_target_memory = __memory_type(blt->dst.region);
+
+	data->dw07.src_x1 = blt->src.x1;
+	data->dw07.src_y1 = blt->src.y1;
+
+	data->dw08.src_pitch = blt->src.pitch - 1;
+	data->dw08.src_aux_mode = __aux_mode(&blt->src);
+	data->dw08.src_mocs = blt->src.mocs;
+	data->dw08.src_compression = blt->src.compression;
+	data->dw08.src_tiling = __block_tiling(blt->src.tiling);
+
+	if (blt->src.compression)
+		data->dw08.src_ctrl_surface_type = blt->src.compression_type;
+
+	data->dw09.src_address_lo = src_offset;
+	data->dw10.src_address_hi = src_offset >> 32;
+
+	data->dw11.src_x_offset = blt->src.x_offset;
+	data->dw11.src_y_offset = blt->src.y_offset;
+	data->dw11.src_target_memory = __memory_type(blt->src.region);
+}
+
+static void fill_data_ext(struct gen12_block_copy_data_ext *dext,
+			  const struct blt_block_copy_data_ext *ext)
+{
+	dext->dw12.src_compression_format = ext->src.compression_format;
+	dext->dw12.src_clear_value_enable = ext->src.clear_value_enable;
+	dext->dw12.src_clear_address_low = ext->src.clear_address;
+
+	dext->dw13.src_clear_address_hi0 = ext->src.clear_address >> 32;
+
+	dext->dw14.dst_compression_format = ext->dst.compression_format;
+	dext->dw14.dst_clear_value_enable = ext->dst.clear_value_enable;
+	dext->dw14.dst_clear_address_low = ext->dst.clear_address;
+
+	dext->dw15.dst_clear_address_hi0 = ext->dst.clear_address >> 32;
+
+	dext->dw16.dst_surface_width = ext->dst.surface_width - 1;
+	dext->dw16.dst_surface_height = ext->dst.surface_height - 1;
+	dext->dw16.dst_surface_type = ext->dst.surface_type;
+
+	dext->dw17.dst_lod = ext->dst.lod;
+	dext->dw17.dst_surface_depth = ext->dst.surface_depth;
+	dext->dw17.dst_surface_qpitch = ext->dst.surface_qpitch;
+
+	dext->dw18.dst_horizontal_align = ext->dst.horizontal_align;
+	dext->dw18.dst_vertical_align = ext->dst.vertical_align;
+	dext->dw18.dst_mip_tail_start_lod = ext->dst.mip_tail_start_lod;
+	dext->dw18.dst_depth_stencil_resource = ext->dst.depth_stencil_resource;
+	dext->dw18.dst_array_index = ext->dst.array_index;
+
+	dext->dw19.src_surface_width = ext->src.surface_width - 1;
+	dext->dw19.src_surface_height = ext->src.surface_height - 1;
+
+	dext->dw19.src_surface_type = ext->src.surface_type;
+
+	dext->dw20.src_lod = ext->src.lod;
+	dext->dw20.src_surface_depth = ext->src.surface_depth;
+	dext->dw20.src_surface_qpitch = ext->src.surface_qpitch;
+
+	dext->dw21.src_horizontal_align = ext->src.horizontal_align;
+	dext->dw21.src_vertical_align = ext->src.vertical_align;
+	dext->dw21.src_mip_tail_start_lod = ext->src.mip_tail_start_lod;
+	dext->dw21.src_depth_stencil_resource = ext->src.depth_stencil_resource;
+	dext->dw21.src_array_index = ext->src.array_index;
+}
+
+static void dump_bb_cmd(struct gen12_block_copy_data *data)
+{
+	uint32_t *cmd = (uint32_t *) data;
+
+	igt_info("details:\n");
+	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, color depth: %d, "
+		 "special mode: %d, length: %d>\n",
+		 cmd[0],
+		 data->dw00.client, data->dw00.opcode, data->dw00.color_depth,
+		 data->dw00.special_mode, data->dw00.length);
+	igt_info(" dw01: [%08x] dst <pitch: %d, aux: %d, mocs: %d, compr: %d, "
+		 "tiling: %d, ctrl surf type: %d>\n",
+		 cmd[1], data->dw01.dst_pitch, data->dw01.dst_aux_mode,
+		 data->dw01.dst_mocs, data->dw01.dst_compression,
+		 data->dw01.dst_tiling, data->dw01.dst_ctrl_surface_type);
+	igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
+		 cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
+	igt_info(" dw03: [%08x]          <x2: %d, y2: %d>\n",
+		 cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
+	igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
+		 cmd[4], data->dw04.dst_address_lo);
+	igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
+		 cmd[5], data->dw05.dst_address_hi);
+	igt_info(" dw06: [%08x] dst <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
+		 cmd[6], data->dw06.dst_x_offset, data->dw06.dst_y_offset,
+		 data->dw06.dst_target_memory);
+	igt_info(" dw07: [%08x] src geom <x1: %d, y1: %d>\n",
+		 cmd[7], data->dw07.src_x1, data->dw07.src_y1);
+	igt_info(" dw08: [%08x] src <pitch: %d, aux: %d, mocs: %d, compr: %d, "
+		 "tiling: %d, ctrl surf type: %d>\n",
+		 cmd[8], data->dw08.src_pitch, data->dw08.src_aux_mode,
+		 data->dw08.src_mocs, data->dw08.src_compression,
+		 data->dw08.src_tiling, data->dw08.src_ctrl_surface_type);
+	igt_info(" dw09: [%08x] src offset lo (0x%x)\n",
+		 cmd[9], data->dw09.src_address_lo);
+	igt_info(" dw10: [%08x] src offset hi (0x%x)\n",
+		 cmd[10], data->dw10.src_address_hi);
+	igt_info(" dw11: [%08x] src <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
+		 cmd[11], data->dw11.src_x_offset, data->dw11.src_y_offset,
+		 data->dw11.src_target_memory);
+}
+
+static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
+{
+	uint32_t *cmd = (uint32_t *) data;
+
+	igt_info("ext details:\n");
+	igt_info(" dw12: [%08x] src <compression fmt: %d, clear value enable: %d, "
+		 "clear address low: 0x%x>\n",
+		 cmd[0],
+		 data->dw12.src_compression_format,
+		 data->dw12.src_clear_value_enable,
+		 data->dw12.src_clear_address_low);
+	igt_info(" dw13: [%08x] src clear address hi: 0x%x\n",
+		 cmd[1], data->dw13.src_clear_address_hi0);
+	igt_info(" dw14: [%08x] dst <compression fmt: %d, clear value enable: %d, "
+		 "clear address low: 0x%x>\n",
+		 cmd[2],
+		 data->dw14.dst_compression_format,
+		 data->dw14.dst_clear_value_enable,
+		 data->dw14.dst_clear_address_low);
+	igt_info(" dw15: [%08x] dst clear address hi: 0x%x\n",
+		 cmd[3], data->dw15.dst_clear_address_hi0);
+	igt_info(" dw16: [%08x] dst surface <width: %d, height: %d, type: %d>\n",
+		 cmd[4], data->dw16.dst_surface_width,
+		 data->dw16.dst_surface_height, data->dw16.dst_surface_type);
+	igt_info(" dw17: [%08x] dst surface <lod: %d, depth: %d, qpitch: %d>\n",
+		 cmd[5], data->dw17.dst_lod,
+		 data->dw17.dst_surface_depth, data->dw17.dst_surface_qpitch);
+	igt_info(" dw18: [%08x] dst <halign: %d, valign: %d, mip tail: %d, "
+		 "depth stencil: %d, array index: %d>\n",
+		 cmd[6],
+		 data->dw18.dst_horizontal_align,
+		 data->dw18.dst_vertical_align,
+		 data->dw18.dst_mip_tail_start_lod,
+		 data->dw18.dst_depth_stencil_resource,
+		 data->dw18.dst_array_index);
+
+	igt_info(" dw19: [%08x] src surface <width: %d, height: %d, type: %d>\n",
+		 cmd[7], data->dw19.src_surface_width,
+		 data->dw19.src_surface_height, data->dw19.src_surface_type);
+	igt_info(" dw20: [%08x] src surface <lod: %d, depth: %d, qpitch: %d>\n",
+		 cmd[8], data->dw20.src_lod,
+		 data->dw20.src_surface_depth, data->dw20.src_surface_qpitch);
+	igt_info(" dw21: [%08x] src <halign: %d, valign: %d, mip tail: %d, "
+		 "depth stencil: %d, array index: %d>\n",
+		 cmd[9],
+		 data->dw21.src_horizontal_align,
+		 data->dw21.src_vertical_align,
+		 data->dw21.src_mip_tail_start_lod,
+		 data->dw21.src_depth_stencil_resource,
+		 data->dw21.src_array_index);
+}
+
+/**
+ * blt_block_copy:
+ * @i915: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: basic blitter data (for TGL/DG1 which doesn't support ext version)
+ * @ext: extended blitter data (for DG2+, supports flatccs compression)
+ *
+ * Function does blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_block_copy(int i915,
+		   const intel_ctx_t *ctx,
+		   const struct intel_execution_engine2 *e,
+		   uint64_t ahnd,
+		   const struct blt_copy_data *blt,
+		   const struct blt_block_copy_data_ext *ext)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct gen12_block_copy_data data = {};
+	struct gen12_block_copy_data_ext dext = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	uint32_t *bb;
+	int i, ret;
+
+	igt_assert_f(ahnd, "block-copy supports softpin only\n");
+	igt_assert_f(blt, "block-copy requires data to do blit\n");
+
+	alignment = gem_detect_safe_alignment(i915);
+	src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+	if (__special_mode(blt) == SM_FULL_RESOLVE)
+		dst_offset = src_offset;
+	else
+		dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+	bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+	fill_data(&data, blt, src_offset, dst_offset, ext);
+
+	i = sizeof(data) / sizeof(uint32_t);
+	bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
+				       PROT_READ | PROT_WRITE);
+	memcpy(bb, &data, sizeof(data));
+
+	if (ext) {
+		fill_data_ext(&dext, ext);
+		memcpy(bb + i, &dext, sizeof(dext));
+		i += sizeof(dext) / sizeof(uint32_t);
+	}
+	bb[i++] = MI_BATCH_BUFFER_END;
+
+	if (blt->print_bb) {
+		igt_info("[BLOCK COPY]\n");
+		igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
+			 (long long) src_offset, (long long) dst_offset,
+			 (long long) bb_offset);
+
+		dump_bb_cmd(&data);
+		if (ext)
+			dump_bb_ext(&dext);
+	}
+
+	munmap(bb, blt->bb.size);
+
+	obj[0].offset = CANONICAL(dst_offset);
+	obj[1].offset = CANONICAL(src_offset);
+	obj[2].offset = CANONICAL(bb_offset);
+	obj[0].handle = blt->dst.handle;
+	obj[1].handle = blt->src.handle;
+	obj[2].handle = blt->bb.handle;
+	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	execbuf.buffer_count = 3;
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.rsvd1 = ctx ? ctx->id : 0;
+	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+	ret = __gem_execbuf(i915, &execbuf);
+
+	return ret;
+}
+
+static uint16_t __ccs_size(const struct blt_ctrl_surf_copy_data *surf)
+{
+	uint32_t src_size, dst_size;
+
+	src_size = surf->src.access_type == DIRECT_ACCESS ?
+				surf->src.size : surf->src.size / CCS_RATIO;
+
+	dst_size = surf->dst.access_type == DIRECT_ACCESS ?
+				surf->dst.size : surf->dst.size / CCS_RATIO;
+
+	igt_assert_f(src_size <= dst_size, "dst size must be >= src size for CCS copy\n");
+
+	return src_size;
+}
+
+struct gen12_ctrl_surf_copy_data {
+	struct {
+		uint32_t length:			BITRANGE(0, 7);
+		uint32_t size_of_ctrl_copy:		BITRANGE(8, 17);
+		uint32_t rsvd0:				BITRANGE(18, 19);
+		uint32_t dst_access_type:		BITRANGE(20, 20);
+		uint32_t src_access_type:		BITRANGE(21, 21);
+		uint32_t opcode:			BITRANGE(22, 28);
+		uint32_t client:			BITRANGE(29, 31);
+	} dw00;
+
+	struct {
+		uint32_t src_address_lo;
+	} dw01;
+
+	struct {
+		uint32_t src_address_hi:		BITRANGE(0, 24);
+		uint32_t src_mocs:			BITRANGE(25, 31);
+	} dw02;
+
+	struct {
+		uint32_t dst_address_lo;
+	} dw03;
+
+	struct {
+		uint32_t dst_address_hi:		BITRANGE(0, 24);
+		uint32_t dst_mocs:			BITRANGE(25, 31);
+	} dw04;
+};
+
+static void dump_bb_surf_ctrl_cmd(const struct gen12_ctrl_surf_copy_data *data)
+{
+	uint32_t *cmd = (uint32_t *) data;
+
+	igt_info("details:\n");
+	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, "
+		 "src/dst access type: <%d, %d>, size of ctrl copy: %u, length: %d>\n",
+		 cmd[0],
+		 data->dw00.client, data->dw00.opcode,
+		 data->dw00.src_access_type, data->dw00.dst_access_type,
+		 data->dw00.size_of_ctrl_copy, data->dw00.length);
+	igt_info(" dw01: [%08x] src offset lo (0x%x)\n",
+		 cmd[1], data->dw01.src_address_lo);
+	igt_info(" dw02: [%08x] src offset hi (0x%x), src mocs: %u\n",
+		 cmd[2], data->dw02.src_address_hi, data->dw02.src_mocs);
+	igt_info(" dw03: [%08x] dst offset lo (0x%x)\n",
+		 cmd[3], data->dw03.dst_address_lo);
+	igt_info(" dw04: [%08x] dst offset hi (0x%x), src mocs: %u\n",
+		 cmd[4], data->dw04.dst_address_hi, data->dw04.dst_mocs);
+}
+
+/**
+ * blt_ctrl_surf_copy:
+ * @i915: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @surf: blitter data for ctrl-surf-copy
+ *
+ * Function does ctrl-surf-copy blit between @src and @dst described in
+ * @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_ctrl_surf_copy(int i915,
+		       const intel_ctx_t *ctx,
+		       const struct intel_execution_engine2 *e,
+		       uint64_t ahnd,
+		       const struct blt_ctrl_surf_copy_data *surf)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct gen12_ctrl_surf_copy_data data = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	uint32_t *bb;
+	int i;
+
+	igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
+	igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
+
+	alignment = max_t(uint64_t, gem_detect_safe_alignment(i915), 1ull << 16);
+
+	data.dw00.client = 0x2;
+	data.dw00.opcode = 0x48;
+	data.dw00.src_access_type = surf->src.access_type;
+	data.dw00.dst_access_type = surf->dst.access_type;
+
+	/* Ensure dst has size capable to keep src ccs aux */
+	data.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
+	data.dw00.length = 0x3;
+
+	src_offset = get_offset(ahnd, surf->src.handle, surf->src.size,
+				alignment);
+	dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size,
+				alignment);
+	bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size,
+			       alignment);
+
+	data.dw01.src_address_lo = src_offset;
+	data.dw02.src_address_hi = src_offset >> 32;
+	data.dw02.src_mocs = surf->src.mocs;
+
+	data.dw03.dst_address_lo = dst_offset;
+	data.dw04.dst_address_hi = dst_offset >> 32;
+	data.dw04.dst_mocs = surf->dst.mocs;
+
+	i = sizeof(data) / sizeof(uint32_t);
+	bb = gem_mmap__device_coherent(i915, surf->bb.handle, 0, surf->bb.size,
+				       PROT_READ | PROT_WRITE);
+	memcpy(bb, &data, sizeof(data));
+	bb[i++] = MI_BATCH_BUFFER_END;
+
+	if (surf->print_bb) {
+		igt_info("BB [CTRL SURF]:\n");
+		igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
+			 (long long) src_offset, (long long) dst_offset,
+			 (long long) bb_offset);
+
+		dump_bb_surf_ctrl_cmd(&data);
+	}
+	munmap(bb, surf->bb.size);
+
+	obj[0].offset = CANONICAL(dst_offset);
+	obj[1].offset = CANONICAL(src_offset);
+	obj[2].offset = CANONICAL(bb_offset);
+	obj[0].handle = surf->dst.handle;
+	obj[1].handle = surf->src.handle;
+	obj[2].handle = surf->bb.handle;
+	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	execbuf.buffer_count = 3;
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+	execbuf.rsvd1 = ctx ? ctx->id : 0;
+	gem_execbuf(i915, &execbuf);
+	put_offset(ahnd, surf->dst.handle);
+	put_offset(ahnd, surf->src.handle);
+	put_offset(ahnd, surf->bb.handle);
+
+	return 0;
+}
+
+struct gen12_fast_copy_data {
+	struct {
+		uint32_t length:			BITRANGE(0, 7);
+		uint32_t rsvd1:				BITRANGE(8, 12);
+		uint32_t dst_tiling:			BITRANGE(13, 14);
+		uint32_t rsvd0:				BITRANGE(15, 19);
+		uint32_t src_tiling:			BITRANGE(20, 21);
+		uint32_t opcode:			BITRANGE(22, 28);
+		uint32_t client:			BITRANGE(29, 31);
+	} dw00;
+
+	struct {
+		uint32_t dst_pitch:			BITRANGE(0, 15);
+		uint32_t rsvd1:				BITRANGE(16, 23);
+		uint32_t color_depth:			BITRANGE(24, 26);
+		uint32_t rsvd0:				BITRANGE(27, 27);
+		uint32_t dst_memory:			BITRANGE(28, 28);
+		uint32_t src_memory:			BITRANGE(29, 29);
+		uint32_t dst_type_y:			BITRANGE(30, 30);
+		uint32_t src_type_y:			BITRANGE(31, 31);
+	} dw01;
+
+	struct {
+		int32_t dst_x1:				BITRANGE(0, 15);
+		int32_t dst_y1:				BITRANGE(16, 31);
+	} dw02;
+
+	struct {
+		int32_t dst_x2:				BITRANGE(0, 15);
+		int32_t dst_y2:				BITRANGE(16, 31);
+	} dw03;
+
+	struct {
+		uint32_t dst_address_lo;
+	} dw04;
+
+	struct {
+		uint32_t dst_address_hi;
+	} dw05;
+
+	struct {
+		int32_t src_x1:				BITRANGE(0, 15);
+		int32_t src_y1:				BITRANGE(16, 31);
+	} dw06;
+
+	struct {
+		uint32_t src_pitch:			BITRANGE(0, 15);
+		uint32_t rsvd0:				BITRANGE(16, 31);
+	} dw07;
+
+	struct {
+		uint32_t src_address_lo;
+	} dw08;
+
+	struct {
+		uint32_t src_address_hi;
+	} dw09;
+};
+
+static int __fast_tiling(enum blt_tiling tiling)
+{
+	switch (tiling) {
+	case T_LINEAR: return 0;
+	case T_XMAJOR: return 1;
+	case T_YMAJOR: return 2;
+	case T_TILE4:  return 2;
+	case T_TILE64: return 3;
+	}
+	return 0;
+}
+
+static int __fast_color_depth(enum blt_color_depth depth)
+{
+	switch (depth) {
+	case CD_8bit:   return 0;
+	case CD_16bit:  return 1;
+	case CD_32bit:  return 3;
+	case CD_64bit:  return 4;
+	case CD_96bit:
+		igt_assert_f(0, "Unsupported depth\n");
+		break;
+	case CD_128bit: return 5;
+	};
+	return 0;
+}
+
+static void dump_bb_fast_cmd(struct gen12_fast_copy_data *data)
+{
+	uint32_t *cmd = (uint32_t *) data;
+
+	igt_info("BB details:\n");
+	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, src tiling: %d, "
+		 "dst tiling: %d, length: %d>\n",
+		 cmd[0], data->dw00.client, data->dw00.opcode,
+		 data->dw00.src_tiling, data->dw00.dst_tiling, data->dw00.length);
+	igt_info(" dw01: [%08x] dst <pitch: %d, color depth: %d, dst memory: %d, "
+		 "src memory: %d,\n"
+		 "\t\t\tdst type tile: %d (0-legacy, 1-tile4),\n"
+		 "\t\t\tsrc type tile: %d (0-legacy, 1-tile4)>\n",
+		 cmd[1], data->dw01.dst_pitch, data->dw01.color_depth,
+		 data->dw01.dst_memory, data->dw01.src_memory,
+		 data->dw01.dst_type_y, data->dw01.src_type_y);
+	igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
+		 cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
+	igt_info(" dw03: [%08x]          <x2: %d, y2: %d>\n",
+		 cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
+	igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
+		 cmd[4], data->dw04.dst_address_lo);
+	igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
+		 cmd[5], data->dw05.dst_address_hi);
+	igt_info(" dw06: [%08x] src geom <x1: %d, y1: %d>\n",
+		 cmd[6], data->dw06.src_x1, data->dw06.src_y1);
+	igt_info(" dw07: [%08x] src <pitch: %d>\n",
+		 cmd[7], data->dw07.src_pitch);
+	igt_info(" dw08: [%08x] src offset lo (0x%x)\n",
+		 cmd[8], data->dw08.src_address_lo);
+	igt_info(" dw09: [%08x] src offset hi (0x%x)\n",
+		 cmd[9], data->dw09.src_address_hi);
+}
+
+/**
+ * blt_fast_copy:
+ * @i915: drm fd
+ * @ctx: intel_ctx_t context
+ * @e: blitter engine for @ctx
+ * @ahnd: allocator handle
+ * @blt: blitter data for fast-copy (same as for block-copy but doesn't use
+ * compression fields).
+ *
+ * Function does fast blit between @src and @dst described in @blt object.
+ *
+ * Returns:
+ * execbuffer status.
+ */
+int blt_fast_copy(int i915,
+		  const intel_ctx_t *ctx,
+		  const struct intel_execution_engine2 *e,
+		  uint64_t ahnd,
+		  const struct blt_copy_data *blt)
+{
+	struct drm_i915_gem_execbuffer2 execbuf = {};
+	struct drm_i915_gem_exec_object2 obj[3] = {};
+	struct gen12_fast_copy_data data = {};
+	uint64_t dst_offset, src_offset, bb_offset, alignment;
+	uint32_t *bb;
+	int i, ret;
+
+	alignment = gem_detect_safe_alignment(i915);
+
+	data.dw00.client = 0x2;
+	data.dw00.opcode = 0x42;
+	data.dw00.dst_tiling = __fast_tiling(blt->dst.tiling);
+	data.dw00.src_tiling = __fast_tiling(blt->src.tiling);
+	data.dw00.length = 8;
+
+	data.dw01.dst_pitch = blt->dst.pitch;
+	data.dw01.color_depth = __fast_color_depth(blt->color_depth);
+	data.dw01.dst_memory = __memory_type(blt->dst.region);
+	data.dw01.src_memory = __memory_type(blt->src.region);
+	data.dw01.dst_type_y = blt->dst.tiling == T_TILE4 ? 1 : 0;
+	data.dw01.src_type_y = blt->src.tiling == T_TILE4 ? 1 : 0;
+
+	data.dw02.dst_x1 = blt->dst.x1;
+	data.dw02.dst_y1 = blt->dst.y1;
+
+	data.dw03.dst_x2 = blt->dst.x2;
+	data.dw03.dst_y2 = blt->dst.y2;
+
+	src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+	dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+	bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+	data.dw04.dst_address_lo = dst_offset;
+	data.dw05.dst_address_hi = dst_offset >> 32;
+
+	data.dw06.src_x1 = blt->src.x1;
+	data.dw06.src_y1 = blt->src.y1;
+
+	data.dw07.src_pitch = blt->src.pitch;
+
+	data.dw08.src_address_lo = src_offset;
+	data.dw09.src_address_hi = src_offset >> 32;
+
+	i = sizeof(data) / sizeof(uint32_t);
+	bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
+				       PROT_READ | PROT_WRITE);
+
+	memcpy(bb, &data, sizeof(data));
+	bb[i++] = MI_BATCH_BUFFER_END;
+
+	if (blt->print_bb) {
+		igt_info("BB [FAST COPY]\n");
+		igt_info("blit [src offset: %llx, dst offset: %llx\n",
+			 (long long) src_offset, (long long) dst_offset);
+		dump_bb_fast_cmd(&data);
+	}
+
+	munmap(bb, blt->bb.size);
+
+	obj[0].offset = CANONICAL(dst_offset);
+	obj[1].offset = CANONICAL(src_offset);
+	obj[2].offset = CANONICAL(bb_offset);
+	obj[0].handle = blt->dst.handle;
+	obj[1].handle = blt->src.handle;
+	obj[2].handle = blt->bb.handle;
+	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
+		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+	execbuf.buffer_count = 3;
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.rsvd1 = ctx ? ctx->id : 0;
+	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+	ret = __gem_execbuf(i915, &execbuf);
+	put_offset(ahnd, blt->dst.handle);
+	put_offset(ahnd, blt->src.handle);
+	put_offset(ahnd, blt->bb.handle);
+
+	return ret;
+}
+
+/**
+ * blt_surface_fill_rect:
+ * @i915: drm fd
+ * @obj: blitter copy object (@blt_copy_object) to fill with gradient pattern
+ * @width: width
+ * @height: height
+ *
+ * Function fills surface @width x @height * 24bpp with color gradient
+ * (internally uses ARGB where A == 0xff, see Cairo docs).
+ */
+void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
+			   uint32_t width, uint32_t height)
+{
+	cairo_surface_t *surface;
+	cairo_pattern_t *pat;
+	cairo_t *cr;
+	void *map = obj->ptr;
+
+	if (!map)
+		map = gem_mmap__device_coherent(i915, obj->handle, 0,
+						obj->size, PROT_READ | PROT_WRITE);
+
+	surface = cairo_image_surface_create_for_data(map,
+						      CAIRO_FORMAT_RGB24,
+						      width, height,
+						      obj->pitch);
+
+	cr = cairo_create(surface);
+
+	cairo_rectangle(cr, 0, 0, width, height);
+	cairo_clip(cr);
+
+	pat = cairo_pattern_create_mesh();
+	cairo_mesh_pattern_begin_patch(pat);
+	cairo_mesh_pattern_move_to(pat, 0, 0);
+	cairo_mesh_pattern_line_to(pat, width, 0);
+	cairo_mesh_pattern_line_to(pat, width, height);
+	cairo_mesh_pattern_line_to(pat, 0, height);
+	cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
+	cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
+	cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
+	cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
+	cairo_mesh_pattern_end_patch(pat);
+
+	cairo_rectangle(cr, 0, 0, width, height);
+	cairo_set_source(cr, pat);
+	cairo_fill(cr);
+	cairo_pattern_destroy(pat);
+
+	cairo_destroy(cr);
+
+	cairo_surface_destroy(surface);
+	if (!obj->ptr)
+		munmap(map, obj->size);
+}
+
+/**
+ * blt_surface_info:
+ * @info: information header
+ * @obj: blitter copy object (@blt_copy_object) to print surface info
+ */
+void blt_surface_info(const char *info, const struct blt_copy_object *obj)
+{
+	igt_info("[%s]\n", info);
+	igt_info("surface <handle: %u, size: %llx, region: %x, mocs: %x>\n",
+		 obj->handle, (long long) obj->size, obj->region, obj->mocs);
+	igt_info("        <tiling: %s, compression: %u, compression type: %d>\n",
+		 blt_tiling_name(obj->tiling), obj->compression, obj->compression_type);
+	igt_info("        <pitch: %u, offset [x: %u, y: %u] geom [<%d,%d> <%d,%d>]>\n",
+		 obj->pitch, obj->x_offset, obj->y_offset,
+		 obj->x1, obj->y1, obj->x2, obj->y2);
+}
+
+/**
+ * blt_surface_to_png:
+ * @i915: drm fd
+ * @run_id: prefix id to allow grouping files stored from single run
+ * @fileid: file identifier
+ * @obj: blitter copy object (@blt_copy_object) to save to png
+ * @width: width
+ * @height: height
+ *
+ * Function save surface to png file. Assumes ARGB format where A == 0xff.
+ */
+void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
+			const struct blt_copy_object *obj,
+			uint32_t width, uint32_t height)
+{
+	cairo_surface_t *surface;
+	cairo_status_t ret;
+	uint8_t *map = (uint8_t *) obj->ptr;
+	int format;
+	int stride = obj->tiling ? obj->pitch * 4 : obj->pitch;
+	char filename[FILENAME_MAX];
+
+	snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png",
+		 run_id, fileid, blt_tiling_name(obj->tiling), width, height,
+		 obj->compression ? "compressed" : "uncompressed");
+
+	if (!map)
+		map = gem_mmap__device_coherent(i915, obj->handle, 0,
+						obj->size, PROT_READ);
+	format = CAIRO_FORMAT_RGB24;
+	surface = cairo_image_surface_create_for_data(map,
+						      format, width, height,
+						      stride);
+	ret = cairo_surface_write_to_png(surface, filename);
+	if (ret)
+		igt_info("Cairo ret: %d (%s)\n", ret, cairo_status_to_string(ret));
+	igt_assert(ret == CAIRO_STATUS_SUCCESS);
+	cairo_surface_destroy(surface);
+
+	if (!obj->ptr)
+		munmap(map, obj->size);
+}
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
new file mode 100644
index 0000000000..e0e8b52bc2
--- /dev/null
+++ b/lib/i915/i915_blt.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/**
+ * SECTION:i915_blt
+ * @short_description: i915 blitter library
+ * @title: Blitter library
+ * @include: i915_blt.h
+ *
+ * # Introduction
+ *
+ * Gen12+ blitter commands like XY_BLOCK_COPY_BLT are quite long
+ * and if we would like to provide all arguments to function,
+ * list would be long, unreadable and error prone to invalid argument placement.
+ * Providing objects (structs) seems more reasonable and opens some more
+ * opportunities to share some object data across different blitter commands.
+ *
+ * Blitter library supports no-reloc (softpin) mode only (apart of TGL
+ * there's no relocations enabled) thus ahnd is mandatory. Providing NULL ctx
+ * means we use default context with I915_EXEC_BLT as an execution engine.
+ *
+ * Library introduces tiling enum which distinguishes tiling formats regardless
+ * legacy I915_TILING_... definitions. This allows to control fully what tilings
+ * are handled by command and skip/assert ones which are not supported.
+ *
+ * # Supported commands
+ *
+ * - XY_BLOCK_COPY_BLT - (block-copy) TGL/DG1 + DG2+ (ext version)
+ * - XY_FAST_COPY_BLT - (fast-copy)
+ * - XY_CTRL_SURF_COPY_BLT - (ctrl-surf-copy) DG2+
+ *
+ * # Usage details
+ *
+ * For block-copy and fast-copy @blt_copy_object struct is used to collect
+ * data about source and destination objects. It contains handle, region,
+ * size, etc...  which are using for blits. Some fields are not used for
+ * fast-copy copy (like compression) and command which use this exclusively
+ * is annotated in the comment.
+ *
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+
+#define CCS_RATIO 256
+
+enum blt_color_depth {
+	CD_8bit,
+	CD_16bit,
+	CD_32bit,
+	CD_64bit,
+	CD_96bit,
+	CD_128bit,
+};
+
+enum blt_tiling {
+	T_LINEAR,
+	T_XMAJOR,
+	T_YMAJOR,
+	T_TILE4,
+	T_TILE64,
+};
+
+enum blt_compression {
+	COMPRESSION_DISABLED,
+	COMPRESSION_ENABLED,
+};
+
+enum blt_compression_type {
+	COMPRESSION_TYPE_3D,
+	COMPRESSION_TYPE_MEDIA,
+};
+
+/* BC - block-copy */
+struct blt_copy_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs;
+	enum blt_tiling tiling;
+	enum blt_compression compression;  /* BC only */
+	enum blt_compression_type compression_type; /* BC only */
+	uint32_t pitch;
+	uint16_t x_offset, y_offset;
+	int16_t x1, y1, x2, y2;
+
+	/* mapping or null */
+	uint32_t *ptr;
+};
+
+struct blt_copy_batch {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+};
+
+/* Common for block-copy and fast-copy */
+struct blt_copy_data {
+	int i915;
+	struct blt_copy_object src;
+	struct blt_copy_object dst;
+	struct blt_copy_batch bb;
+	enum blt_color_depth color_depth;
+
+	/* debug stuff */
+	bool print_bb;
+};
+
+enum blt_surface_type {
+	SURFACE_TYPE_1D,
+	SURFACE_TYPE_2D,
+	SURFACE_TYPE_3D,
+	SURFACE_TYPE_CUBE,
+};
+
+struct blt_block_copy_object_ext {
+	uint8_t compression_format;
+	bool clear_value_enable;
+	uint64_t clear_address;
+	uint16_t surface_width;
+	uint16_t surface_height;
+	enum blt_surface_type surface_type;
+	uint16_t surface_qpitch;
+	uint16_t surface_depth;
+	uint8_t lod;
+	uint8_t horizontal_align;
+	uint8_t vertical_align;
+	uint8_t mip_tail_start_lod;
+	bool depth_stencil_resource;
+	uint16_t array_index;
+};
+
+struct blt_block_copy_data_ext {
+	struct blt_block_copy_object_ext src;
+	struct blt_block_copy_object_ext dst;
+};
+
+enum blt_access_type {
+	INDIRECT_ACCESS,
+	DIRECT_ACCESS,
+};
+
+struct blt_ctrl_surf_copy_object {
+	uint32_t handle;
+	uint32_t region;
+	uint64_t size;
+	uint8_t mocs;
+	enum blt_access_type access_type;
+};
+
+struct blt_ctrl_surf_copy_data {
+	int i915;
+	struct blt_ctrl_surf_copy_object src;
+	struct blt_ctrl_surf_copy_object dst;
+	struct blt_copy_batch bb;
+
+	/* debug stuff */
+	bool print_bb;
+};
+
+bool blt_supports_compression(int i915);
+bool blt_supports_tiling(int i915, enum blt_tiling tiling);
+const char *blt_tiling_name(enum blt_tiling tiling);
+
+int blt_block_copy(int i915,
+		   const intel_ctx_t *ctx,
+		   const struct intel_execution_engine2 *e,
+		   uint64_t ahnd,
+		   const struct blt_copy_data *blt,
+		   const struct blt_block_copy_data_ext *ext);
+
+int blt_ctrl_surf_copy(int i915,
+		       const intel_ctx_t *ctx,
+		       const struct intel_execution_engine2 *e,
+		       uint64_t ahnd,
+		       const struct blt_ctrl_surf_copy_data *surf);
+
+int blt_fast_copy(int i915,
+		  const intel_ctx_t *ctx,
+		  const struct intel_execution_engine2 *e,
+		  uint64_t ahnd,
+		  const struct blt_copy_data *blt);
+
+void blt_surface_info(const char *info,
+		      const struct blt_copy_object *obj);
+void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
+			   uint32_t width, uint32_t height);
+void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
+		    const struct blt_copy_object *obj,
+		    uint32_t width, uint32_t height);
diff --git a/lib/meson.build b/lib/meson.build
index a5fe91dc99..6fc1958604 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -12,6 +12,7 @@ lib_sources = [
 	'i915/gem_vm.c',
 	'i915/intel_memory_region.c',
 	'i915/intel_mocs.c',
+	'i915/i915_blt.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
-- 
2.32.0

[igt-dev] [PATCH i-g-t 6/6] tests/gem_ccs: Verify uncompressed and compressed blits

[Zbigniew Kempczyński]

DG2 and above supports flat-ccs what means object compression lays in
dedicated part or memory and is directly correlated with object location
in physical memory. As no mapping is possible from CPU side to this area
dedicated blitter command (XY_CTRL_SURF_COPY_BLT) was created to copy
from/to ccs data.

Test exercises scenarios:
1. block-copy without compression (TGL/DG1)
2. block-copy with flat-ccs compression (DG2+) + inplace decompression
3. ctrl-surf-copy which verifies copying ccs data to/from flat-ccs area

v2: set mip tail lod to 0xf to avoid overlap with lod
v3: address review comments (Kamil) + setting uc_mocs (Ayaz)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/i915/gem_ccs.c | 487 +++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build    |   1 +
 2 files changed, 488 insertions(+)
 create mode 100644 tests/i915/gem_ccs.c

diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
new file mode 100644
index 0000000000..f4d06f201d
--- /dev/null
+++ b/tests/i915/gem_ccs.c
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+#include <malloc.h>
+#include "drm.h"
+#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "lib/intel_chipset.h"
+#include "i915/i915_blt.h"
+#include "i915/intel_mocs.h"
+
+IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression");
+
+static struct param {
+	int compression_format;
+	int tiling;
+	bool write_png;
+	bool print_bb;
+	bool print_surface_info;
+	int width;
+	int height;
+} param = {
+	.compression_format = 0,
+	.tiling = -1,
+	.write_png = false,
+	.print_bb = false,
+	.print_surface_info = false,
+	.width = 512,
+	.height = 512,
+};
+
+struct test_config {
+	bool compression;
+	bool inplace;
+	bool surfcopy;
+};
+
+static void set_object(struct blt_copy_object *obj,
+		       uint32_t handle, uint64_t size, uint32_t region,
+		       uint8_t mocs, enum blt_tiling tiling,
+		       enum blt_compression compression,
+		       enum blt_compression_type compression_type)
+{
+	obj->handle = handle;
+	obj->size = size;
+	obj->region = region;
+	obj->mocs = mocs;
+	obj->tiling = tiling;
+	obj->compression = compression;
+	obj->compression_type = compression_type;
+}
+
+static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
+		     int16_t x1, int16_t y1, int16_t x2, int16_t y2,
+		     uint16_t x_offset, uint16_t y_offset)
+{
+	obj->pitch = pitch;
+	obj->x1 = x1;
+	obj->y1 = y1;
+	obj->x2 = x2;
+	obj->y2 = y2;
+	obj->x_offset = x_offset;
+	obj->y_offset = y_offset;
+}
+
+static void set_batch(struct blt_copy_batch *batch,
+		      uint32_t handle, uint64_t size, uint32_t region)
+{
+	batch->handle = handle;
+	batch->size = size;
+	batch->region = region;
+}
+
+static void set_object_ext(struct blt_block_copy_object_ext *obj,
+			   uint8_t compression_format,
+			   uint16_t surface_width, uint16_t surface_height,
+			   enum blt_surface_type surface_type)
+{
+	obj->compression_format = compression_format;
+	obj->surface_width = surface_width;
+	obj->surface_height = surface_height;
+	obj->surface_type = surface_type;
+
+	/* Ensure mip tail won't overlap lod */
+	obj->mip_tail_start_lod = 0xf;
+}
+
+static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
+			    uint32_t handle, uint32_t region, uint64_t size,
+			    uint8_t mocs, enum blt_access_type access_type)
+{
+	obj->handle = handle;
+	obj->region = region;
+	obj->size = size;
+	obj->mocs = mocs;
+	obj->access_type = access_type;
+}
+
+static struct blt_copy_object *
+create_object(int i915, uint32_t region,
+	      uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
+	      enum blt_tiling tiling,
+	      enum blt_compression compression,
+	      enum blt_compression_type compression_type,
+	      bool create_mapping)
+{
+	struct blt_copy_object *obj;
+	uint64_t size = width * height * bpp / 8;
+	uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
+	uint32_t handle;
+
+	obj = calloc(1, sizeof(*obj));
+
+	obj->size = size;
+	igt_assert(__gem_create_in_memory_regions(i915, &handle,
+						  &size, region) == 0);
+
+	set_object(obj, handle, size, region, mocs, tiling,
+		   compression, compression_type);
+	set_geom(obj, stride, 0, 0, width, height, 0, 0);
+
+	if (create_mapping)
+		obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
+						     PROT_READ | PROT_WRITE);
+
+	return obj;
+}
+
+static void destroy_object(int i915, struct blt_copy_object *obj)
+{
+	if (obj->ptr)
+		munmap(obj->ptr, obj->size);
+
+	gem_close(i915, obj->handle);
+}
+
+static void set_blt_object(struct blt_copy_object *obj,
+			   const struct blt_copy_object *orig)
+{
+	memcpy(obj, orig, sizeof(*obj));
+}
+
+#define PRINT_SURFACE_INFO(name, obj) do { \
+	if (param.print_surface_info) \
+		blt_surface_info((name), (obj)); } while (0)
+
+#define WRITE_PNG(fd, id, name, obj, w, h) do { \
+	if (param.write_png) \
+		blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
+
+static void surf_copy(int i915,
+		      const intel_ctx_t *ctx,
+		      const struct intel_execution_engine2 *e,
+		      uint64_t ahnd,
+		      const struct blt_copy_object *src,
+		      const struct blt_copy_object *mid,
+		      const struct blt_copy_object *dst,
+		      int run_id)
+{
+	struct blt_copy_data blt = {};
+	struct blt_block_copy_data_ext ext = {};
+	struct blt_ctrl_surf_copy_data surf = {};
+	uint32_t bb, ccs, *ccsmap;
+	uint64_t bb_size = 4096;
+	uint64_t ccssize = mid->size / CCS_RATIO;
+	uint32_t *ccscopy;
+	uint8_t uc_mocs = intel_get_uc_mocs(i915);
+	int result;
+
+	igt_assert(mid->compression);
+	ccscopy = (uint32_t *) malloc(ccssize);
+	bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	ccs = gem_create(i915, ccssize);
+
+	surf.i915 = i915;
+	surf.print_bb = param.print_bb;
+	set_surf_object(&surf.src, mid->handle, mid->region, mid->size,
+			uc_mocs, INDIRECT_ACCESS);
+	set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
+			uc_mocs, DIRECT_ACCESS);
+	set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
+	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
+	gem_sync(i915, surf.dst.handle);
+
+	ccsmap = gem_mmap__device_coherent(i915, ccs, 0, surf.dst.size,
+					   PROT_READ | PROT_WRITE);
+	memcpy(ccscopy, ccsmap, ccssize);
+
+	/* corrupt ccs */
+	for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
+		ccsmap[i] = i;
+	set_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
+			uc_mocs, DIRECT_ACCESS);
+	set_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
+			uc_mocs, INDIRECT_ACCESS);
+	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
+
+	memset(&blt, 0, sizeof(blt));
+	blt.color_depth = CD_32bit;
+	blt.print_bb = param.print_bb;
+	set_blt_object(&blt.src, mid);
+	set_blt_object(&blt.dst, dst);
+	set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
+	set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
+	bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
+	set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
+	blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
+	gem_sync(i915, blt.dst.handle);
+	WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
+	result = memcmp(src->ptr, dst->ptr, src->size);
+	igt_assert(result != 0);
+
+	/* retrieve back ccs */
+	memcpy(ccsmap, ccscopy, ccssize);
+	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
+
+	blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
+	gem_sync(i915, blt.dst.handle);
+	WRITE_PNG(i915, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
+	result = memcmp(src->ptr, dst->ptr, src->size);
+	igt_assert(result == 0);
+
+	munmap(ccsmap, ccssize);
+	gem_close(i915, ccs);
+}
+
+static void block_copy(int i915,
+		       const intel_ctx_t *ctx,
+		       const struct intel_execution_engine2 *e,
+		       uint32_t region1, uint32_t region2,
+		       enum blt_tiling mid_tiling, bool compression,
+		       bool inplace,
+		       bool surfcopy)
+{
+	struct blt_copy_data blt = {};
+	struct blt_block_copy_data_ext ext = {}, *pext = &ext;
+	struct blt_copy_object *src, *mid, *dst;
+	const uint32_t bpp = 32;
+	uint64_t bb_size = 4096;
+	uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
+						  INTEL_ALLOCATOR_SIMPLE,
+						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+	uint32_t run_id = mid_tiling;
+	uint32_t mid_region = region2, bb;
+	uint32_t width = param.width, height = param.height;
+	enum blt_compression mid_compression = compression;
+	int mid_compression_format = param.compression_format;
+	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
+	uint8_t uc_mocs = intel_get_uc_mocs(i915);
+	int result;
+
+	igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
+
+	if (!blt_supports_compression(i915))
+		pext = NULL;
+
+	src = create_object(i915, region1, width, height, bpp, uc_mocs,
+			    T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+	mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
+			    mid_tiling, mid_compression, comp_type, true);
+	dst = create_object(i915, region1, width, height, bpp, uc_mocs,
+			    T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+	igt_assert(src->size == dst->size);
+	PRINT_SURFACE_INFO("src", src);
+	PRINT_SURFACE_INFO("mid", mid);
+	PRINT_SURFACE_INFO("dst", dst);
+
+	blt_surface_fill_rect(i915, src, width, height);
+	WRITE_PNG(i915, run_id, "src", src, width, height);
+
+	memset(&blt, 0, sizeof(blt));
+	blt.color_depth = CD_32bit;
+	blt.print_bb = param.print_bb;
+	set_blt_object(&blt.src, src);
+	set_blt_object(&blt.dst, mid);
+	set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
+	set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
+	set_batch(&blt.bb, bb, bb_size, region1);
+
+	blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
+	gem_sync(i915, mid->handle);
+
+	/* We expect mid != src if there's compression */
+	if (mid->compression)
+		igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0);
+
+	WRITE_PNG(i915, run_id, "src", &blt.src, width, height);
+	WRITE_PNG(i915, run_id, "mid", &blt.dst, width, height);
+
+	if (surfcopy && pext)
+		surf_copy(i915, ctx, e, ahnd, src, mid, dst, run_id);
+
+	memset(&blt, 0, sizeof(blt));
+	blt.color_depth = CD_32bit;
+	blt.print_bb = param.print_bb;
+	set_blt_object(&blt.src, mid);
+	set_blt_object(&blt.dst, dst);
+	set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
+	set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
+	if (inplace) {
+		set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
+			   T_LINEAR, COMPRESSION_DISABLED, comp_type);
+		blt.dst.ptr = mid->ptr;
+	}
+
+	set_batch(&blt.bb, bb, bb_size, region1);
+	blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
+	gem_sync(i915, blt.dst.handle);
+	WRITE_PNG(i915, run_id, "dst", &blt.dst, width, height);
+
+	result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+	destroy_object(i915, src);
+	destroy_object(i915, mid);
+	destroy_object(i915, dst);
+	gem_close(i915, bb);
+	put_ahnd(ahnd);
+
+	igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+static void block_copy_test(int i915,
+			    const struct test_config *config,
+			    const intel_ctx_t *ctx,
+			    struct igt_collection *set)
+{
+	struct igt_collection *regions;
+	const struct intel_execution_engine2 *e;
+
+	if (config->compression && !blt_supports_compression(i915))
+		return;
+
+	if (config->inplace && !config->compression)
+		return;
+
+	for (int tiling = T_LINEAR; tiling <= T_TILE64; tiling++) {
+		if (!blt_supports_tiling(i915, tiling) ||
+		    (param.tiling >= 0 && param.tiling != tiling))
+			continue;
+
+		for_each_ctx_engine(i915, ctx, e) {
+			if (!gem_engine_can_block_copy(i915, e))
+				continue;
+
+			for_each_variation_r(regions, 2, set) {
+				uint32_t region1, region2;
+				char *regtxt;
+
+				region1 = igt_collection_get_value(regions, 0);
+				region2 = igt_collection_get_value(regions, 1);
+
+				/* Compressed surface must be in device memory */
+				if (config->compression && !IS_DEVICE_MEMORY_REGION(region2))
+					continue;
+
+				regtxt = memregion_dynamic_subtest_name(regions);
+				igt_dynamic_f("%s-%s-compfmt%d-%s",
+					      blt_tiling_name(tiling),
+					      config->compression ?
+						      "compressed" : "uncompressed",
+					      param.compression_format, regtxt) {
+					block_copy(i915, ctx, e,
+						   region1, region2,
+						   tiling,
+						   config->compression,
+						   config->inplace,
+						   config->surfcopy);
+				}
+				free(regtxt);
+			}
+		}
+	}
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+	switch (opt) {
+	case 'b':
+		param.print_bb = true;
+		igt_debug("Print bb: %d\n", param.print_bb);
+		break;
+	case 'f':
+		param.compression_format = atoi(optarg);
+		igt_debug("Compression format: %d\n", param.compression_format);
+		igt_assert((param.compression_format & ~0x1f) == 0);
+		break;
+	case 'p':
+		param.write_png = true;
+		igt_debug("Write png: %d\n", param.write_png);
+		break;
+	case 's':
+		param.print_surface_info = true;
+		igt_debug("Print surface info: %d\n", param.print_surface_info);
+		break;
+	case 't':
+		param.tiling = atoi(optarg);
+		igt_debug("Tiling: %d\n", param.tiling);
+		break;
+	case 'W':
+		param.width = atoi(optarg);
+		igt_debug("Width: %d\n", param.width);
+		break;
+	case 'H':
+		param.height = atoi(optarg);
+		igt_debug("Height: %d\n", param.height);
+		break;
+	default:
+		return IGT_OPT_HANDLER_ERROR;
+	}
+
+	return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+	"  -b\tPrint bb\n"
+	"  -f\tCompression format (0-31)"
+	"  -p\tWrite PNG\n"
+	"  -s\tPrint surface info\n"
+	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
+	"  -W\tWidth (default 512)\n"
+	"  -H\tHeight (default 512)"
+	;
+
+igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
+{
+	struct drm_i915_query_memory_regions *query_info;
+	struct igt_collection *set;
+	const intel_ctx_t *ctx;
+	int i915;
+	igt_hang_t hang;
+
+	igt_fixture {
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(i915);
+		igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
+
+		query_info = gem_get_query_memory_regions(i915);
+		igt_require(query_info);
+
+		set = get_memory_region_set(query_info,
+					    I915_SYSTEM_MEMORY,
+					    I915_DEVICE_MEMORY);
+		ctx = intel_ctx_create_all_physical(i915);
+		hang = igt_allow_hang(i915, ctx->id, 0);
+	}
+
+	igt_describe("Check block-copy uncompressed blit");
+	igt_subtest_with_dynamic("block-copy-uncompressed") {
+		struct test_config config = {};
+
+		block_copy_test(i915, &config, ctx, set);
+	}
+
+	igt_describe("Check block-copy flatccs compressed blit");
+	igt_subtest_with_dynamic("block-copy-compressed") {
+		struct test_config config = { .compression = true };
+
+		block_copy_test(i915, &config, ctx, set);
+	}
+
+	igt_describe("Check block-copy flatccs inplace decompression blit");
+	igt_subtest_with_dynamic("block-copy-inplace") {
+		struct test_config config = { .compression = true,
+					      .inplace = true };
+
+		block_copy_test(i915, &config, ctx, set);
+	}
+
+	igt_describe("Check flatccs data can be copied from/to surface");
+	igt_subtest_with_dynamic("ctrl-surf-copy") {
+		struct test_config config = { .compression = true,
+					      .surfcopy = true };
+
+		block_copy_test(i915, &config, ctx, set);
+	}
+
+	igt_fixture {
+		igt_disallow_hang(i915, hang);
+		close(i915);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 3dbba7a1b7..3af4576f4a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -109,6 +109,7 @@ i915_progs = [
 	'gem_blits',
 	'gem_busy',
 	'gem_caching',
+	'gem_ccs',
 	'gem_close',
 	'gem_close_race',
 	'gem_concurrent_blit',
-- 
2.32.0

[igt-dev] ✓ Fi.CI.BAT: success for Add i915 blt library + gem_ccs test (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 14082 bytes --]

== Series Details ==

Series: Add i915 blt library + gem_ccs test (rev7)
URL   : https://patchwork.freedesktop.org/series/99925/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11347 -> IGTPW_6769
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html

Participating hosts (41 -> 43)
------------------------------

  Additional (4): fi-bxt-dsi bat-dg2-9 bat-dg1-6 bat-adlp-4 
  Missing    (2): fi-bsw-cyan shard-tglu 

Known issues
------------

  Here are the changes found in IGTPW_6769 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - bat-dg1-6:          NOTRUN -> [SKIP][1] ([i915#4086])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@gem_exec_gttfill@basic.html

  * igt@gem_huc_copy@huc-copy:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - bat-adlp-4:         NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-bxt-dsi/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-dg1-6:          NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@gem_mmap@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-dg1-6:          NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-adlp-4:         NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@gem_tiled_pread_basic.html
    - bat-dg1-6:          NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - bat-dg1-6:          NOTRUN -> [SKIP][9] ([i915#1155])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-6:          NOTRUN -> [FAIL][10] ([i915#4032])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@workarounds:
    - bat-adlp-4:         NOTRUN -> [DMESG-FAIL][11] ([i915#5020])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-dg1-6:          NOTRUN -> [SKIP][12] ([i915#4212]) +7 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-6:          NOTRUN -> [SKIP][13] ([i915#4215])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
    - bat-adlp-4:         NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - bat-dg1-6:          NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-dg1-6:          NOTRUN -> [SKIP][17] ([i915#4103] / [i915#4213]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adlp-4:         NOTRUN -> [SKIP][18] ([i915#4103]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - bat-adlp-4:         NOTRUN -> [DMESG-WARN][19] ([i915#3576]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][20] ([fdo#109271]) +31 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg1-6:          NOTRUN -> [SKIP][21] ([fdo#109285])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
    - bat-adlp-4:         NOTRUN -> [SKIP][22] ([fdo#109285])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#533])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-dg1-6:          NOTRUN -> [SKIP][24] ([i915#1072] / [i915#4078]) +3 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adlp-4:         NOTRUN -> [SKIP][25] ([i915#3555])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg1-6:          NOTRUN -> [SKIP][26] ([i915#3555])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adlp-4:         NOTRUN -> [SKIP][27] ([i915#3291] / [i915#3708]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg1-6:          NOTRUN -> [SKIP][28] ([i915#3708] / [i915#4077]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
    - bat-dg1-6:          NOTRUN -> [SKIP][29] ([i915#3708] / [i915#4873])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@prime_vgem@basic-userptr.html
    - bat-adlp-4:         NOTRUN -> [SKIP][30] ([i915#3301] / [i915#3708])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-4/igt@prime_vgem@basic-userptr.html

  * igt@prime_vgem@basic-write:
    - bat-dg1-6:          NOTRUN -> [SKIP][31] ([i915#3708]) +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-6/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - {fi-rkl-11600}:     [INCOMPLETE][32] ([i915#5127]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@active:
    - {bat-rpls-2}:       [DMESG-WARN][34] ([i915#4391]) -> [PASS][35] +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/bat-rpls-2/igt@i915_selftest@live@active.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-rpls-2/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@workarounds:
    - {bat-adlp-6}:       [DMESG-WARN][36] ([i915#5068]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/bat-adlp-6/igt@i915_selftest@live@workarounds.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_busy@basic@flip:
    - {bat-adlp-6}:       [DMESG-WARN][38] ([i915#3576]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/bat-adlp-6/igt@kms_busy@basic@flip.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-adlp-6/igt@kms_busy@basic@flip.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
    - fi-cfl-8109u:       [DMESG-WARN][40] ([i915#295]) -> [PASS][41] +11 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-kbl-guc:         [FAIL][42] ([i915#3049]) -> [SKIP][43] ([fdo#109271])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          [DMESG-FAIL][44] ([i915#4494] / [i915#4957]) -> [DMESG-FAIL][45] ([i915#4957])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/bat-dg1-5/igt@i915_selftest@live@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4086]: https://gitlab.freedesktop.org/drm/intel/issues/4086
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5020]: https://gitlab.freedesktop.org/drm/intel/issues/5020
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
  [i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192
  [i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
  [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
  [i915#5276]: https://gitlab.freedesktop.org/drm/intel/issues/5276
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6373 -> IGTPW_6769

  CI-20190529: 20190529
  CI_DRM_11347: 99965da17d037dcf0bf0c2ebb34804217ab9c018 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6769: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html
  IGT_6373: 82306f1903c0fee8371f43a156d8b63163ca61c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@api_intel_allocator@gem-pool
+igt@gem_ccs@block-copy-compressed
+igt@gem_ccs@block-copy-inplace
+igt@gem_ccs@block-copy-uncompressed
+igt@gem_ccs@ctrl-surf-copy

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html

[-- Attachment #2: Type: text/html, Size: 15961 bytes --]

[igt-dev] ✗ Fi.CI.IGT: failure for Add i915 blt library + gem_ccs test (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30260 bytes --]

== Series Details ==

Series: Add i915 blt library + gem_ccs test (rev7)
URL   : https://patchwork.freedesktop.org/series/99925/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11347_full -> IGTPW_6769_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6769_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6769_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html

Participating hosts (13 -> 7)
------------------------------

  Missing    (6): pig-kbl-iris shard-tglu pig-glk-j5005 pig-skl-6260u shard-rkl shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6769_full:

### IGT changes ###

#### Possible regressions ####

  * igt@api_intel_allocator@fork-simple-stress:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@api_intel_allocator@fork-simple-stress.html

  * {igt@gem_ccs@block-copy-compressed} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb3/igt@gem_ccs@block-copy-compressed.html

  * {igt@gem_ccs@block-copy-uncompressed} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][3] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb8/igt@gem_ccs@block-copy-uncompressed.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_setmode@basic@pipe-b-vga-1}:
    - shard-snb:          [FAIL][4] ([i915#31]) -> [FAIL][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-snb7/igt@kms_setmode@basic@pipe-b-vga-1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-snb6/igt@kms_setmode@basic@pipe-b-vga-1.html

  
New tests
---------

  New tests have been introduced between CI_DRM_11347_full and IGTPW_6769_full:

### New IGT tests (5) ###

  * igt@api_intel_allocator@gem-pool:
    - Statuses : 6 pass(s)
    - Exec time: [0.00, 0.02] s

  * igt@gem_ccs@block-copy-compressed:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@block-copy-inplace:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@block-copy-uncompressed:
    - Statuses : 4 skip(s)
    - Exec time: [0.0] s

  * igt@gem_ccs@ctrl-surf-copy:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_6769_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-4x:
    - shard-apl:          NOTRUN -> [SKIP][6] ([fdo#109271]) +209 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl1/igt@feature_discovery@display-4x.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed-process.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglb:         NOTRUN -> [SKIP][8] ([i915#280])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@kms:
    - shard-tglb:         NOTRUN -> [FAIL][9] ([i915#232])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         NOTRUN -> [SKIP][10] ([i915#4525])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb8/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][11] ([i915#5076])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@gem_exec_balancer@parallel-contexts.html
    - shard-kbl:          NOTRUN -> [DMESG-WARN][12] ([i915#5076])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl3/igt@gem_exec_balancer@parallel-contexts.html
    - shard-iclb:         NOTRUN -> [DMESG-WARN][13] ([i915#5076])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][16] ([i915#2842]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
    - shard-glk:          NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
    - shard-iclb:         NOTRUN -> [FAIL][18] ([i915#2842])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-tglb:         NOTRUN -> [FAIL][19] ([i915#2842]) +5 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][20] -> [FAIL][21] ([i915#2842]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([fdo#109283] / [i915#4877])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@gem_exec_params@no-vebox.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-kbl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-multi.html
    - shard-glk:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#4613])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk8/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@random:
    - shard-apl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#4613]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl6/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([i915#4613]) +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_pxp@reject-modify-context-protection-on:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#4270]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb3/igt@gem_pxp@reject-modify-context-protection-on.html
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#4270]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb5/igt@gem_pxp@reject-modify-context-protection-on.html

  * igt@gem_softpin@noreloc-s3:
    - shard-snb:          [PASS][29] -> [INCOMPLETE][30] ([i915#5230])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-snb6/igt@gem_softpin@noreloc-s3.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-snb4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([i915#3297])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen3_render_tiledy_blits:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#109289]) +5 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][33] -> [DMESG-WARN][34] ([i915#1436] / [i915#716])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk2/igt@gen9_exec_parse@allowed-all.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk9/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#2527] / [i915#2856]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb3/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([i915#2856]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb1/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         NOTRUN -> [FAIL][37] ([i915#454])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
    - shard-tglb:         NOTRUN -> [FAIL][38] ([i915#454])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([fdo#111644] / [i915#1397] / [i915#2411])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#110892])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-snb:          NOTRUN -> [SKIP][41] ([fdo#109271]) +119 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-snb5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@pc8-residency:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#109293] / [fdo#109506])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb7/igt@i915_pm_rpm@pc8-residency.html
    - shard-tglb:         NOTRUN -> [SKIP][43] ([fdo#109506] / [i915#2411])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@i915_pm_rpm@pc8-residency.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([i915#4387])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@i915_pm_sseu@full-enable.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#1769])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([i915#5286]) +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb1/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#5286]) +6 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#110725] / [fdo#111614])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([fdo#111614]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3777]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3777]) +3 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-glk:          [PASS][52] -> [DMESG-WARN][53] ([i915#118])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk3/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-glk:          NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3777])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#111615]) +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb3/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#110723]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([i915#2705])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_big_joiner@invalid-modeset.html
    - shard-tglb:         NOTRUN -> [SKIP][58] ([i915#2705])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#3886]) +9 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3886]) +10 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#3689] / [i915#3886]) +3 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#3689]) +7 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][63] ([fdo#111615] / [i915#3689]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#3886]) +6 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk5/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][65] ([fdo#109278] / [i915#3886]) +8 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cdclk@plane-scaling:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([i915#3742])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb3/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl6/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-for-each-pipe:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk1/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html

  * igt@kms_chamelium@vga-hpd-without-ddc:
    - shard-snb:          NOTRUN -> [SKIP][69] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-snb6/igt@kms_chamelium@vga-hpd-without-ddc.html

  * igt@kms_color@pipe-d-gamma:
    - shard-iclb:         NOTRUN -> [SKIP][70] ([fdo#109278] / [i915#1149])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb1/igt@kms_color@pipe-d-gamma.html

  * igt@kms_color_chamelium@pipe-a-degamma:
    - shard-kbl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [fdo#111827]) +12 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl4/igt@kms_color_chamelium@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb3/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html

  * igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][73] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-tglb:         NOTRUN -> [SKIP][74] ([fdo#109284] / [fdo#111827]) +10 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_content_protection@content_type_change:
    - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109300] / [fdo#111066]) +1 similar issue
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_content_protection@content_type_change.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([i915#3116])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb3/igt@kms_content_protection@dp-mst-lic-type-1.html
    - shard-tglb:         NOTRUN -> [SKIP][77] ([i915#3116] / [i915#3299])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@srm:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#1063]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@kms_content_protection@srm.html
    - shard-kbl:          NOTRUN -> [TIMEOUT][79] ([i915#1319])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl6/igt@kms_content_protection@srm.html
    - shard-apl:          NOTRUN -> [TIMEOUT][80] ([i915#1319])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl6/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][82] ([fdo#109279] / [i915#3359]) +3 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][83] ([i915#3359]) +6 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb2/igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][84] ([fdo#109274] / [fdo#111825]) +12 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
    - shard-iclb:         NOTRUN -> [SKIP][85] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@pipe-d-single-move:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([fdo#109278]) +18 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb5/igt@kms_cursor_legacy@pipe-d-single-move.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([fdo#109274]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb2/igt@kms_display_modes@extended-mode-basic.html
    - shard-tglb:         NOTRUN -> [SKIP][88] ([fdo#109274])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb5/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([i915#5287]) +2 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html
    - shard-iclb:         NOTRUN -> [SKIP][90] ([i915#5287])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][91] -> [FAIL][92] ([i915#79]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([i915#2587])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-iclb:         [PASS][94] -> [SKIP][95] ([i915#3701])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
    - shard-iclb:         NOTRUN -> [SKIP][96] ([i915#2587])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([fdo#109280]) +17 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][98] ([fdo#109280] / [fdo#111825]) +37 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-glk:          NOTRUN -> [SKIP][99] ([fdo#109271]) +66 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][100] ([i915#3555])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb1/igt@kms_hdr@static-toggle-dpms.html
    - shard-iclb:         NOTRUN -> [SKIP][101] ([i915#3555])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb1/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([i915#1839])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
    - shard-iclb:         NOTRUN -> [SKIP][103] ([fdo#109289]) +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb6/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-apl:          [PASS][104] -> [DMESG-WARN][105] ([i915#180]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265]) +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-glk:          NOTRUN -> [FAIL][107] ([i915#265])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk9/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
    - shard-apl:          NOTRUN -> [FAIL][108] ([i915#265])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][109] ([fdo#108145] / [i915#265]) +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  * igt@kms_plane_lowres@pipe-c-tiling-4:
    - shard-tglb:         NOTRUN -> [SKIP][110] ([i915#5288]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb1/igt@kms_plane_lowres@pipe-c-tiling-4.html
    - shard-iclb:         NOTRUN -> [SKIP][111] ([i915#5288])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@kms_plane_lowres@pipe-c-tiling-4.html

  * igt@kms_plane_lowres@pipe-d-tiling-none:
    - shard-tglb:         NOTRUN -> [SKIP][112] ([i915#3536])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@kms_plane_lowres@pipe-d-tiling-none.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-apl:          NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658]) +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-apl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
    - shard-kbl:          NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658]) +2 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
    - shard-glk:          NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#658])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-glk2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-iclb:         NOTRUN -> [SKIP][116] ([fdo#111068] / [i915#658]) +1 similar issue
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
    - shard-tglb:         NOTRUN -> [SKIP][117] ([i915#2920]) +1 similar issue
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-tglb:         NOTRUN -> [SKIP][118] ([i915#1911])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb8/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr2_dpms:
    - shard-tglb:         NOTRUN -> [FAIL][119] ([i915#132] / [i915#3467]) +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-tglb7/igt@kms_psr@psr2_dpms.html
    - shard-iclb:         NOTRUN -> [SKIP][120] ([fdo#109441])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb1/igt@kms_psr@psr2_dpms.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [PASS][121] -> [SKIP][122] ([fdo#109441]) +1 similar issue
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11347/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-iclb8/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-kbl:          NOTRUN -> [SKIP][123] ([fdo#109271]) +158 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl1/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-kbl:          NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#533])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shard-kbl4/ig

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html

[-- Attachment #2: Type: text/html, Size: 34056 bytes --]

Re: [igt-dev] [PATCH i-g-t 1/6] lib/i915/gem_create: Introduce gem-pool bo cache

[Kamil Konieczny]

Dnia 2022-03-10 at 08:15:24 +0100, Zbigniew Kempczyński napisał(a):
> Handling batchbuffers with softpin requires tracking its state otherwise
> we can write to inflight batchbuffer and encounter gpu hang. Gem pool
> adds such tracking (similar to libdrm bo cache) and provides free and
> ready to use bo. If pool has no free bo new one is created what means pool
> can be growing during test execution. When test completes freeing buffers
> and memory is called from igt_core so no additional cleanup is necessary.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
>  .../igt-gpu-tools/igt-gpu-tools-docs.xml      |   1 +
>  lib/i915/gem_create.c                         | 271 ++++++++++++++++++
>  lib/i915/gem_create.h                         |   4 +
>  lib/igt_core.c                                |   2 +
>  4 files changed, 278 insertions(+)
> 
> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> index 0dc5a0b7e7..c22e70b712 100644
> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> @@ -56,6 +56,7 @@
>    </chapter>
>    <chapter>
>      <title>igt/i915 API Reference</title>
> +    <xi:include href="xml/gem_create.xml"/>
>      <xi:include href="xml/gem_context.xml"/>
>      <xi:include href="xml/gem_engine_topology.xml"/>
>      <xi:include href="xml/gem_scheduler.xml"/>
> diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c
> index b2e8d5595f..605c45139d 100644
> --- a/lib/i915/gem_create.c
> +++ b/lib/i915/gem_create.c
> @@ -4,12 +4,25 @@
>   */
>  
>  #include <errno.h>
> +#include <pthread.h>
>  
> +#include "drmtest.h"
>  #include "gem_create.h"
>  #include "i915_drm.h"
>  #include "igt_core.h"
> +#include "igt_list.h"
> +#include "igt_map.h"
>  #include "ioctl_wrappers.h"
>  
> +/**
> + * SECTION:gem_create
> + * @short_description: Helpers for dealing with objects creation
> + * @title: GEM Create
> + *
> + * This helper library contains functions used for handling creating gem
> + * objects.
> + */
> +
>  int __gem_create(int fd, uint64_t *size, uint32_t *handle)
>  {
>  	struct drm_i915_gem_create create = {
> @@ -88,3 +101,261 @@ uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext)
>  
>  	return handle;
>  }
> +
> +static struct igt_map *pool;
> +static pthread_mutex_t pool_mutex = PTHREAD_MUTEX_INITIALIZER;
> +
> +struct pool_entry {
> +	int fd;
> +	uint32_t handle;
> +	uint64_t size;		/* requested bo size */
> +	uint64_t bo_size;	/* created bo size */
> +	uint32_t region;
> +	struct igt_list_head link;
> +};
> +
> +struct pool_list {
> +	uint64_t size;
> +	struct igt_list_head list;
> +};
> +
> +static struct pool_entry *find_or_create(int fd, struct pool_list *pl,
> +					 uint64_t size, uint32_t region)
> +{
> +	struct pool_entry *pe;
> +	bool found = false;
> +
> +	igt_list_for_each_entry(pe, &pl->list, link) {
> +		if (pe->fd == fd && pe->size == size && pe->region == region &&
> +		    !gem_bo_busy(fd, pe->handle)) {
> +			found = true;
> +			break;
> +		}
> +	}
> +
> +	if (!found) {
> +		pe = calloc(1, sizeof(*pe));
> +		if (!pe)
> +			goto out;
> +
> +		pe->fd = fd;
> +		pe->bo_size = size;
> +		if (__gem_create_in_memory_regions(fd, &pe->handle, &pe->bo_size, region)) {
> +			free(pe);
> +			pe = NULL;
> +			goto out;
> +		}
> +		pe->size = size;
> +		pe->region = region;
> +
> +		igt_list_add_tail(&pe->link, &pl->list);
> +	}
> +
> +out:
> +	return pe;
> +}
> +
> +/**
> + * gem_create_from_pool:
> + * @fd: open i915 drm file descriptor
> + * @size: pointer to size, on input it points to requested bo size,
> + * on output created bo size will be stored there
> + * @region: region in which bo should be created
> + *
> + * Function returns bo handle which is free to use (not busy). Internally
> + * it iterates over previously allocated bo and returns first free. If there
> + * are no free bo a new one is created.
> + *
> + * Returns: bo handle + created bo size (via pointer to size)
> + */
> +uint32_t gem_create_from_pool(int fd, uint64_t *size, uint32_t region)
> +{
> +	struct pool_list *pl;
> +	struct pool_entry *pe;
> +
> +	pthread_mutex_lock(&pool_mutex);
> +
> +	pl = igt_map_search(pool, size);
> +	if (!pl) {
> +		pl = calloc(1, sizeof(*pl));
> +		if (!pl)
> +			goto out;
> +
> +		IGT_INIT_LIST_HEAD(&pl->list);
> +		pl->size = *size;
> +		igt_map_insert(pool, &pl->size, pl);
> +	}
> +	pe = find_or_create(fd, pl, *size, region);
> +
> +out:
> +	pthread_mutex_unlock(&pool_mutex);
> +
> +	igt_assert(pl && pe);
> +
> +	return pe->handle;
> +}
> +
> +static void __pool_list_free_func(struct igt_map_entry *entry)
> +{
> +	free(entry->data);
> +}
> +
> +static void __destroy_pool(struct igt_map *map, pthread_mutex_t *mutex)
> +{
> +	struct igt_map_entry *pos;
> +	const struct pool_list *pl;
> +	struct pool_entry *pe, *tmp;
> +
> +	if (!map)
> +		return;
> +
> +	pthread_mutex_lock(mutex);
> +
> +	igt_map_foreach(map, pos) {
> +		pl = pos->key;
> +		igt_list_for_each_entry_safe(pe, tmp, &pl->list, link) {
> +			gem_close(pe->fd, pe->handle);
> +			igt_list_del(&pe->link);
> +			free(pe);
> +		}
> +	}
> +
> +	pthread_mutex_unlock(mutex);
> +
> +	igt_map_destroy(map, __pool_list_free_func);
> +}
> +
> +void gem_pool_dump(void)
> +{
> +	struct igt_map_entry *pos;
> +	const struct pool_list *pl;
> +	struct pool_entry *pe;
> +
> +	if (!pool)
> +		return;
> +
> +	pthread_mutex_lock(&pool_mutex);
> +
> +	igt_debug("[pool]\n");
> +	igt_map_foreach(pool, pos) {
> +		pl = pos->key;
> +		igt_debug("bucket [%llx]\n", (long long) pl->size);
> +		igt_list_for_each_entry(pe, &pl->list, link)
> +			igt_debug(" - handle: %u, size: %llx, bo_size: %llx, region: %x\n",
> +				  pe->handle, (long long) pe->size,
> +				  (long long) pe->bo_size, pe->region);
> +	}
> +
> +	pthread_mutex_unlock(&pool_mutex);
> +}
> +
> +#define GOLDEN_RATIO_PRIME_64 0x9e37fffffffc0001ULL
> +static inline uint32_t hash_pool(const void *val)
> +{
> +	uint64_t hash = *(uint64_t *) val;
> +
> +	hash = hash * GOLDEN_RATIO_PRIME_64;
> +	return hash >> 32;
> +}
> +
> +static int equal_pool(const void *a, const void *b)
> +{
> +	struct pool_list *p1 = (struct pool_list *) a;
> +	struct pool_list *p2 = (struct pool_list *) b;
> +
> +	return p1->size == p2->size;
> +}
> +
> +/**
> + * gem_pool_init:
> + *
> + * Function initializes bo pool (kind of bo cache). Main purpose of it is to
> + * support working with softpin to achieve pipelined execution on gpu (without
> + * stalls).
> + *
> + * For example imagine code as follows:
> + *
> + * |[<!-- language="C" -->
> + * uint32_t bb = gem_create(fd, 4096);
> + * uint32_t *bbptr = gem_mmap__device_coherent(fd, bb, ...)
> + * uint32_t *cmd = bbptr;
> + * ...
> + * *cmd++ = ...gpu commands...
> + * ...
> + * *cmd++ = MI_BATCH_BUFFER_END;
> + * ...
> + * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- first execbuf
> + *
> + * cmd = bbptr;
> + * ...
> + * *cmd++ = ... next gpu commands...
> + * ...
> + * *cmd++ = MI_BATCH_BUFFER_END;
> + * ...
> + * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- second execbuf
> + * ]|
> + *
> + * Above code is prone to gpu hang because when bb was submitted to gpu
> + * we immediately started writing to it. If gpu started executing commands
> + * from first execbuf we're overwriting it leading to unpredicted behavior
> + * (partially execute from first and second commands or we get gpu hang).
> + * To avoid this we can sync after first execbuf but we will get stall
> + * in execution. For some tests it might be accepted but such "isolated"
> + * execution hides bugs (synchronization, cache flushes, etc).
> + *
> + * So, to achive pipelined execution we need to use another bb. If we would
> + * like to enqueue more work which is serialized we would need more bbs
> + * (depends on execution speed). Handling this manually is cumbersome as
> + * we need to track all bb and their status (busy or free).
> + *
> + * Solution to above is gem pool. It returns first handle of requested size
> + * which is not busy (or create a new one if there's none or all of bo are
> + * in use). Here's an example how to use it:
> + *
> + * |[<!-- language="C" -->
> + * uint64_t bbsize = 4096;
> + * uint32_t bb = gem_create_from_pool(fd, &bbsize, REGION_SMEM);
> + * uint32_t *bbptr = gem_mmap__device_coherent(fd, bb, ...)
> + * uint32_t *cmd = bbptr;
> + * ...
> + * *cmd++ = ...gpu commands...
> + * ...
> + * *cmd++ = MI_BATCH_BUFFER_END;
> + * gem_munmap(bbptr, bbsize);
> + * ...
> + * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- first execbuf
> + *
> + * bbsize = 4096;
> + * bb = gem_create_from_pool(fd, &bbsize, REGION_SMEM);
> + * cmd = bbptr;
> + * ...
> + * *cmd++ = ... next gpu commands...
> + * ...
> + * *cmd++ = MI_BATCH_BUFFER_END;
> + * gem_munmap(bbptr, bbsize);
> + * ...
> + * gem_execbuf(fd, execbuf); // bb is part of execbuf   <--- second execbuf
> + * ]|
> + *
> + * Assuming first execbuf is executed we will get new bb handle when we call
> + * gem_create_from_pool(). When test completes pool is freed automatically
> + * in igt core (all handles will be closed, memory will be freed and gem pool
> + * will be reinitialized for next test).
> + *
> + * Some explanation is needed why we need to put pointer to size instead of
> + * passing absolute value. On discrete regarding memory placement (region)
> + * object created in the memory can be bigger than requested. Especially when
> + * we use allocator to handle vm space and we allocate vma with requested
> + * size (which is smaller than bo created) we can overlap with next allocation
> + * and get -ENOSPC.
> + */
> +void gem_pool_init(void)
> +{
> +	pthread_mutex_init(&pool_mutex, NULL);
> +	__destroy_pool(pool, &pool_mutex);
> +	pool = igt_map_create(hash_pool, equal_pool);
> +}
> +
> +igt_constructor {
> +	gem_pool_init();
> +}
> diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h
> index c2b531b4d7..c32a815d60 100644
> --- a/lib/i915/gem_create.h
> +++ b/lib/i915/gem_create.h
> @@ -16,4 +16,8 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
>                       struct i915_user_extension *ext);
>  uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext);
>  
> +void gem_pool_init(void);
> +void gem_pool_dump(void);
> +uint32_t gem_create_from_pool(int fd, uint64_t *size, uint32_t region);
> +
>  #endif /* GEM_CREATE_H */
> diff --git a/lib/igt_core.c b/lib/igt_core.c
> index f2c701deab..6dad3c8485 100644
> --- a/lib/igt_core.c
> +++ b/lib/igt_core.c
> @@ -58,6 +58,7 @@
>  #include <glib.h>
>  
>  #include "drmtest.h"
> +#include "i915/gem_create.h"
>  #include "intel_allocator.h"
>  #include "intel_batchbuffer.h"
>  #include "intel_chipset.h"
> @@ -1428,6 +1429,7 @@ __noreturn static void exit_subtest(const char *result)
>  	 */
>  	intel_allocator_init();
>  	intel_bb_reinit_allocator();
> +	gem_pool_init();
>  
>  	if (!in_dynamic_subtest)
>  		_igt_dynamic_tests_executed = -1;
> -- 
> 2.32.0
> 
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>

--
Kamil

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Add i915 blt library + gem_ccs test (rev7)

[Zbigniew Kempczyński]

On Thu, Mar 10, 2022 at 12:34:45PM +0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  Add i915 blt library + gem_ccs test (rev7)                     
>    URL:     https://patchwork.freedesktop.org/series/99925/                
>    State:   failure                                                        
>    Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html 
> 
>          CI Bug Log - changes from CI_DRM_11347_full -> IGTPW_6769_full
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with IGTPW_6769_full absolutely need to be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in IGTPW_6769_full, please notify your bug team to allow them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
>    External URL:
>    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html
> 
> Participating hosts (13 -> 7)
> 
>    Missing (6): pig-kbl-iris shard-tglu pig-glk-j5005 pig-skl-6260u shard-rkl
>    shard-dg1
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in
>    IGTPW_6769_full:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@api_intel_allocator@fork-simple-stress:
> 
>           * shard-tglb: NOTRUN -> INCOMPLETE

This is strange, igt@api_intel_allocator@fork-simple-stress-signal is executing
whereas above not:

https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shards-all.html?testfilter=api_intel_allocator@fork-simple

Anyway series haven't touch above test so it is unrelated to above incompletion.

>      * {igt@gem_ccs@block-copy-compressed} (NEW):
> 
>           * shard-tglb: NOTRUN -> SKIP +1 similar issue
>      * {igt@gem_ccs@block-copy-uncompressed} (NEW):
> 
>           * shard-iclb: NOTRUN -> SKIP +2 similar issues

For those generations skip is expected.

--
Zbigniew

> 
>     Suppressed
> 
>    The following results come from untrusted machines, tests, or statuses.
>    They do not affect the overall result.
> 
>      * {igt@kms_setmode@basic@pipe-b-vga-1}:
>           * shard-snb: FAIL ([i915#31]) -> FAIL
> 
> New tests
> 
>    New tests have been introduced between CI_DRM_11347_full and
>    IGTPW_6769_full:
> 
>   New IGT tests (5)
> 
>      * igt@api_intel_allocator@gem-pool:
> 
>           * Statuses : 6 pass(s)
>           * Exec time: [0.00, 0.02] s
>      * igt@gem_ccs@block-copy-compressed:
> 
>           * Statuses : 6 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@block-copy-inplace:
> 
>           * Statuses : 3 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@block-copy-uncompressed:
> 
>           * Statuses : 4 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@ctrl-surf-copy:
> 
>           * Statuses : 6 skip(s)
>           * Exec time: [0.0] s
> 
> Known issues
> 
>    Here are the changes found in IGTPW_6769_full that come from known issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@feature_discovery@display-4x:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271]) +209 similar issues
>      * igt@gem_ctx_persistence@legacy-engines-mixed-process:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [i915#1099])
>      * igt@gem_ctx_sseu@invalid-args:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#280])
>      * igt@gem_eio@kms:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#232])
>      * igt@gem_exec_balancer@parallel:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#4525])
>      * igt@gem_exec_balancer@parallel-contexts:
> 
>           * shard-tglb: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>           * shard-kbl: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>           * shard-iclb: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>      * igt@gem_exec_fair@basic-none-share@rcs0:
> 
>           * shard-iclb: PASS -> FAIL ([i915#2842])
>      * igt@gem_exec_fair@basic-none-solo@rcs0:
> 
>           * shard-kbl: NOTRUN -> FAIL ([i915#2842]) +2 similar issues
> 
>           * shard-glk: NOTRUN -> FAIL ([i915#2842])
> 
>           * shard-iclb: NOTRUN -> FAIL ([i915#2842])
> 
>      * igt@gem_exec_fair@basic-none@vcs0:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#2842]) +5 similar issues
>      * igt@gem_exec_fair@basic-pace-share@rcs0:
> 
>           * shard-glk: PASS -> FAIL ([i915#2842]) +1 similar issue
>      * igt@gem_exec_params@no-vebox:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109283] / [i915#4877])
>      * igt@gem_lmem_swapping@heavy-verify-multi:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +2 similar
>             issues
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
> 
>      * igt@gem_lmem_swapping@random:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +2 similar
>             issues
>      * igt@gem_lmem_swapping@random-engines:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4613]) +2 similar issues
>      * igt@gem_pxp@reject-modify-context-protection-on:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4270]) +2 similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#4270]) +1 similar issue
> 
>      * igt@gem_softpin@noreloc-s3:
> 
>           * shard-snb: PASS -> INCOMPLETE ([i915#5230])
>      * igt@gem_userptr_blits@create-destroy-unsync:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3297])
>      * igt@gen3_render_tiledy_blits:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109289]) +5 similar issues
>      * igt@gen9_exec_parse@allowed-all:
> 
>           * shard-glk: PASS -> DMESG-WARN ([i915#1436] / [i915#716])
>      * igt@gen9_exec_parse@allowed-single:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2527] / [i915#2856]) +3 similar
>             issues
>      * igt@gen9_exec_parse@bb-start-far:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2856]) +2 similar issues
>      * igt@i915_pm_dc@dc6-psr:
> 
>           * shard-iclb: NOTRUN -> FAIL ([i915#454])
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#454])
> 
>      * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111644] / [i915#1397] /
>             [i915#2411])
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110892])
> 
>      * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271]) +119 similar issues
>      * igt@i915_pm_rpm@pc8-residency:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109293] / [fdo#109506])
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109506] / [i915#2411])
> 
>      * igt@i915_pm_sseu@full-enable:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4387])
>      * igt@kms_atomic_transition@plane-all-modeset-transition:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1769])
>      * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5286]) +1 similar issue
>      * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5286]) +6 similar issues
>      * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614])
>      * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111614]) +1 similar issue
>      * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +1 similar
>             issue
>      * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +3 similar
>             issues
>      * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
> 
>           * shard-glk: PASS -> DMESG-WARN ([i915#118])
>      * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3777])
>      * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111615]) +3 similar issues
>      * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110723]) +1 similar issue
>      * igt@kms_big_joiner@invalid-modeset:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2705])
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2705])
> 
>      * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +9 similar
>             issues
>      * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +10
>             similar issues
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3689] / [i915#3886]) +3 similar
>             issues
> 
>      * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3689]) +7 similar issues
>      * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111615] / [i915#3689]) +3
>             similar issues
>      * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +6 similar
>             issues
>      * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#3886]) +8
>             similar issues
>      * igt@kms_cdclk@plane-scaling:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3742])
>      * igt@kms_chamelium@dp-mode-timings:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +14
>             similar issues
>      * igt@kms_chamelium@hdmi-hpd-for-each-pipe:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +3
>             similar issues
>      * igt@kms_chamelium@vga-hpd-without-ddc:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +3
>             similar issues
>      * igt@kms_color@pipe-d-gamma:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#1149])
>      * igt@kms_color_chamelium@pipe-a-degamma:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +12
>             similar issues
>      * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +5
>             similar issues
>      * igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109284] /
>             [fdo#111827])
>      * igt@kms_color_chamelium@pipe-d-ctm-max:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +10
>             similar issues
>      * igt@kms_content_protection@content_type_change:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109300] / [fdo#111066]) +1
>             similar issue
>      * igt@kms_content_protection@dp-mst-lic-type-1:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3116])
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3116] / [i915#3299])
> 
>      * igt@kms_content_protection@srm:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1063]) +1 similar issue
> 
>           * shard-kbl: NOTRUN -> TIMEOUT ([i915#1319])
> 
>           * shard-apl: NOTRUN -> TIMEOUT ([i915#1319])
> 
>      * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109279]) +1
>             similar issue
>      * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109279] / [i915#3359]) +3
>             similar issues
>      * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3359]) +6 similar issues
>      * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109274] / [fdo#111825]) +12
>             similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109274] / [fdo#109278]) +1
>             similar issue
> 
>      * igt@kms_cursor_legacy@pipe-d-single-move:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278]) +18 similar issues
>      * igt@kms_display_modes@extended-mode-basic:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109274]) +1 similar issue
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109274])
> 
>      * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5287]) +2 similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5287])
> 
>      * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
> 
>           * shard-glk: PASS -> FAIL ([i915#79]) +1 similar issue
>      * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2587])
>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
> 
>           * shard-iclb: PASS -> SKIP ([i915#3701])
>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2587])
>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109280]) +17 similar issues
>      * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109280] / [fdo#111825]) +37
>             similar issues
>      * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271]) +66 similar issues
>      * igt@kms_hdr@static-toggle-dpms:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3555])
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3555])
> 
>      * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1839])
>      * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109289]) +1 similar issue
>      * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> 
>           * shard-apl: PASS -> DMESG-WARN ([i915#180]) +1 similar issue
>      * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
> 
>           * shard-apl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +1 similar
>             issue
>      * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
> 
>           * shard-glk: NOTRUN -> FAIL ([i915#265])
> 
>           * shard-apl: NOTRUN -> FAIL ([i915#265])
> 
>      * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
> 
>           * shard-kbl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +1 similar
>             issue
>      * igt@kms_plane_lowres@pipe-c-tiling-4:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5288]) +1 similar issue
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5288])
> 
>      * igt@kms_plane_lowres@pipe-d-tiling-none:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3536])
>      * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +1 similar
>             issue
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +2 similar
>             issues
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#658])
> 
>      * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#111068] / [i915#658]) +1 similar
>             issue
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2920]) +1 similar issue
> 
>      * igt@kms_psr2_su@page_flip-p010:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1911])
>      * igt@kms_psr@psr2_dpms:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#132] / [i915#3467]) +1 similar
>             issue
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109441])
> 
>      * igt@kms_psr@psr2_primary_blt:
> 
>           * shard-iclb: PASS -> SKIP ([fdo#109441]) +1 similar issue
>      * igt@kms_scaling_modes@scaling-mode-full-aspect:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271]) +158 similar issues
>      * igt@kms_vblank@pipe-d-wait-idle:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#533])

Re: [igt-dev] [PATCH i-g-t 4/6] i915/gem_engine_topology: Add helpers for checking driver capabilities

[Zbigniew Kempczyński]

On Thu, Mar 10, 2022 at 08:15:27AM +0100, Zbigniew Kempczyński wrote:
> From: Chris Wilson <chris.p.wilson@intel.com>
> 
> If driver is able to report capabilities we want to use them in easy way.
> For example it can support blitter "block_copy" (XY_BLOCK_COPY_BLT
> command) and reports it in sysfs. We add then capabilities helpers to
> read these properties. Helpers allows checking does driver knows
> capability (by checking sysfs "known_capabilities" file) and supports it
> (by checking sysfs "capabilities" file). Dedicated helper was added to
> verify "block_copy" capability.
> 
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>

Looks good for me.

Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

--
Zbigniew

> ---
>  lib/i915/gem_engine_topology.c | 39 ++++++++++++++++++++++++++++++++++
>  lib/i915/gem_engine_topology.h |  5 +++++
>  2 files changed, 44 insertions(+)
> 
> diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
> index bd12d0bc98..ca3333c252 100644
> --- a/lib/i915/gem_engine_topology.c
> +++ b/lib/i915/gem_engine_topology.c
> @@ -534,6 +534,45 @@ void gem_engine_properties_restore(int fd, const struct gem_engine_properties *s
>  	}
>  }
>  
> +static bool
> +__gem_engine_has_capability(int i915, const char *engine,
> +			    const char *attr, const char *cap)
> +{
> +	char buf[4096] = {};
> +	FILE *file;
> +
> +	file = __open_attr(igt_sysfs_open(i915), "r",
> +			   "engine", engine, attr, NULL);
> +	if (!file)
> +		return NULL;
> +
> +	fread(buf, 1, sizeof(buf) - 1, file);
> +	fclose(file);
> +
> +	return strstr(buf, cap);
> +}
> +
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap)
> +{
> +	return __gem_engine_has_capability(i915, engine, "capabilities", cap);
> +}
> +
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap)
> +{
> +	return __gem_engine_has_capability(i915, engine, "known_capabilities", cap);
> +}
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine)
> +{
> +	if (engine->class != I915_ENGINE_CLASS_COPY)
> +		return false;
> +
> +	if (!gem_engine_has_known_capability(i915, engine->name, "block_copy"))
> +		return intel_gen(intel_get_drm_devid(i915)) >= 12;
> +
> +	return gem_engine_has_capability(i915, engine->name, "block_copy");
> +}
> +
>  uint32_t gem_engine_mmio_base(int i915, const char *engine)
>  {
>  	unsigned int mmio = 0;
> diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
> index b413aa8aba..987f2bf944 100644
> --- a/lib/i915/gem_engine_topology.h
> +++ b/lib/i915/gem_engine_topology.h
> @@ -133,6 +133,11 @@ int gem_engine_property_printf(int i915, const char *engine, const char *attr,
>  
>  uint32_t gem_engine_mmio_base(int i915, const char *engine);
>  
> +bool gem_engine_has_capability(int i915, const char *engine, const char *cap);
> +bool gem_engine_has_known_capability(int i915, const char *engine, const char *cap);
> +
> +bool gem_engine_can_block_copy(int i915, const struct intel_execution_engine2 *engine);
> +
>  void dyn_sysfs_engines(int i915, int engines, const char *file,
>  		       void (*test)(int i915, int engine));
>  
> -- 
> 2.32.0
> 

Re: [igt-dev] [PATCH i-g-t 2/6] tests/api_intel_allocator: Verify gem-pool is working as expected

[Kamil Konieczny]

Dnia 2022-03-10 at 08:15:25 +0100, Zbigniew Kempczyński napisał(a):
> Simple check which acquires buffer objects from gem-pool. It verifies:
> - object reuse (previously created is completed in execbuf)
> - object creation (submitting batches when spinner is executing).
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
>  tests/i915/api_intel_allocator.c | 58 ++++++++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c
> index a652caf4ec..a7929e9b13 100644
> --- a/tests/i915/api_intel_allocator.c
> +++ b/tests/i915/api_intel_allocator.c
> @@ -692,6 +692,60 @@ static void fork_reopen_allocator(int fd, uint8_t type)
>  	intel_allocator_multiprocess_stop();
>  }
>  
> +static uint32_t single_exec_from_pool(int i915, uint64_t ahnd, uint64_t size)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj = {};
> +	uint32_t bb = gem_create_from_pool(i915, &size, REGION_SMEM);
> +	uint32_t *bbptr;
> +
> +	bbptr = gem_mmap__device_coherent(i915, bb, 0, size, PROT_WRITE);
> +	*bbptr = MI_BATCH_BUFFER_END;
> +	gem_munmap(bbptr, size);
> +	obj.offset = get_offset(ahnd, bb, size, 0);
> +	if (ahnd)
> +		obj.flags = EXEC_OBJECT_PINNED;
> +	obj.handle = bb;
> +	execbuf.buffer_count = 1;
> +	execbuf.buffers_ptr = to_user_pointer(&obj);
> +	gem_execbuf(i915, &execbuf);
> +
> +	return bb;
> +}
> +
> +static void gem_pool(int i915)
> +{
> +	uint32_t bb[4];
> +	uint64_t ahnd = get_reloc_ahnd(i915, 0);
> +	igt_spin_t *spin;
> +
> +	bb[0] = single_exec_from_pool(i915, ahnd, 4096);
> +	gem_sync(i915, bb[0]);
> +	bb[1] = single_exec_from_pool(i915, ahnd, 4096);
> +	igt_assert(bb[0] == bb[1]);
> +
> +	bb[2] = single_exec_from_pool(i915, ahnd, 8192);
> +	gem_sync(i915, bb[2]);
> +	bb[3] = single_exec_from_pool(i915, ahnd, 8192);
> +	igt_assert(bb[2] == bb[3]);
> +	igt_assert(bb[0] != bb[2]);
> +
> +	spin = igt_spin_new(i915,
> +			    .ahnd = ahnd,
> +			    .engine = I915_EXEC_DEFAULT);
> +	bb[0] = single_exec_from_pool(i915, ahnd, 4096);
> +	bb[1] = single_exec_from_pool(i915, ahnd, 4096);
> +	bb[2] = single_exec_from_pool(i915, ahnd, 8192);
> +	bb[3] = single_exec_from_pool(i915, ahnd, 8192);
> +	igt_spin_free(i915, spin);
> +	igt_assert(bb[0] != bb[1]);
> +	igt_assert(bb[2] != bb[3]);
> +
> +	put_ahnd(ahnd);
> +
> +	gem_pool_dump();
> +}
> +
>  struct allocators {
>  	const char *name;
>  	uint8_t type;
> @@ -790,6 +844,10 @@ igt_main
>  	igt_subtest_f("execbuf-with-allocator")
>  		execbuf_with_allocator(fd);
>  
> +	igt_describe("Verifies creating and executing bb from gem pool");
> +	igt_subtest_f("gem-pool")
> +		gem_pool(fd);
> +
>  	igt_fixture
>  		close(fd);
>  }
> -- 
> 2.32.0
> 
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>

--
Kamil

Re: [igt-dev] [PATCH i-g-t 3/6] lib/i915: Introduce library intel_mocs

[Kamil Konieczny]

Hi Zbigniew,

Dnia 2022-03-10 at 08:15:26 +0100, Zbigniew Kempczyński napisał(a):
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Add new library intel_mocs for mocs settings.
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/i915/intel_mocs.c | 56 +++++++++++++++++++++++++++++++++++++++++++
>  lib/i915/intel_mocs.h | 25 +++++++++++++++++++
>  lib/meson.build       |  1 +
>  3 files changed, 82 insertions(+)
>  create mode 100644 lib/i915/intel_mocs.c
>  create mode 100644 lib/i915/intel_mocs.h
> 
> diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
> new file mode 100644
> index 0000000000..63ead1118f
> --- /dev/null
> +++ b/lib/i915/intel_mocs.c
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "intel_mocs.h"
> +
> +static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> +{
> +	uint16_t devid = intel_get_drm_devid(fd);
> +
> +	/*
> +	 * Gen >= 12 onwards don't have a setting for PTE,
> +	 * so using I915_MOCS_PTE as mocs index may leads to
> +	 * some undefined MOCS behavior.
> +	 * This helper function is providing current UC as well
> +	 * as WB MOCS index based on platform.
> +	 */
> +	if (IS_DG1(devid)) {
> +		mocs->uc_index = DG1_MOCS_UC_IDX;
> +		mocs->wb_index = DG1_MOCS_WB_IDX;
> +	} else if (IS_DG2(devid)) {
> +		mocs->uc_index = DG2_MOCS_UC_IDX;
> +		mocs->wb_index = DG2_MOCS_WB_IDX;
> +
> +	} else if (IS_GEN12(devid)) {
> +		mocs->uc_index = GEN12_MOCS_UC_IDX;
> +		mocs->wb_index = GEN12_MOCS_WB_IDX;
> +	} else {
> +		mocs->uc_index = I915_MOCS_PTE;
> +		mocs->wb_index = I915_MOCS_CACHED;
> +		igt_info("C1\n");

Remove this or make it igt_debug.

> +	}
> +}
> +
> +/* BitField [6:1] represents index to MOCS Tables
> + * BitField [0] represents Encryption/Decryption
> + */
> +
> +uint8_t intel_get_wb_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.wb_index << 1;
> +}
> +
> +uint8_t intel_get_uc_mocs(int fd)
> +{
> +	struct drm_i915_mocs_index mocs;
> +
> +	get_mocs_index(fd, &mocs);
> +	return mocs.uc_index << 1;
> +}
> diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
> new file mode 100644
> index 0000000000..c05569f426
> --- /dev/null
> +++ b/lib/i915/intel_mocs.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _INTEL_MOCS_H
> +#define _INTEL_MOCS_H
> +
> +#define DG1_MOCS_UC_IDX			1
> +#define DG1_MOCS_WB_IDX			5
> +#define DG2_MOCS_UC_IDX			1
> +#define DG2_MOCS_WB_IDX			3
> +#define GEN12_MOCS_UC_IDX			3
> +#define GEN12_MOCS_WB_IDX			2

Do we need this here ? Can it be placed in lib implementation
and hided there ?

> +#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
> +#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25

Same here, there is no uses for this constants. They can stay
if you can tell they will be used in near future.

> +
> +struct drm_i915_mocs_index {
> +	uint8_t uc_index;
> +	uint8_t wb_index;
> +};
> +
> +uint8_t intel_get_wb_mocs(int fd);
> +uint8_t intel_get_uc_mocs(int fd);

These helpers returns uc and wb index, so maybe struct can be
moved to .c implementation ? So we can keep headers clean. It is
up to you, I do not insist on changes in header file.

> +#endif /* _INTEL_MOCS_H */
> diff --git a/lib/meson.build b/lib/meson.build
> index 3e43316d1e..a5fe91dc99 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -11,6 +11,7 @@ lib_sources = [
>  	'i915/gem_mman.c',
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
> +	'i915/intel_mocs.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.32.0
> 

With that fixed you can add my r-b tag,

Regards,
Kamil

Re: [igt-dev] [PATCH i-g-t 5/6] lib/i915_blt: Add library for blitter

[Kamil Konieczny]

Dnia 2022-03-10 at 08:15:28 +0100, Zbigniew Kempczyński napisał(a):
> Blitter commands became complicated thus manual bitshifting is error
> prone and hard debugable - XY_BLOCK_COPY_BLT is the best example -
> in extended version (for DG2+) it takes 20 dwords of command data.
> To avoid mistakes and dozens of arguments for command library provides
> input data in more structured form.
> 
> Currently supported commands:
> - XY_BLOCK_COPY_BLT:
>   a)  TGL/DG1 uses shorter version of command which doesn't support
>       compression
>   b)  DG2+ command is extended and supports compression
> - XY_CTRL_SURF_COPY_BLT
> - XY_FAST_COPY_BLT
> 
> Source, destination and batchbuffer are provided to blitter functions
> as objects (structs). This increases readability and allows use same
> object in many functions. Only drawback of such attitude is some fields
> used in one function may be ignored in another. As an example is
> blt_copy_object which contains a lot of information about gem object.
> In block-copy all of data are used but in fast-copy only some of them
> (fast-copy doesn't support compression).
> 
> v2-v3: address review comments (Kamil)
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---

Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>

--
Kamil

>  .../igt-gpu-tools/igt-gpu-tools-docs.xml      |    1 +
>  lib/i915/i915_blt.c                           | 1082 +++++++++++++++++
>  lib/i915/i915_blt.h                           |  196 +++
>  lib/meson.build                               |    1 +
>  4 files changed, 1280 insertions(+)
>  create mode 100644 lib/i915/i915_blt.c
>  create mode 100644 lib/i915/i915_blt.h
> 
> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> index c22e70b712..1774256530 100644
> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> @@ -61,6 +61,7 @@
>      <xi:include href="xml/gem_engine_topology.xml"/>
>      <xi:include href="xml/gem_scheduler.xml"/>
>      <xi:include href="xml/gem_submission.xml"/>
> +    <xi:include href="xml/i915_blt.xml"/>
>      <xi:include href="xml/intel_ctx.xml"/>
>    </chapter>
>    <xi:include href="xml/igt_test_programs.xml"/>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> new file mode 100644
> index 0000000000..8d46e51fb7
> --- /dev/null
> +++ b/lib/i915/i915_blt.c
> @@ -0,0 +1,1082 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include <cairo.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "gem_create.h"
> +#include "i915_blt.h"
> +
> +#define BITRANGE(start, end) (end - start + 1)
> +
> +enum blt_special_mode {
> +	SM_NONE,
> +	SM_FULL_RESOLVE,
> +	SM_PARTIAL_RESOLVE,
> +	SM_RESERVED,
> +};
> +
> +enum blt_aux_mode {
> +	AM_AUX_NONE,
> +	AM_AUX_CCS_E = 5,
> +};
> +
> +enum blt_target_mem {
> +	TM_LOCAL_MEM,
> +	TM_SYSTEM_MEM,
> +};
> +
> +struct gen12_block_copy_data {
> +	struct {
> +		uint32_t length:			BITRANGE(0, 7);
> +		uint32_t rsvd1:				BITRANGE(8, 8);
> +		uint32_t multisamples:			BITRANGE(9, 11);
> +		uint32_t special_mode:			BITRANGE(12, 13);
> +		uint32_t rsvd0:				BITRANGE(14, 18);
> +		uint32_t color_depth:			BITRANGE(19, 21);
> +		uint32_t opcode:			BITRANGE(22, 28);
> +		uint32_t client:			BITRANGE(29, 31);
> +	} dw00;
> +
> +	struct {
> +		uint32_t dst_pitch:			BITRANGE(0, 17);
> +		uint32_t dst_aux_mode:			BITRANGE(18, 20);
> +		uint32_t dst_mocs:			BITRANGE(21, 27);
> +		uint32_t dst_ctrl_surface_type:		BITRANGE(28, 28);
> +		uint32_t dst_compression:		BITRANGE(29, 29);
> +		uint32_t dst_tiling:			BITRANGE(30, 31);
> +	} dw01;
> +
> +	struct {
> +		int32_t dst_x1:				BITRANGE(0, 15);
> +		int32_t dst_y1:				BITRANGE(16, 31);
> +	} dw02;
> +
> +	struct {
> +		int32_t dst_x2:				BITRANGE(0, 15);
> +		int32_t dst_y2:				BITRANGE(16, 31);
> +	} dw03;
> +
> +	struct {
> +		uint32_t dst_address_lo;
> +	} dw04;
> +
> +	struct {
> +		uint32_t dst_address_hi;
> +	} dw05;
> +
> +	struct {
> +		uint32_t dst_x_offset:			BITRANGE(0, 13);
> +		uint32_t rsvd1:				BITRANGE(14, 15);
> +		uint32_t dst_y_offset:			BITRANGE(16, 29);
> +		uint32_t rsvd0:				BITRANGE(30, 30);
> +		uint32_t dst_target_memory:		BITRANGE(31, 31);
> +	} dw06;
> +
> +	struct {
> +		int32_t src_x1:				BITRANGE(0, 15);
> +		int32_t src_y1:				BITRANGE(16, 31);
> +	} dw07;
> +
> +	struct {
> +		uint32_t src_pitch:			BITRANGE(0, 17);
> +		uint32_t src_aux_mode:			BITRANGE(18, 20);
> +		uint32_t src_mocs:			BITRANGE(21, 27);
> +		uint32_t src_ctrl_surface_type:		BITRANGE(28, 28);
> +		uint32_t src_compression:		BITRANGE(29, 29);
> +		uint32_t src_tiling:			BITRANGE(30, 31);
> +	} dw08;
> +
> +	struct {
> +		uint32_t src_address_lo;
> +	} dw09;
> +
> +	struct {
> +		uint32_t src_address_hi;
> +	} dw10;
> +
> +	struct {
> +		uint32_t src_x_offset:			BITRANGE(0, 13);
> +		uint32_t rsvd1:				BITRANGE(14, 15);
> +		uint32_t src_y_offset:			BITRANGE(16, 29);
> +		uint32_t rsvd0:				BITRANGE(30, 30);
> +		uint32_t src_target_memory:		BITRANGE(31, 31);
> +	} dw11;
> +};
> +
> +struct gen12_block_copy_data_ext {
> +	struct {
> +		uint32_t src_compression_format:	BITRANGE(0, 4);
> +		uint32_t src_clear_value_enable:	BITRANGE(5, 5);
> +		uint32_t src_clear_address_low:		BITRANGE(6, 31);
> +	} dw12;
> +
> +	union {
> +		/* DG2, XEHP */
> +		uint32_t src_clear_address_hi0;
> +		/* Others */
> +		uint32_t src_clear_address_hi1;
> +	} dw13;
> +
> +	struct {
> +		uint32_t dst_compression_format:	BITRANGE(0, 4);
> +		uint32_t dst_clear_value_enable:	BITRANGE(5, 5);
> +		uint32_t dst_clear_address_low:		BITRANGE(6, 31);
> +	} dw14;
> +
> +	union {
> +		/* DG2, XEHP */
> +		uint32_t dst_clear_address_hi0;
> +		/* Others */
> +		uint32_t dst_clear_address_hi1;
> +	} dw15;
> +
> +	struct {
> +		uint32_t dst_surface_height:		BITRANGE(0, 13);
> +		uint32_t dst_surface_width:		BITRANGE(14, 27);
> +		uint32_t rsvd0:				BITRANGE(28, 28);
> +		uint32_t dst_surface_type:		BITRANGE(29, 31);
> +	} dw16;
> +
> +	struct {
> +		uint32_t dst_lod:			BITRANGE(0, 3);
> +		uint32_t dst_surface_qpitch:		BITRANGE(4, 18);
> +		uint32_t rsvd0:				BITRANGE(19, 20);
> +		uint32_t dst_surface_depth:		BITRANGE(21, 31);
> +	} dw17;
> +
> +	struct {
> +		uint32_t dst_horizontal_align:		BITRANGE(0, 1);
> +		uint32_t rsvd0:				BITRANGE(2, 2);
> +		uint32_t dst_vertical_align:		BITRANGE(3, 4);
> +		uint32_t rsvd1:				BITRANGE(5, 7);
> +		uint32_t dst_mip_tail_start_lod:	BITRANGE(8, 11);
> +		uint32_t rsvd2:				BITRANGE(12, 17);
> +		uint32_t dst_depth_stencil_resource:	BITRANGE(18, 18);
> +		uint32_t rsvd3:				BITRANGE(19, 20);
> +		uint32_t dst_array_index:		BITRANGE(21, 31);
> +	} dw18;
> +
> +	struct {
> +		uint32_t src_surface_height:		BITRANGE(0, 13);
> +		uint32_t src_surface_width:		BITRANGE(14, 27);
> +		uint32_t rsvd0:				BITRANGE(28, 28);
> +		uint32_t src_surface_type:		BITRANGE(29, 31);
> +	} dw19;
> +
> +	struct {
> +		uint32_t src_lod:			BITRANGE(0, 3);
> +		uint32_t src_surface_qpitch:		BITRANGE(4, 18);
> +		uint32_t rsvd0:				BITRANGE(19, 20);
> +		uint32_t src_surface_depth:		BITRANGE(21, 31);
> +	} dw20;
> +
> +	struct {
> +		uint32_t src_horizontal_align:		BITRANGE(0, 1);
> +		uint32_t rsvd0:				BITRANGE(2, 2);
> +		uint32_t src_vertical_align:		BITRANGE(3, 4);
> +		uint32_t rsvd1:				BITRANGE(5, 7);
> +		uint32_t src_mip_tail_start_lod:	BITRANGE(8, 11);
> +		uint32_t rsvd2:				BITRANGE(12, 17);
> +		uint32_t src_depth_stencil_resource:	BITRANGE(18, 18);
> +		uint32_t rsvd3:				BITRANGE(19, 20);
> +		uint32_t src_array_index:		BITRANGE(21, 31);
> +	} dw21;
> +};
> +
> +/**
> + * blt_supports_compression:
> + * @i915: drm fd
> + *
> + * Function checks if HW supports flatccs compression in blitter commands
> + * on @i915 device.
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_supports_compression(int i915)
> +{
> +	uint32_t devid = intel_get_drm_devid(i915);
> +
> +	return HAS_FLATCCS(devid);
> +}
> +
> +/**
> + * blt_supports_tiling:
> + * @i915: drm fd
> + * @tiling: tiling id
> + *
> + * Function checks if blitter supports @tiling on @i915 device.
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_supports_tiling(int i915, enum blt_tiling tiling)
> +{
> +	uint32_t devid = intel_get_drm_devid(i915);
> +
> +	if (tiling == T_XMAJOR) {
> +		if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> +			return false;
> +		else
> +			return true;
> +	}
> +
> +	if (tiling == T_YMAJOR) {
> +		if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> +			return true;
> +		else
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
> +/**
> + * blt_tiling_name:
> + * @tiling: tiling id
> + *
> + * Returns:
> + * name of @tiling passed. Useful to build test names.
> + */
> +const char *blt_tiling_name(enum blt_tiling tiling)
> +{
> +	switch (tiling) {
> +	case T_LINEAR: return "linear";
> +	case T_XMAJOR: return "xmajor";
> +	case T_YMAJOR: return "ymajor";
> +	case T_TILE4:  return "tile4";
> +	case T_TILE64: return "tile64";
> +	}
> +
> +	igt_warn("invalid tiling passed: %d\n", tiling);
> +	return NULL;
> +}
> +
> +static int __block_tiling(enum blt_tiling tiling)
> +{
> +	switch (tiling) {
> +	case T_LINEAR: return 0;
> +	case T_XMAJOR: return 1;
> +	case T_YMAJOR: return 1;
> +	case T_TILE4:  return 2;
> +	case T_TILE64: return 3;
> +	}
> +
> +	igt_warn("invalid tiling passed: %d\n", tiling);
> +	return 0;
> +}
> +
> +static int __special_mode(const struct blt_copy_data *blt)
> +{
> +	if (blt->src.handle == blt->dst.handle &&
> +	    blt->src.compression && !blt->dst.compression)
> +		return SM_FULL_RESOLVE;
> +
> +
> +	return SM_NONE;
> +}
> +
> +static int __memory_type(uint32_t region)
> +{
> +	igt_assert_f(IS_DEVICE_MEMORY_REGION(region) ||
> +		     IS_SYSTEM_MEMORY_REGION(region),
> +		     "Invalid region: %x\n", region);
> +
> +	if (IS_DEVICE_MEMORY_REGION(region))
> +		return TM_LOCAL_MEM;
> +	return TM_SYSTEM_MEM;
> +}
> +
> +static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
> +{
> +	if (obj->compression == COMPRESSION_ENABLED) {
> +		igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region),
> +			     "XY_BLOCK_COPY_BLT supports compression "
> +			     "on device memory only\n");
> +		return AM_AUX_CCS_E;
> +	}
> +
> +	return AM_AUX_NONE;
> +}
> +
> +static void fill_data(struct gen12_block_copy_data *data,
> +		      const struct blt_copy_data *blt,
> +		      uint64_t src_offset, uint64_t dst_offset,
> +		      bool extended_command)
> +{
> +	data->dw00.client = 0x2;
> +	data->dw00.opcode = 0x41;
> +	data->dw00.color_depth = blt->color_depth;
> +	data->dw00.special_mode = __special_mode(blt);
> +	data->dw00.length = extended_command ? 20 : 10;
> +
> +	data->dw01.dst_pitch = blt->dst.pitch - 1;
> +	data->dw01.dst_aux_mode = __aux_mode(&blt->dst);
> +	data->dw01.dst_mocs = blt->dst.mocs;
> +	data->dw01.dst_compression = blt->dst.compression;
> +	data->dw01.dst_tiling = __block_tiling(blt->dst.tiling);
> +
> +	if (blt->dst.compression)
> +		data->dw01.dst_ctrl_surface_type = blt->dst.compression_type;
> +
> +	data->dw02.dst_x1 = blt->dst.x1;
> +	data->dw02.dst_y1 = blt->dst.y1;
> +
> +	data->dw03.dst_x2 = blt->dst.x2;
> +	data->dw03.dst_y2 = blt->dst.y2;
> +
> +	data->dw04.dst_address_lo = dst_offset;
> +	data->dw05.dst_address_hi = dst_offset >> 32;
> +
> +	data->dw06.dst_x_offset = blt->dst.x_offset;
> +	data->dw06.dst_y_offset = blt->dst.y_offset;
> +	data->dw06.dst_target_memory = __memory_type(blt->dst.region);
> +
> +	data->dw07.src_x1 = blt->src.x1;
> +	data->dw07.src_y1 = blt->src.y1;
> +
> +	data->dw08.src_pitch = blt->src.pitch - 1;
> +	data->dw08.src_aux_mode = __aux_mode(&blt->src);
> +	data->dw08.src_mocs = blt->src.mocs;
> +	data->dw08.src_compression = blt->src.compression;
> +	data->dw08.src_tiling = __block_tiling(blt->src.tiling);
> +
> +	if (blt->src.compression)
> +		data->dw08.src_ctrl_surface_type = blt->src.compression_type;
> +
> +	data->dw09.src_address_lo = src_offset;
> +	data->dw10.src_address_hi = src_offset >> 32;
> +
> +	data->dw11.src_x_offset = blt->src.x_offset;
> +	data->dw11.src_y_offset = blt->src.y_offset;
> +	data->dw11.src_target_memory = __memory_type(blt->src.region);
> +}
> +
> +static void fill_data_ext(struct gen12_block_copy_data_ext *dext,
> +			  const struct blt_block_copy_data_ext *ext)
> +{
> +	dext->dw12.src_compression_format = ext->src.compression_format;
> +	dext->dw12.src_clear_value_enable = ext->src.clear_value_enable;
> +	dext->dw12.src_clear_address_low = ext->src.clear_address;
> +
> +	dext->dw13.src_clear_address_hi0 = ext->src.clear_address >> 32;
> +
> +	dext->dw14.dst_compression_format = ext->dst.compression_format;
> +	dext->dw14.dst_clear_value_enable = ext->dst.clear_value_enable;
> +	dext->dw14.dst_clear_address_low = ext->dst.clear_address;
> +
> +	dext->dw15.dst_clear_address_hi0 = ext->dst.clear_address >> 32;
> +
> +	dext->dw16.dst_surface_width = ext->dst.surface_width - 1;
> +	dext->dw16.dst_surface_height = ext->dst.surface_height - 1;
> +	dext->dw16.dst_surface_type = ext->dst.surface_type;
> +
> +	dext->dw17.dst_lod = ext->dst.lod;
> +	dext->dw17.dst_surface_depth = ext->dst.surface_depth;
> +	dext->dw17.dst_surface_qpitch = ext->dst.surface_qpitch;
> +
> +	dext->dw18.dst_horizontal_align = ext->dst.horizontal_align;
> +	dext->dw18.dst_vertical_align = ext->dst.vertical_align;
> +	dext->dw18.dst_mip_tail_start_lod = ext->dst.mip_tail_start_lod;
> +	dext->dw18.dst_depth_stencil_resource = ext->dst.depth_stencil_resource;
> +	dext->dw18.dst_array_index = ext->dst.array_index;
> +
> +	dext->dw19.src_surface_width = ext->src.surface_width - 1;
> +	dext->dw19.src_surface_height = ext->src.surface_height - 1;
> +
> +	dext->dw19.src_surface_type = ext->src.surface_type;
> +
> +	dext->dw20.src_lod = ext->src.lod;
> +	dext->dw20.src_surface_depth = ext->src.surface_depth;
> +	dext->dw20.src_surface_qpitch = ext->src.surface_qpitch;
> +
> +	dext->dw21.src_horizontal_align = ext->src.horizontal_align;
> +	dext->dw21.src_vertical_align = ext->src.vertical_align;
> +	dext->dw21.src_mip_tail_start_lod = ext->src.mip_tail_start_lod;
> +	dext->dw21.src_depth_stencil_resource = ext->src.depth_stencil_resource;
> +	dext->dw21.src_array_index = ext->src.array_index;
> +}
> +
> +static void dump_bb_cmd(struct gen12_block_copy_data *data)
> +{
> +	uint32_t *cmd = (uint32_t *) data;
> +
> +	igt_info("details:\n");
> +	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, color depth: %d, "
> +		 "special mode: %d, length: %d>\n",
> +		 cmd[0],
> +		 data->dw00.client, data->dw00.opcode, data->dw00.color_depth,
> +		 data->dw00.special_mode, data->dw00.length);
> +	igt_info(" dw01: [%08x] dst <pitch: %d, aux: %d, mocs: %d, compr: %d, "
> +		 "tiling: %d, ctrl surf type: %d>\n",
> +		 cmd[1], data->dw01.dst_pitch, data->dw01.dst_aux_mode,
> +		 data->dw01.dst_mocs, data->dw01.dst_compression,
> +		 data->dw01.dst_tiling, data->dw01.dst_ctrl_surface_type);
> +	igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
> +		 cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
> +	igt_info(" dw03: [%08x]          <x2: %d, y2: %d>\n",
> +		 cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
> +	igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
> +		 cmd[4], data->dw04.dst_address_lo);
> +	igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
> +		 cmd[5], data->dw05.dst_address_hi);
> +	igt_info(" dw06: [%08x] dst <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
> +		 cmd[6], data->dw06.dst_x_offset, data->dw06.dst_y_offset,
> +		 data->dw06.dst_target_memory);
> +	igt_info(" dw07: [%08x] src geom <x1: %d, y1: %d>\n",
> +		 cmd[7], data->dw07.src_x1, data->dw07.src_y1);
> +	igt_info(" dw08: [%08x] src <pitch: %d, aux: %d, mocs: %d, compr: %d, "
> +		 "tiling: %d, ctrl surf type: %d>\n",
> +		 cmd[8], data->dw08.src_pitch, data->dw08.src_aux_mode,
> +		 data->dw08.src_mocs, data->dw08.src_compression,
> +		 data->dw08.src_tiling, data->dw08.src_ctrl_surface_type);
> +	igt_info(" dw09: [%08x] src offset lo (0x%x)\n",
> +		 cmd[9], data->dw09.src_address_lo);
> +	igt_info(" dw10: [%08x] src offset hi (0x%x)\n",
> +		 cmd[10], data->dw10.src_address_hi);
> +	igt_info(" dw11: [%08x] src <x offset: 0x%x, y offset: 0x%0x, target mem: %d>\n",
> +		 cmd[11], data->dw11.src_x_offset, data->dw11.src_y_offset,
> +		 data->dw11.src_target_memory);
> +}
> +
> +static void dump_bb_ext(struct gen12_block_copy_data_ext *data)
> +{
> +	uint32_t *cmd = (uint32_t *) data;
> +
> +	igt_info("ext details:\n");
> +	igt_info(" dw12: [%08x] src <compression fmt: %d, clear value enable: %d, "
> +		 "clear address low: 0x%x>\n",
> +		 cmd[0],
> +		 data->dw12.src_compression_format,
> +		 data->dw12.src_clear_value_enable,
> +		 data->dw12.src_clear_address_low);
> +	igt_info(" dw13: [%08x] src clear address hi: 0x%x\n",
> +		 cmd[1], data->dw13.src_clear_address_hi0);
> +	igt_info(" dw14: [%08x] dst <compression fmt: %d, clear value enable: %d, "
> +		 "clear address low: 0x%x>\n",
> +		 cmd[2],
> +		 data->dw14.dst_compression_format,
> +		 data->dw14.dst_clear_value_enable,
> +		 data->dw14.dst_clear_address_low);
> +	igt_info(" dw15: [%08x] dst clear address hi: 0x%x\n",
> +		 cmd[3], data->dw15.dst_clear_address_hi0);
> +	igt_info(" dw16: [%08x] dst surface <width: %d, height: %d, type: %d>\n",
> +		 cmd[4], data->dw16.dst_surface_width,
> +		 data->dw16.dst_surface_height, data->dw16.dst_surface_type);
> +	igt_info(" dw17: [%08x] dst surface <lod: %d, depth: %d, qpitch: %d>\n",
> +		 cmd[5], data->dw17.dst_lod,
> +		 data->dw17.dst_surface_depth, data->dw17.dst_surface_qpitch);
> +	igt_info(" dw18: [%08x] dst <halign: %d, valign: %d, mip tail: %d, "
> +		 "depth stencil: %d, array index: %d>\n",
> +		 cmd[6],
> +		 data->dw18.dst_horizontal_align,
> +		 data->dw18.dst_vertical_align,
> +		 data->dw18.dst_mip_tail_start_lod,
> +		 data->dw18.dst_depth_stencil_resource,
> +		 data->dw18.dst_array_index);
> +
> +	igt_info(" dw19: [%08x] src surface <width: %d, height: %d, type: %d>\n",
> +		 cmd[7], data->dw19.src_surface_width,
> +		 data->dw19.src_surface_height, data->dw19.src_surface_type);
> +	igt_info(" dw20: [%08x] src surface <lod: %d, depth: %d, qpitch: %d>\n",
> +		 cmd[8], data->dw20.src_lod,
> +		 data->dw20.src_surface_depth, data->dw20.src_surface_qpitch);
> +	igt_info(" dw21: [%08x] src <halign: %d, valign: %d, mip tail: %d, "
> +		 "depth stencil: %d, array index: %d>\n",
> +		 cmd[9],
> +		 data->dw21.src_horizontal_align,
> +		 data->dw21.src_vertical_align,
> +		 data->dw21.src_mip_tail_start_lod,
> +		 data->dw21.src_depth_stencil_resource,
> +		 data->dw21.src_array_index);
> +}
> +
> +/**
> + * blt_block_copy:
> + * @i915: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: basic blitter data (for TGL/DG1 which doesn't support ext version)
> + * @ext: extended blitter data (for DG2+, supports flatccs compression)
> + *
> + * Function does blit between @src and @dst described in @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_block_copy(int i915,
> +		   const intel_ctx_t *ctx,
> +		   const struct intel_execution_engine2 *e,
> +		   uint64_t ahnd,
> +		   const struct blt_copy_data *blt,
> +		   const struct blt_block_copy_data_ext *ext)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	struct gen12_block_copy_data data = {};
> +	struct gen12_block_copy_data_ext dext = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	uint32_t *bb;
> +	int i, ret;
> +
> +	igt_assert_f(ahnd, "block-copy supports softpin only\n");
> +	igt_assert_f(blt, "block-copy requires data to do blit\n");
> +
> +	alignment = gem_detect_safe_alignment(i915);
> +	src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> +	if (__special_mode(blt) == SM_FULL_RESOLVE)
> +		dst_offset = src_offset;
> +	else
> +		dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
> +
> +	fill_data(&data, blt, src_offset, dst_offset, ext);
> +
> +	i = sizeof(data) / sizeof(uint32_t);
> +	bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
> +				       PROT_READ | PROT_WRITE);
> +	memcpy(bb, &data, sizeof(data));
> +
> +	if (ext) {
> +		fill_data_ext(&dext, ext);
> +		memcpy(bb + i, &dext, sizeof(dext));
> +		i += sizeof(dext) / sizeof(uint32_t);
> +	}
> +	bb[i++] = MI_BATCH_BUFFER_END;
> +
> +	if (blt->print_bb) {
> +		igt_info("[BLOCK COPY]\n");
> +		igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
> +			 (long long) src_offset, (long long) dst_offset,
> +			 (long long) bb_offset);
> +
> +		dump_bb_cmd(&data);
> +		if (ext)
> +			dump_bb_ext(&dext);
> +	}
> +
> +	munmap(bb, blt->bb.size);
> +
> +	obj[0].offset = CANONICAL(dst_offset);
> +	obj[1].offset = CANONICAL(src_offset);
> +	obj[2].offset = CANONICAL(bb_offset);
> +	obj[0].handle = blt->dst.handle;
> +	obj[1].handle = blt->src.handle;
> +	obj[2].handle = blt->bb.handle;
> +	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	execbuf.buffer_count = 3;
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.rsvd1 = ctx ? ctx->id : 0;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	ret = __gem_execbuf(i915, &execbuf);
> +
> +	return ret;
> +}
> +
> +static uint16_t __ccs_size(const struct blt_ctrl_surf_copy_data *surf)
> +{
> +	uint32_t src_size, dst_size;
> +
> +	src_size = surf->src.access_type == DIRECT_ACCESS ?
> +				surf->src.size : surf->src.size / CCS_RATIO;
> +
> +	dst_size = surf->dst.access_type == DIRECT_ACCESS ?
> +				surf->dst.size : surf->dst.size / CCS_RATIO;
> +
> +	igt_assert_f(src_size <= dst_size, "dst size must be >= src size for CCS copy\n");
> +
> +	return src_size;
> +}
> +
> +struct gen12_ctrl_surf_copy_data {
> +	struct {
> +		uint32_t length:			BITRANGE(0, 7);
> +		uint32_t size_of_ctrl_copy:		BITRANGE(8, 17);
> +		uint32_t rsvd0:				BITRANGE(18, 19);
> +		uint32_t dst_access_type:		BITRANGE(20, 20);
> +		uint32_t src_access_type:		BITRANGE(21, 21);
> +		uint32_t opcode:			BITRANGE(22, 28);
> +		uint32_t client:			BITRANGE(29, 31);
> +	} dw00;
> +
> +	struct {
> +		uint32_t src_address_lo;
> +	} dw01;
> +
> +	struct {
> +		uint32_t src_address_hi:		BITRANGE(0, 24);
> +		uint32_t src_mocs:			BITRANGE(25, 31);
> +	} dw02;
> +
> +	struct {
> +		uint32_t dst_address_lo;
> +	} dw03;
> +
> +	struct {
> +		uint32_t dst_address_hi:		BITRANGE(0, 24);
> +		uint32_t dst_mocs:			BITRANGE(25, 31);
> +	} dw04;
> +};
> +
> +static void dump_bb_surf_ctrl_cmd(const struct gen12_ctrl_surf_copy_data *data)
> +{
> +	uint32_t *cmd = (uint32_t *) data;
> +
> +	igt_info("details:\n");
> +	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, "
> +		 "src/dst access type: <%d, %d>, size of ctrl copy: %u, length: %d>\n",
> +		 cmd[0],
> +		 data->dw00.client, data->dw00.opcode,
> +		 data->dw00.src_access_type, data->dw00.dst_access_type,
> +		 data->dw00.size_of_ctrl_copy, data->dw00.length);
> +	igt_info(" dw01: [%08x] src offset lo (0x%x)\n",
> +		 cmd[1], data->dw01.src_address_lo);
> +	igt_info(" dw02: [%08x] src offset hi (0x%x), src mocs: %u\n",
> +		 cmd[2], data->dw02.src_address_hi, data->dw02.src_mocs);
> +	igt_info(" dw03: [%08x] dst offset lo (0x%x)\n",
> +		 cmd[3], data->dw03.dst_address_lo);
> +	igt_info(" dw04: [%08x] dst offset hi (0x%x), src mocs: %u\n",
> +		 cmd[4], data->dw04.dst_address_hi, data->dw04.dst_mocs);
> +}
> +
> +/**
> + * blt_ctrl_surf_copy:
> + * @i915: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @surf: blitter data for ctrl-surf-copy
> + *
> + * Function does ctrl-surf-copy blit between @src and @dst described in
> + * @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_ctrl_surf_copy(int i915,
> +		       const intel_ctx_t *ctx,
> +		       const struct intel_execution_engine2 *e,
> +		       uint64_t ahnd,
> +		       const struct blt_ctrl_surf_copy_data *surf)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	struct gen12_ctrl_surf_copy_data data = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	uint32_t *bb;
> +	int i;
> +
> +	igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n");
> +	igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n");
> +
> +	alignment = max_t(uint64_t, gem_detect_safe_alignment(i915), 1ull << 16);
> +
> +	data.dw00.client = 0x2;
> +	data.dw00.opcode = 0x48;
> +	data.dw00.src_access_type = surf->src.access_type;
> +	data.dw00.dst_access_type = surf->dst.access_type;
> +
> +	/* Ensure dst has size capable to keep src ccs aux */
> +	data.dw00.size_of_ctrl_copy = __ccs_size(surf) / CCS_RATIO - 1;
> +	data.dw00.length = 0x3;
> +
> +	src_offset = get_offset(ahnd, surf->src.handle, surf->src.size,
> +				alignment);
> +	dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size,
> +				alignment);
> +	bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size,
> +			       alignment);
> +
> +	data.dw01.src_address_lo = src_offset;
> +	data.dw02.src_address_hi = src_offset >> 32;
> +	data.dw02.src_mocs = surf->src.mocs;
> +
> +	data.dw03.dst_address_lo = dst_offset;
> +	data.dw04.dst_address_hi = dst_offset >> 32;
> +	data.dw04.dst_mocs = surf->dst.mocs;
> +
> +	i = sizeof(data) / sizeof(uint32_t);
> +	bb = gem_mmap__device_coherent(i915, surf->bb.handle, 0, surf->bb.size,
> +				       PROT_READ | PROT_WRITE);
> +	memcpy(bb, &data, sizeof(data));
> +	bb[i++] = MI_BATCH_BUFFER_END;
> +
> +	if (surf->print_bb) {
> +		igt_info("BB [CTRL SURF]:\n");
> +		igt_info("src offset: %llx, dst offset: %llx, bb offset: %llx\n",
> +			 (long long) src_offset, (long long) dst_offset,
> +			 (long long) bb_offset);
> +
> +		dump_bb_surf_ctrl_cmd(&data);
> +	}
> +	munmap(bb, surf->bb.size);
> +
> +	obj[0].offset = CANONICAL(dst_offset);
> +	obj[1].offset = CANONICAL(src_offset);
> +	obj[2].offset = CANONICAL(bb_offset);
> +	obj[0].handle = surf->dst.handle;
> +	obj[1].handle = surf->src.handle;
> +	obj[2].handle = surf->bb.handle;
> +	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	execbuf.buffer_count = 3;
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	execbuf.rsvd1 = ctx ? ctx->id : 0;
> +	gem_execbuf(i915, &execbuf);
> +	put_offset(ahnd, surf->dst.handle);
> +	put_offset(ahnd, surf->src.handle);
> +	put_offset(ahnd, surf->bb.handle);
> +
> +	return 0;
> +}
> +
> +struct gen12_fast_copy_data {
> +	struct {
> +		uint32_t length:			BITRANGE(0, 7);
> +		uint32_t rsvd1:				BITRANGE(8, 12);
> +		uint32_t dst_tiling:			BITRANGE(13, 14);
> +		uint32_t rsvd0:				BITRANGE(15, 19);
> +		uint32_t src_tiling:			BITRANGE(20, 21);
> +		uint32_t opcode:			BITRANGE(22, 28);
> +		uint32_t client:			BITRANGE(29, 31);
> +	} dw00;
> +
> +	struct {
> +		uint32_t dst_pitch:			BITRANGE(0, 15);
> +		uint32_t rsvd1:				BITRANGE(16, 23);
> +		uint32_t color_depth:			BITRANGE(24, 26);
> +		uint32_t rsvd0:				BITRANGE(27, 27);
> +		uint32_t dst_memory:			BITRANGE(28, 28);
> +		uint32_t src_memory:			BITRANGE(29, 29);
> +		uint32_t dst_type_y:			BITRANGE(30, 30);
> +		uint32_t src_type_y:			BITRANGE(31, 31);
> +	} dw01;
> +
> +	struct {
> +		int32_t dst_x1:				BITRANGE(0, 15);
> +		int32_t dst_y1:				BITRANGE(16, 31);
> +	} dw02;
> +
> +	struct {
> +		int32_t dst_x2:				BITRANGE(0, 15);
> +		int32_t dst_y2:				BITRANGE(16, 31);
> +	} dw03;
> +
> +	struct {
> +		uint32_t dst_address_lo;
> +	} dw04;
> +
> +	struct {
> +		uint32_t dst_address_hi;
> +	} dw05;
> +
> +	struct {
> +		int32_t src_x1:				BITRANGE(0, 15);
> +		int32_t src_y1:				BITRANGE(16, 31);
> +	} dw06;
> +
> +	struct {
> +		uint32_t src_pitch:			BITRANGE(0, 15);
> +		uint32_t rsvd0:				BITRANGE(16, 31);
> +	} dw07;
> +
> +	struct {
> +		uint32_t src_address_lo;
> +	} dw08;
> +
> +	struct {
> +		uint32_t src_address_hi;
> +	} dw09;
> +};
> +
> +static int __fast_tiling(enum blt_tiling tiling)
> +{
> +	switch (tiling) {
> +	case T_LINEAR: return 0;
> +	case T_XMAJOR: return 1;
> +	case T_YMAJOR: return 2;
> +	case T_TILE4:  return 2;
> +	case T_TILE64: return 3;
> +	}
> +	return 0;
> +}
> +
> +static int __fast_color_depth(enum blt_color_depth depth)
> +{
> +	switch (depth) {
> +	case CD_8bit:   return 0;
> +	case CD_16bit:  return 1;
> +	case CD_32bit:  return 3;
> +	case CD_64bit:  return 4;
> +	case CD_96bit:
> +		igt_assert_f(0, "Unsupported depth\n");
> +		break;
> +	case CD_128bit: return 5;
> +	};
> +	return 0;
> +}
> +
> +static void dump_bb_fast_cmd(struct gen12_fast_copy_data *data)
> +{
> +	uint32_t *cmd = (uint32_t *) data;
> +
> +	igt_info("BB details:\n");
> +	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, src tiling: %d, "
> +		 "dst tiling: %d, length: %d>\n",
> +		 cmd[0], data->dw00.client, data->dw00.opcode,
> +		 data->dw00.src_tiling, data->dw00.dst_tiling, data->dw00.length);
> +	igt_info(" dw01: [%08x] dst <pitch: %d, color depth: %d, dst memory: %d, "
> +		 "src memory: %d,\n"
> +		 "\t\t\tdst type tile: %d (0-legacy, 1-tile4),\n"
> +		 "\t\t\tsrc type tile: %d (0-legacy, 1-tile4)>\n",
> +		 cmd[1], data->dw01.dst_pitch, data->dw01.color_depth,
> +		 data->dw01.dst_memory, data->dw01.src_memory,
> +		 data->dw01.dst_type_y, data->dw01.src_type_y);
> +	igt_info(" dw02: [%08x] dst geom <x1: %d, y1: %d>\n",
> +		 cmd[2], data->dw02.dst_x1, data->dw02.dst_y1);
> +	igt_info(" dw03: [%08x]          <x2: %d, y2: %d>\n",
> +		 cmd[3], data->dw03.dst_x2, data->dw03.dst_y2);
> +	igt_info(" dw04: [%08x] dst offset lo (0x%x)\n",
> +		 cmd[4], data->dw04.dst_address_lo);
> +	igt_info(" dw05: [%08x] dst offset hi (0x%x)\n",
> +		 cmd[5], data->dw05.dst_address_hi);
> +	igt_info(" dw06: [%08x] src geom <x1: %d, y1: %d>\n",
> +		 cmd[6], data->dw06.src_x1, data->dw06.src_y1);
> +	igt_info(" dw07: [%08x] src <pitch: %d>\n",
> +		 cmd[7], data->dw07.src_pitch);
> +	igt_info(" dw08: [%08x] src offset lo (0x%x)\n",
> +		 cmd[8], data->dw08.src_address_lo);
> +	igt_info(" dw09: [%08x] src offset hi (0x%x)\n",
> +		 cmd[9], data->dw09.src_address_hi);
> +}
> +
> +/**
> + * blt_fast_copy:
> + * @i915: drm fd
> + * @ctx: intel_ctx_t context
> + * @e: blitter engine for @ctx
> + * @ahnd: allocator handle
> + * @blt: blitter data for fast-copy (same as for block-copy but doesn't use
> + * compression fields).
> + *
> + * Function does fast blit between @src and @dst described in @blt object.
> + *
> + * Returns:
> + * execbuffer status.
> + */
> +int blt_fast_copy(int i915,
> +		  const intel_ctx_t *ctx,
> +		  const struct intel_execution_engine2 *e,
> +		  uint64_t ahnd,
> +		  const struct blt_copy_data *blt)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf = {};
> +	struct drm_i915_gem_exec_object2 obj[3] = {};
> +	struct gen12_fast_copy_data data = {};
> +	uint64_t dst_offset, src_offset, bb_offset, alignment;
> +	uint32_t *bb;
> +	int i, ret;
> +
> +	alignment = gem_detect_safe_alignment(i915);
> +
> +	data.dw00.client = 0x2;
> +	data.dw00.opcode = 0x42;
> +	data.dw00.dst_tiling = __fast_tiling(blt->dst.tiling);
> +	data.dw00.src_tiling = __fast_tiling(blt->src.tiling);
> +	data.dw00.length = 8;
> +
> +	data.dw01.dst_pitch = blt->dst.pitch;
> +	data.dw01.color_depth = __fast_color_depth(blt->color_depth);
> +	data.dw01.dst_memory = __memory_type(blt->dst.region);
> +	data.dw01.src_memory = __memory_type(blt->src.region);
> +	data.dw01.dst_type_y = blt->dst.tiling == T_TILE4 ? 1 : 0;
> +	data.dw01.src_type_y = blt->src.tiling == T_TILE4 ? 1 : 0;
> +
> +	data.dw02.dst_x1 = blt->dst.x1;
> +	data.dw02.dst_y1 = blt->dst.y1;
> +
> +	data.dw03.dst_x2 = blt->dst.x2;
> +	data.dw03.dst_y2 = blt->dst.y2;
> +
> +	src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> +	dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> +	bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
> +
> +	data.dw04.dst_address_lo = dst_offset;
> +	data.dw05.dst_address_hi = dst_offset >> 32;
> +
> +	data.dw06.src_x1 = blt->src.x1;
> +	data.dw06.src_y1 = blt->src.y1;
> +
> +	data.dw07.src_pitch = blt->src.pitch;
> +
> +	data.dw08.src_address_lo = src_offset;
> +	data.dw09.src_address_hi = src_offset >> 32;
> +
> +	i = sizeof(data) / sizeof(uint32_t);
> +	bb = gem_mmap__device_coherent(i915, blt->bb.handle, 0, blt->bb.size,
> +				       PROT_READ | PROT_WRITE);
> +
> +	memcpy(bb, &data, sizeof(data));
> +	bb[i++] = MI_BATCH_BUFFER_END;
> +
> +	if (blt->print_bb) {
> +		igt_info("BB [FAST COPY]\n");
> +		igt_info("blit [src offset: %llx, dst offset: %llx\n",
> +			 (long long) src_offset, (long long) dst_offset);
> +		dump_bb_fast_cmd(&data);
> +	}
> +
> +	munmap(bb, blt->bb.size);
> +
> +	obj[0].offset = CANONICAL(dst_offset);
> +	obj[1].offset = CANONICAL(src_offset);
> +	obj[2].offset = CANONICAL(bb_offset);
> +	obj[0].handle = blt->dst.handle;
> +	obj[1].handle = blt->src.handle;
> +	obj[2].handle = blt->bb.handle;
> +	obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE |
> +		       EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +	execbuf.buffer_count = 3;
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.rsvd1 = ctx ? ctx->id : 0;
> +	execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> +	ret = __gem_execbuf(i915, &execbuf);
> +	put_offset(ahnd, blt->dst.handle);
> +	put_offset(ahnd, blt->src.handle);
> +	put_offset(ahnd, blt->bb.handle);
> +
> +	return ret;
> +}
> +
> +/**
> + * blt_surface_fill_rect:
> + * @i915: drm fd
> + * @obj: blitter copy object (@blt_copy_object) to fill with gradient pattern
> + * @width: width
> + * @height: height
> + *
> + * Function fills surface @width x @height * 24bpp with color gradient
> + * (internally uses ARGB where A == 0xff, see Cairo docs).
> + */
> +void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
> +			   uint32_t width, uint32_t height)
> +{
> +	cairo_surface_t *surface;
> +	cairo_pattern_t *pat;
> +	cairo_t *cr;
> +	void *map = obj->ptr;
> +
> +	if (!map)
> +		map = gem_mmap__device_coherent(i915, obj->handle, 0,
> +						obj->size, PROT_READ | PROT_WRITE);
> +
> +	surface = cairo_image_surface_create_for_data(map,
> +						      CAIRO_FORMAT_RGB24,
> +						      width, height,
> +						      obj->pitch);
> +
> +	cr = cairo_create(surface);
> +
> +	cairo_rectangle(cr, 0, 0, width, height);
> +	cairo_clip(cr);
> +
> +	pat = cairo_pattern_create_mesh();
> +	cairo_mesh_pattern_begin_patch(pat);
> +	cairo_mesh_pattern_move_to(pat, 0, 0);
> +	cairo_mesh_pattern_line_to(pat, width, 0);
> +	cairo_mesh_pattern_line_to(pat, width, height);
> +	cairo_mesh_pattern_line_to(pat, 0, height);
> +	cairo_mesh_pattern_set_corner_color_rgb(pat, 0, 1.0, 0.0, 0.0);
> +	cairo_mesh_pattern_set_corner_color_rgb(pat, 1, 0.0, 1.0, 0.0);
> +	cairo_mesh_pattern_set_corner_color_rgb(pat, 2, 0.0, 0.0, 1.0);
> +	cairo_mesh_pattern_set_corner_color_rgb(pat, 3, 1.0, 1.0, 1.0);
> +	cairo_mesh_pattern_end_patch(pat);
> +
> +	cairo_rectangle(cr, 0, 0, width, height);
> +	cairo_set_source(cr, pat);
> +	cairo_fill(cr);
> +	cairo_pattern_destroy(pat);
> +
> +	cairo_destroy(cr);
> +
> +	cairo_surface_destroy(surface);
> +	if (!obj->ptr)
> +		munmap(map, obj->size);
> +}
> +
> +/**
> + * blt_surface_info:
> + * @info: information header
> + * @obj: blitter copy object (@blt_copy_object) to print surface info
> + */
> +void blt_surface_info(const char *info, const struct blt_copy_object *obj)
> +{
> +	igt_info("[%s]\n", info);
> +	igt_info("surface <handle: %u, size: %llx, region: %x, mocs: %x>\n",
> +		 obj->handle, (long long) obj->size, obj->region, obj->mocs);
> +	igt_info("        <tiling: %s, compression: %u, compression type: %d>\n",
> +		 blt_tiling_name(obj->tiling), obj->compression, obj->compression_type);
> +	igt_info("        <pitch: %u, offset [x: %u, y: %u] geom [<%d,%d> <%d,%d>]>\n",
> +		 obj->pitch, obj->x_offset, obj->y_offset,
> +		 obj->x1, obj->y1, obj->x2, obj->y2);
> +}
> +
> +/**
> + * blt_surface_to_png:
> + * @i915: drm fd
> + * @run_id: prefix id to allow grouping files stored from single run
> + * @fileid: file identifier
> + * @obj: blitter copy object (@blt_copy_object) to save to png
> + * @width: width
> + * @height: height
> + *
> + * Function save surface to png file. Assumes ARGB format where A == 0xff.
> + */
> +void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
> +			const struct blt_copy_object *obj,
> +			uint32_t width, uint32_t height)
> +{
> +	cairo_surface_t *surface;
> +	cairo_status_t ret;
> +	uint8_t *map = (uint8_t *) obj->ptr;
> +	int format;
> +	int stride = obj->tiling ? obj->pitch * 4 : obj->pitch;
> +	char filename[FILENAME_MAX];
> +
> +	snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png",
> +		 run_id, fileid, blt_tiling_name(obj->tiling), width, height,
> +		 obj->compression ? "compressed" : "uncompressed");
> +
> +	if (!map)
> +		map = gem_mmap__device_coherent(i915, obj->handle, 0,
> +						obj->size, PROT_READ);
> +	format = CAIRO_FORMAT_RGB24;
> +	surface = cairo_image_surface_create_for_data(map,
> +						      format, width, height,
> +						      stride);
> +	ret = cairo_surface_write_to_png(surface, filename);
> +	if (ret)
> +		igt_info("Cairo ret: %d (%s)\n", ret, cairo_status_to_string(ret));
> +	igt_assert(ret == CAIRO_STATUS_SUCCESS);
> +	cairo_surface_destroy(surface);
> +
> +	if (!obj->ptr)
> +		munmap(map, obj->size);
> +}
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> new file mode 100644
> index 0000000000..e0e8b52bc2
> --- /dev/null
> +++ b/lib/i915/i915_blt.h
> @@ -0,0 +1,196 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +/**
> + * SECTION:i915_blt
> + * @short_description: i915 blitter library
> + * @title: Blitter library
> + * @include: i915_blt.h
> + *
> + * # Introduction
> + *
> + * Gen12+ blitter commands like XY_BLOCK_COPY_BLT are quite long
> + * and if we would like to provide all arguments to function,
> + * list would be long, unreadable and error prone to invalid argument placement.
> + * Providing objects (structs) seems more reasonable and opens some more
> + * opportunities to share some object data across different blitter commands.
> + *
> + * Blitter library supports no-reloc (softpin) mode only (apart of TGL
> + * there's no relocations enabled) thus ahnd is mandatory. Providing NULL ctx
> + * means we use default context with I915_EXEC_BLT as an execution engine.
> + *
> + * Library introduces tiling enum which distinguishes tiling formats regardless
> + * legacy I915_TILING_... definitions. This allows to control fully what tilings
> + * are handled by command and skip/assert ones which are not supported.
> + *
> + * # Supported commands
> + *
> + * - XY_BLOCK_COPY_BLT - (block-copy) TGL/DG1 + DG2+ (ext version)
> + * - XY_FAST_COPY_BLT - (fast-copy)
> + * - XY_CTRL_SURF_COPY_BLT - (ctrl-surf-copy) DG2+
> + *
> + * # Usage details
> + *
> + * For block-copy and fast-copy @blt_copy_object struct is used to collect
> + * data about source and destination objects. It contains handle, region,
> + * size, etc...  which are using for blits. Some fields are not used for
> + * fast-copy copy (like compression) and command which use this exclusively
> + * is annotated in the comment.
> + *
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +
> +#define CCS_RATIO 256
> +
> +enum blt_color_depth {
> +	CD_8bit,
> +	CD_16bit,
> +	CD_32bit,
> +	CD_64bit,
> +	CD_96bit,
> +	CD_128bit,
> +};
> +
> +enum blt_tiling {
> +	T_LINEAR,
> +	T_XMAJOR,
> +	T_YMAJOR,
> +	T_TILE4,
> +	T_TILE64,
> +};
> +
> +enum blt_compression {
> +	COMPRESSION_DISABLED,
> +	COMPRESSION_ENABLED,
> +};
> +
> +enum blt_compression_type {
> +	COMPRESSION_TYPE_3D,
> +	COMPRESSION_TYPE_MEDIA,
> +};
> +
> +/* BC - block-copy */
> +struct blt_copy_object {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +	uint8_t mocs;
> +	enum blt_tiling tiling;
> +	enum blt_compression compression;  /* BC only */
> +	enum blt_compression_type compression_type; /* BC only */
> +	uint32_t pitch;
> +	uint16_t x_offset, y_offset;
> +	int16_t x1, y1, x2, y2;
> +
> +	/* mapping or null */
> +	uint32_t *ptr;
> +};
> +
> +struct blt_copy_batch {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +};
> +
> +/* Common for block-copy and fast-copy */
> +struct blt_copy_data {
> +	int i915;
> +	struct blt_copy_object src;
> +	struct blt_copy_object dst;
> +	struct blt_copy_batch bb;
> +	enum blt_color_depth color_depth;
> +
> +	/* debug stuff */
> +	bool print_bb;
> +};
> +
> +enum blt_surface_type {
> +	SURFACE_TYPE_1D,
> +	SURFACE_TYPE_2D,
> +	SURFACE_TYPE_3D,
> +	SURFACE_TYPE_CUBE,
> +};
> +
> +struct blt_block_copy_object_ext {
> +	uint8_t compression_format;
> +	bool clear_value_enable;
> +	uint64_t clear_address;
> +	uint16_t surface_width;
> +	uint16_t surface_height;
> +	enum blt_surface_type surface_type;
> +	uint16_t surface_qpitch;
> +	uint16_t surface_depth;
> +	uint8_t lod;
> +	uint8_t horizontal_align;
> +	uint8_t vertical_align;
> +	uint8_t mip_tail_start_lod;
> +	bool depth_stencil_resource;
> +	uint16_t array_index;
> +};
> +
> +struct blt_block_copy_data_ext {
> +	struct blt_block_copy_object_ext src;
> +	struct blt_block_copy_object_ext dst;
> +};
> +
> +enum blt_access_type {
> +	INDIRECT_ACCESS,
> +	DIRECT_ACCESS,
> +};
> +
> +struct blt_ctrl_surf_copy_object {
> +	uint32_t handle;
> +	uint32_t region;
> +	uint64_t size;
> +	uint8_t mocs;
> +	enum blt_access_type access_type;
> +};
> +
> +struct blt_ctrl_surf_copy_data {
> +	int i915;
> +	struct blt_ctrl_surf_copy_object src;
> +	struct blt_ctrl_surf_copy_object dst;
> +	struct blt_copy_batch bb;
> +
> +	/* debug stuff */
> +	bool print_bb;
> +};
> +
> +bool blt_supports_compression(int i915);
> +bool blt_supports_tiling(int i915, enum blt_tiling tiling);
> +const char *blt_tiling_name(enum blt_tiling tiling);
> +
> +int blt_block_copy(int i915,
> +		   const intel_ctx_t *ctx,
> +		   const struct intel_execution_engine2 *e,
> +		   uint64_t ahnd,
> +		   const struct blt_copy_data *blt,
> +		   const struct blt_block_copy_data_ext *ext);
> +
> +int blt_ctrl_surf_copy(int i915,
> +		       const intel_ctx_t *ctx,
> +		       const struct intel_execution_engine2 *e,
> +		       uint64_t ahnd,
> +		       const struct blt_ctrl_surf_copy_data *surf);
> +
> +int blt_fast_copy(int i915,
> +		  const intel_ctx_t *ctx,
> +		  const struct intel_execution_engine2 *e,
> +		  uint64_t ahnd,
> +		  const struct blt_copy_data *blt);
> +
> +void blt_surface_info(const char *info,
> +		      const struct blt_copy_object *obj);
> +void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
> +			   uint32_t width, uint32_t height);
> +void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
> +		    const struct blt_copy_object *obj,
> +		    uint32_t width, uint32_t height);
> diff --git a/lib/meson.build b/lib/meson.build
> index a5fe91dc99..6fc1958604 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -12,6 +12,7 @@ lib_sources = [
>  	'i915/gem_vm.c',
>  	'i915/intel_memory_region.c',
>  	'i915/intel_mocs.c',
> +	'i915/i915_blt.c',
>  	'igt_collection.c',
>  	'igt_color_encoding.c',
>  	'igt_debugfs.c',
> -- 
> 2.32.0
> 

Re: [igt-dev] [PATCH i-g-t 3/6] lib/i915: Introduce library intel_mocs

[Zbigniew Kempczyński]

On Fri, Mar 11, 2022 at 12:14:52PM +0100, Kamil Konieczny wrote:
> Hi Zbigniew,
> 
> Dnia 2022-03-10 at 08:15:26 +0100, Zbigniew Kempczyński napisał(a):
> > From: Apoorva Singh <apoorva1.singh@intel.com>
> > 
> > Add new library intel_mocs for mocs settings.
> > 
> > Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Arjun Melkaveri <arjun.melkaveri@intel.com>
> > Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> >  lib/i915/intel_mocs.c | 56 +++++++++++++++++++++++++++++++++++++++++++
> >  lib/i915/intel_mocs.h | 25 +++++++++++++++++++
> >  lib/meson.build       |  1 +
> >  3 files changed, 82 insertions(+)
> >  create mode 100644 lib/i915/intel_mocs.c
> >  create mode 100644 lib/i915/intel_mocs.h
> > 
> > diff --git a/lib/i915/intel_mocs.c b/lib/i915/intel_mocs.c
> > new file mode 100644
> > index 0000000000..63ead1118f
> > --- /dev/null
> > +++ b/lib/i915/intel_mocs.c
> > @@ -0,0 +1,56 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#include "igt.h"
> > +#include "i915/gem.h"
> > +#include "intel_mocs.h"
> > +
> > +static void get_mocs_index(int fd, struct drm_i915_mocs_index *mocs)
> > +{
> > +	uint16_t devid = intel_get_drm_devid(fd);
> > +
> > +	/*
> > +	 * Gen >= 12 onwards don't have a setting for PTE,
> > +	 * so using I915_MOCS_PTE as mocs index may leads to
> > +	 * some undefined MOCS behavior.
> > +	 * This helper function is providing current UC as well
> > +	 * as WB MOCS index based on platform.
> > +	 */
> > +	if (IS_DG1(devid)) {
> > +		mocs->uc_index = DG1_MOCS_UC_IDX;
> > +		mocs->wb_index = DG1_MOCS_WB_IDX;
> > +	} else if (IS_DG2(devid)) {
> > +		mocs->uc_index = DG2_MOCS_UC_IDX;
> > +		mocs->wb_index = DG2_MOCS_WB_IDX;
> > +
> > +	} else if (IS_GEN12(devid)) {
> > +		mocs->uc_index = GEN12_MOCS_UC_IDX;
> > +		mocs->wb_index = GEN12_MOCS_WB_IDX;
> > +	} else {
> > +		mocs->uc_index = I915_MOCS_PTE;
> > +		mocs->wb_index = I915_MOCS_CACHED;
> > +		igt_info("C1\n");
> 
> Remove this or make it igt_debug.

Eh, thanks for spotting that.

> 
> > +	}
> > +}
> > +
> > +/* BitField [6:1] represents index to MOCS Tables
> > + * BitField [0] represents Encryption/Decryption
> > + */
> > +
> > +uint8_t intel_get_wb_mocs(int fd)
> > +{
> > +	struct drm_i915_mocs_index mocs;
> > +
> > +	get_mocs_index(fd, &mocs);
> > +	return mocs.wb_index << 1;
> > +}
> > +
> > +uint8_t intel_get_uc_mocs(int fd)
> > +{
> > +	struct drm_i915_mocs_index mocs;
> > +
> > +	get_mocs_index(fd, &mocs);
> > +	return mocs.uc_index << 1;
> > +}
> > diff --git a/lib/i915/intel_mocs.h b/lib/i915/intel_mocs.h
> > new file mode 100644
> > index 0000000000..c05569f426
> > --- /dev/null
> > +++ b/lib/i915/intel_mocs.h
> > @@ -0,0 +1,25 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#ifndef _INTEL_MOCS_H
> > +#define _INTEL_MOCS_H
> > +
> > +#define DG1_MOCS_UC_IDX			1
> > +#define DG1_MOCS_WB_IDX			5
> > +#define DG2_MOCS_UC_IDX			1
> > +#define DG2_MOCS_WB_IDX			3
> > +#define GEN12_MOCS_UC_IDX			3
> > +#define GEN12_MOCS_WB_IDX			2
> 
> Do we need this here ? Can it be placed in lib implementation
> and hided there ?

Agree, exporting this is not necessary.

> 
> > +#define XY_BLOCK_COPY_BLT_MOCS_SHIFT		21
> > +#define XY_CTRL_SURF_COPY_BLT_MOCS_SHIFT	25
> 
> Same here, there is no uses for this constants. They can stay
> if you can tell they will be used in near future.

Agree.

> 
> > +
> > +struct drm_i915_mocs_index {
> > +	uint8_t uc_index;
> > +	uint8_t wb_index;
> > +};
> > +
> > +uint8_t intel_get_wb_mocs(int fd);
> > +uint8_t intel_get_uc_mocs(int fd);
> 
> These helpers returns uc and wb index, so maybe struct can be
> moved to .c implementation ? So we can keep headers clean. It is
> up to you, I do not insist on changes in header file.

You're right, if we can hide implementation details we should do this.

Will send in v6.

> 
> > +#endif /* _INTEL_MOCS_H */
> > diff --git a/lib/meson.build b/lib/meson.build
> > index 3e43316d1e..a5fe91dc99 100644
> > --- a/lib/meson.build
> > +++ b/lib/meson.build
> > @@ -11,6 +11,7 @@ lib_sources = [
> >  	'i915/gem_mman.c',
> >  	'i915/gem_vm.c',
> >  	'i915/intel_memory_region.c',
> > +	'i915/intel_mocs.c',
> >  	'igt_collection.c',
> >  	'igt_color_encoding.c',
> >  	'igt_debugfs.c',
> > -- 
> > 2.32.0
> > 
> 
> With that fixed you can add my r-b tag,

Ok, will hide implementation and resend with r-b.

Thank you for the review.

--
Zbigniew
 

> 
> Regards,
> Kamil

Re: [igt-dev] [PATCH i-g-t 6/6] tests/gem_ccs: Verify uncompressed and compressed blits

[Kamil Konieczny]

Hi Zbigniew,

Dnia 2022-03-10 at 08:15:29 +0100, Zbigniew Kempczyński napisał(a):
> DG2 and above supports flat-ccs what means object compression lays in
> dedicated part or memory and is directly correlated with object location
-----------------^
s/or/of/

> in physical memory. As no mapping is possible from CPU side to this area
> dedicated blitter command (XY_CTRL_SURF_COPY_BLT) was created to copy
> from/to ccs data.
> 
> Test exercises scenarios:
> 1. block-copy without compression (TGL/DG1)
> 2. block-copy with flat-ccs compression (DG2+) + inplace decompression
> 3. ctrl-surf-copy which verifies copying ccs data to/from flat-ccs area
> 
> v2: set mip tail lod to 0xf to avoid overlap with lod
> v3: address review comments (Kamil) + setting uc_mocs (Ayaz)
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Only one minor nit, see below, with it fixed you can add my r-b.

> ---
>  tests/i915/gem_ccs.c | 487 +++++++++++++++++++++++++++++++++++++++++++
>  tests/meson.build    |   1 +
>  2 files changed, 488 insertions(+)
>  create mode 100644 tests/i915/gem_ccs.c
> 
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> new file mode 100644
> index 0000000000..f4d06f201d
> --- /dev/null
> +++ b/tests/i915/gem_ccs.c
> @@ -0,0 +1,487 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <sys/ioctl.h>
> +#include <sys/time.h>
> +#include <malloc.h>
> +#include "drm.h"
> +#include "igt.h"
> +#include "i915/gem.h"
> +#include "i915/gem_create.h"
> +#include "lib/intel_chipset.h"
> +#include "i915/i915_blt.h"
> +#include "i915/intel_mocs.h"
> +
> +IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression");
> +
> +static struct param {
> +	int compression_format;
> +	int tiling;
> +	bool write_png;
> +	bool print_bb;
> +	bool print_surface_info;
> +	int width;
> +	int height;
> +} param = {
> +	.compression_format = 0,
> +	.tiling = -1,
> +	.write_png = false,
> +	.print_bb = false,
> +	.print_surface_info = false,
> +	.width = 512,
> +	.height = 512,
> +};
> +
> +struct test_config {
> +	bool compression;
> +	bool inplace;
> +	bool surfcopy;
> +};
> +
> +static void set_object(struct blt_copy_object *obj,
> +		       uint32_t handle, uint64_t size, uint32_t region,
> +		       uint8_t mocs, enum blt_tiling tiling,
> +		       enum blt_compression compression,
> +		       enum blt_compression_type compression_type)
> +{
> +	obj->handle = handle;
> +	obj->size = size;
> +	obj->region = region;
> +	obj->mocs = mocs;
> +	obj->tiling = tiling;
> +	obj->compression = compression;
> +	obj->compression_type = compression_type;
> +}
> +
> +static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
> +		     int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> +		     uint16_t x_offset, uint16_t y_offset)
> +{
> +	obj->pitch = pitch;
> +	obj->x1 = x1;
> +	obj->y1 = y1;
> +	obj->x2 = x2;
> +	obj->y2 = y2;
> +	obj->x_offset = x_offset;
> +	obj->y_offset = y_offset;
> +}
> +
> +static void set_batch(struct blt_copy_batch *batch,
> +		      uint32_t handle, uint64_t size, uint32_t region)
> +{
> +	batch->handle = handle;
> +	batch->size = size;
> +	batch->region = region;
> +}
> +
> +static void set_object_ext(struct blt_block_copy_object_ext *obj,
> +			   uint8_t compression_format,
> +			   uint16_t surface_width, uint16_t surface_height,
> +			   enum blt_surface_type surface_type)
> +{
> +	obj->compression_format = compression_format;
> +	obj->surface_width = surface_width;
> +	obj->surface_height = surface_height;
> +	obj->surface_type = surface_type;
> +
> +	/* Ensure mip tail won't overlap lod */
> +	obj->mip_tail_start_lod = 0xf;
> +}
> +
> +static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
> +			    uint32_t handle, uint32_t region, uint64_t size,
> +			    uint8_t mocs, enum blt_access_type access_type)
> +{
> +	obj->handle = handle;
> +	obj->region = region;
> +	obj->size = size;
> +	obj->mocs = mocs;
> +	obj->access_type = access_type;
> +}
> +
> +static struct blt_copy_object *
> +create_object(int i915, uint32_t region,
> +	      uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
> +	      enum blt_tiling tiling,
> +	      enum blt_compression compression,
> +	      enum blt_compression_type compression_type,
> +	      bool create_mapping)
> +{
> +	struct blt_copy_object *obj;
> +	uint64_t size = width * height * bpp / 8;
> +	uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
> +	uint32_t handle;
> +
> +	obj = calloc(1, sizeof(*obj));
> +
> +	obj->size = size;
> +	igt_assert(__gem_create_in_memory_regions(i915, &handle,
> +						  &size, region) == 0);
> +
> +	set_object(obj, handle, size, region, mocs, tiling,
> +		   compression, compression_type);
> +	set_geom(obj, stride, 0, 0, width, height, 0, 0);
> +
> +	if (create_mapping)
> +		obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
> +						     PROT_READ | PROT_WRITE);
> +
> +	return obj;
> +}
> +
> +static void destroy_object(int i915, struct blt_copy_object *obj)
> +{
> +	if (obj->ptr)
> +		munmap(obj->ptr, obj->size);
> +
> +	gem_close(i915, obj->handle);
> +}
> +
> +static void set_blt_object(struct blt_copy_object *obj,
> +			   const struct blt_copy_object *orig)
> +{
> +	memcpy(obj, orig, sizeof(*obj));
> +}
> +
> +#define PRINT_SURFACE_INFO(name, obj) do { \
> +	if (param.print_surface_info) \
> +		blt_surface_info((name), (obj)); } while (0)
> +
> +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
> +	if (param.write_png) \
> +		blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
> +
> +static void surf_copy(int i915,
> +		      const intel_ctx_t *ctx,
> +		      const struct intel_execution_engine2 *e,
> +		      uint64_t ahnd,
> +		      const struct blt_copy_object *src,
> +		      const struct blt_copy_object *mid,
> +		      const struct blt_copy_object *dst,
> +		      int run_id)
> +{
> +	struct blt_copy_data blt = {};
> +	struct blt_block_copy_data_ext ext = {};
> +	struct blt_ctrl_surf_copy_data surf = {};
> +	uint32_t bb, ccs, *ccsmap;
> +	uint64_t bb_size = 4096;
> +	uint64_t ccssize = mid->size / CCS_RATIO;
> +	uint32_t *ccscopy;
> +	uint8_t uc_mocs = intel_get_uc_mocs(i915);
> +	int result;
> +
> +	igt_assert(mid->compression);
> +	ccscopy = (uint32_t *) malloc(ccssize);
> +	bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
> +	ccs = gem_create(i915, ccssize);
> +
> +	surf.i915 = i915;
> +	surf.print_bb = param.print_bb;
> +	set_surf_object(&surf.src, mid->handle, mid->region, mid->size,
> +			uc_mocs, INDIRECT_ACCESS);
> +	set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
> +			uc_mocs, DIRECT_ACCESS);
> +	set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
> +	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
> +	gem_sync(i915, surf.dst.handle);
> +
> +	ccsmap = gem_mmap__device_coherent(i915, ccs, 0, surf.dst.size,
> +					   PROT_READ | PROT_WRITE);
> +	memcpy(ccscopy, ccsmap, ccssize);
> +
> +	/* corrupt ccs */
> +	for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++)
> +		ccsmap[i] = i;
> +	set_surf_object(&surf.src, ccs, REGION_SMEM, ccssize,
> +			uc_mocs, DIRECT_ACCESS);
> +	set_surf_object(&surf.dst, mid->handle, mid->region, mid->size,
> +			uc_mocs, INDIRECT_ACCESS);
> +	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
> +
> +	memset(&blt, 0, sizeof(blt));
> +	blt.color_depth = CD_32bit;
> +	blt.print_bb = param.print_bb;
> +	set_blt_object(&blt.src, mid);
> +	set_blt_object(&blt.dst, dst);
> +	set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
> +	set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
> +	bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
> +	set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
> +	blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
> +	gem_sync(i915, blt.dst.handle);
> +	WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
> +	result = memcmp(src->ptr, dst->ptr, src->size);
> +	igt_assert(result != 0);
> +
> +	/* retrieve back ccs */
> +	memcpy(ccsmap, ccscopy, ccssize);
> +	blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
> +
> +	blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
> +	gem_sync(i915, blt.dst.handle);
> +	WRITE_PNG(i915, run_id, "corrected", &blt.dst, dst->x2, dst->y2);
> +	result = memcmp(src->ptr, dst->ptr, src->size);
> +	igt_assert(result == 0);
> +
> +	munmap(ccsmap, ccssize);
> +	gem_close(i915, ccs);
> +}
> +
> +static void block_copy(int i915,
> +		       const intel_ctx_t *ctx,
> +		       const struct intel_execution_engine2 *e,
> +		       uint32_t region1, uint32_t region2,
> +		       enum blt_tiling mid_tiling, bool compression,
> +		       bool inplace,
> +		       bool surfcopy)
> +{
> +	struct blt_copy_data blt = {};
> +	struct blt_block_copy_data_ext ext = {}, *pext = &ext;
> +	struct blt_copy_object *src, *mid, *dst;
> +	const uint32_t bpp = 32;
> +	uint64_t bb_size = 4096;
> +	uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
> +						  INTEL_ALLOCATOR_SIMPLE,
> +						  ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> +	uint32_t run_id = mid_tiling;
> +	uint32_t mid_region = region2, bb;
> +	uint32_t width = param.width, height = param.height;
> +	enum blt_compression mid_compression = compression;
> +	int mid_compression_format = param.compression_format;
> +	enum blt_compression_type comp_type = COMPRESSION_TYPE_3D;
> +	uint8_t uc_mocs = intel_get_uc_mocs(i915);
> +	int result;
> +
> +	igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
> +
> +	if (!blt_supports_compression(i915))
> +		pext = NULL;
> +
> +	src = create_object(i915, region1, width, height, bpp, uc_mocs,
> +			    T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> +	mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
> +			    mid_tiling, mid_compression, comp_type, true);
> +	dst = create_object(i915, region1, width, height, bpp, uc_mocs,
> +			    T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> +	igt_assert(src->size == dst->size);
> +	PRINT_SURFACE_INFO("src", src);
> +	PRINT_SURFACE_INFO("mid", mid);
> +	PRINT_SURFACE_INFO("dst", dst);
> +
> +	blt_surface_fill_rect(i915, src, width, height);
> +	WRITE_PNG(i915, run_id, "src", src, width, height);
> +
> +	memset(&blt, 0, sizeof(blt));
> +	blt.color_depth = CD_32bit;
> +	blt.print_bb = param.print_bb;
> +	set_blt_object(&blt.src, src);
> +	set_blt_object(&blt.dst, mid);
> +	set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
> +	set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
> +	set_batch(&blt.bb, bb, bb_size, region1);
> +
> +	blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> +	gem_sync(i915, mid->handle);
> +
> +	/* We expect mid != src if there's compression */
> +	if (mid->compression)
> +		igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0);
> +
> +	WRITE_PNG(i915, run_id, "src", &blt.src, width, height);
> +	WRITE_PNG(i915, run_id, "mid", &blt.dst, width, height);
> +
> +	if (surfcopy && pext)
> +		surf_copy(i915, ctx, e, ahnd, src, mid, dst, run_id);
> +
> +	memset(&blt, 0, sizeof(blt));
> +	blt.color_depth = CD_32bit;
> +	blt.print_bb = param.print_bb;
> +	set_blt_object(&blt.src, mid);
> +	set_blt_object(&blt.dst, dst);
> +	set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
> +	set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
> +	if (inplace) {
> +		set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
> +			   T_LINEAR, COMPRESSION_DISABLED, comp_type);
> +		blt.dst.ptr = mid->ptr;
> +	}
> +
> +	set_batch(&blt.bb, bb, bb_size, region1);
> +	blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> +	gem_sync(i915, blt.dst.handle);
> +	WRITE_PNG(i915, run_id, "dst", &blt.dst, width, height);
> +
> +	result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> +	destroy_object(i915, src);
> +	destroy_object(i915, mid);
> +	destroy_object(i915, dst);
> +	gem_close(i915, bb);
> +	put_ahnd(ahnd);
> +
> +	igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +static void block_copy_test(int i915,
> +			    const struct test_config *config,
> +			    const intel_ctx_t *ctx,
> +			    struct igt_collection *set)
> +{
> +	struct igt_collection *regions;
> +	const struct intel_execution_engine2 *e;
> +
> +	if (config->compression && !blt_supports_compression(i915))
> +		return;
> +
> +	if (config->inplace && !config->compression)
> +		return;
> +
> +	for (int tiling = T_LINEAR; tiling <= T_TILE64; tiling++) {
> +		if (!blt_supports_tiling(i915, tiling) ||
> +		    (param.tiling >= 0 && param.tiling != tiling))
> +			continue;
> +
> +		for_each_ctx_engine(i915, ctx, e) {
> +			if (!gem_engine_can_block_copy(i915, e))
> +				continue;
> +
> +			for_each_variation_r(regions, 2, set) {
> +				uint32_t region1, region2;
> +				char *regtxt;
> +
> +				region1 = igt_collection_get_value(regions, 0);
> +				region2 = igt_collection_get_value(regions, 1);
> +
> +				/* Compressed surface must be in device memory */
> +				if (config->compression && !IS_DEVICE_MEMORY_REGION(region2))
> +					continue;
> +
> +				regtxt = memregion_dynamic_subtest_name(regions);
> +				igt_dynamic_f("%s-%s-compfmt%d-%s",
> +					      blt_tiling_name(tiling),
> +					      config->compression ?
> +						      "compressed" : "uncompressed",
> +					      param.compression_format, regtxt) {
> +					block_copy(i915, ctx, e,
> +						   region1, region2,
> +						   tiling,
> +						   config->compression,
> +						   config->inplace,
> +						   config->surfcopy);
> +				}
> +				free(regtxt);
> +			}
> +		}
> +	}
> +}
> +
> +static int opt_handler(int opt, int opt_index, void *data)
> +{
> +	switch (opt) {
> +	case 'b':
> +		param.print_bb = true;
> +		igt_debug("Print bb: %d\n", param.print_bb);
> +		break;
> +	case 'f':
> +		param.compression_format = atoi(optarg);
> +		igt_debug("Compression format: %d\n", param.compression_format);
> +		igt_assert((param.compression_format & ~0x1f) == 0);
> +		break;
> +	case 'p':
> +		param.write_png = true;
> +		igt_debug("Write png: %d\n", param.write_png);
> +		break;
> +	case 's':
> +		param.print_surface_info = true;
> +		igt_debug("Print surface info: %d\n", param.print_surface_info);
> +		break;
> +	case 't':
> +		param.tiling = atoi(optarg);
> +		igt_debug("Tiling: %d\n", param.tiling);
> +		break;
> +	case 'W':
> +		param.width = atoi(optarg);
> +		igt_debug("Width: %d\n", param.width);
> +		break;
> +	case 'H':
> +		param.height = atoi(optarg);
> +		igt_debug("Height: %d\n", param.height);
> +		break;
> +	default:
> +		return IGT_OPT_HANDLER_ERROR;
> +	}
> +
> +	return IGT_OPT_HANDLER_SUCCESS;
> +}
> +
> +const char *help_str =
> +	"  -b\tPrint bb\n"
> +	"  -f\tCompression format (0-31)"
----------------------------------------^
Put '\n' at end of string.

> +	"  -p\tWrite PNG\n"
> +	"  -s\tPrint surface info\n"
> +	"  -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n"
> +	"  -W\tWidth (default 512)\n"
> +	"  -H\tHeight (default 512)"
> +	;
> +
> +igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> +{
> +	struct drm_i915_query_memory_regions *query_info;
> +	struct igt_collection *set;
> +	const intel_ctx_t *ctx;
> +	int i915;
> +	igt_hang_t hang;
> +
> +	igt_fixture {
> +		i915 = drm_open_driver(DRIVER_INTEL);
> +		igt_require_gem(i915);
> +		igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
> +
> +		query_info = gem_get_query_memory_regions(i915);
> +		igt_require(query_info);
> +
> +		set = get_memory_region_set(query_info,
> +					    I915_SYSTEM_MEMORY,
> +					    I915_DEVICE_MEMORY);
> +		ctx = intel_ctx_create_all_physical(i915);
> +		hang = igt_allow_hang(i915, ctx->id, 0);
> +	}
> +
> +	igt_describe("Check block-copy uncompressed blit");
> +	igt_subtest_with_dynamic("block-copy-uncompressed") {
> +		struct test_config config = {};
> +
> +		block_copy_test(i915, &config, ctx, set);
> +	}
> +
> +	igt_describe("Check block-copy flatccs compressed blit");
> +	igt_subtest_with_dynamic("block-copy-compressed") {
> +		struct test_config config = { .compression = true };
> +
> +		block_copy_test(i915, &config, ctx, set);
> +	}
> +
> +	igt_describe("Check block-copy flatccs inplace decompression blit");
> +	igt_subtest_with_dynamic("block-copy-inplace") {
> +		struct test_config config = { .compression = true,
> +					      .inplace = true };
> +
> +		block_copy_test(i915, &config, ctx, set);
> +	}
> +
> +	igt_describe("Check flatccs data can be copied from/to surface");
> +	igt_subtest_with_dynamic("ctrl-surf-copy") {
> +		struct test_config config = { .compression = true,
> +					      .surfcopy = true };
> +
> +		block_copy_test(i915, &config, ctx, set);
> +	}
> +
> +	igt_fixture {
> +		igt_disallow_hang(i915, hang);
> +		close(i915);
> +	}
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index 3dbba7a1b7..3af4576f4a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -109,6 +109,7 @@ i915_progs = [
>  	'gem_blits',
>  	'gem_busy',
>  	'gem_caching',
> +	'gem_ccs',
>  	'gem_close',
>  	'gem_close_race',
>  	'gem_concurrent_blit',
> -- 
> 2.32.0
> 
Regrads,
Kamil

Re: [igt-dev] ✗ Fi.CI.IGT: failure for Add i915 blt library + gem_ccs test (rev7)

[Vudum, Lakshminarayana]

All three tests are new and they are not yet in CI bug log to create a filter.

Lakshmi.

-----Original Message-----
From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com> 
Sent: Thursday, March 10, 2022 11:23 PM
To: igt-dev@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for Add i915 blt library + gem_ccs test (rev7)

On Thu, Mar 10, 2022 at 12:34:45PM +0000, Patchwork wrote:
>    Patch Details
> 
>    Series:  Add i915 blt library + gem_ccs test (rev7)                     
>    URL:     https://patchwork.freedesktop.org/series/99925/                
>    State:   failure                                                        
>    Details: 
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html
> 
>          CI Bug Log - changes from CI_DRM_11347_full -> 
> IGTPW_6769_full
> 
> Summary
> 
>    FAILURE
> 
>    Serious unknown changes coming with IGTPW_6769_full absolutely need to be
>    verified manually.
> 
>    If you think the reported changes have nothing to do with the changes
>    introduced in IGTPW_6769_full, please notify your bug team to allow them
>    to document this new failure mode, which will reduce false positives in
>    CI.
> 
>    External URL:
>    https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/index.html
> 
> Participating hosts (13 -> 7)
> 
>    Missing (6): pig-kbl-iris shard-tglu pig-glk-j5005 pig-skl-6260u shard-rkl
>    shard-dg1
> 
> Possible new issues
> 
>    Here are the unknown changes that may have been introduced in
>    IGTPW_6769_full:
> 
>   IGT changes
> 
>     Possible regressions
> 
>      * igt@api_intel_allocator@fork-simple-stress:
> 
>           * shard-tglb: NOTRUN -> INCOMPLETE

This is strange, igt@api_intel_allocator@fork-simple-stress-signal is executing whereas above not:

https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6769/shards-all.html?testfilter=api_intel_allocator@fork-simple

Anyway series haven't touch above test so it is unrelated to above incompletion.

>      * {igt@gem_ccs@block-copy-compressed} (NEW):
> 
>           * shard-tglb: NOTRUN -> SKIP +1 similar issue
>      * {igt@gem_ccs@block-copy-uncompressed} (NEW):
> 
>           * shard-iclb: NOTRUN -> SKIP +2 similar issues

For those generations skip is expected.

--
Zbigniew

> 
>     Suppressed
> 
>    The following results come from untrusted machines, tests, or statuses.
>    They do not affect the overall result.
> 
>      * {igt@kms_setmode@basic@pipe-b-vga-1}:
>           * shard-snb: FAIL ([i915#31]) -> FAIL
> 
> New tests
> 
>    New tests have been introduced between CI_DRM_11347_full and
>    IGTPW_6769_full:
> 
>   New IGT tests (5)
> 
>      * igt@api_intel_allocator@gem-pool:
> 
>           * Statuses : 6 pass(s)
>           * Exec time: [0.00, 0.02] s
>      * igt@gem_ccs@block-copy-compressed:
> 
>           * Statuses : 6 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@block-copy-inplace:
> 
>           * Statuses : 3 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@block-copy-uncompressed:
> 
>           * Statuses : 4 skip(s)
>           * Exec time: [0.0] s
>      * igt@gem_ccs@ctrl-surf-copy:
> 
>           * Statuses : 6 skip(s)
>           * Exec time: [0.0] s
> 
> Known issues
> 
>    Here are the changes found in IGTPW_6769_full that come from known issues:
> 
>   IGT changes
> 
>     Issues hit
> 
>      * igt@feature_discovery@display-4x:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271]) +209 similar issues
>      * igt@gem_ctx_persistence@legacy-engines-mixed-process:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [i915#1099])
>      * igt@gem_ctx_sseu@invalid-args:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#280])
>      * igt@gem_eio@kms:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#232])
>      * igt@gem_exec_balancer@parallel:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#4525])
>      * igt@gem_exec_balancer@parallel-contexts:
> 
>           * shard-tglb: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>           * shard-kbl: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>           * shard-iclb: NOTRUN -> DMESG-WARN ([i915#5076])
> 
>      * igt@gem_exec_fair@basic-none-share@rcs0:
> 
>           * shard-iclb: PASS -> FAIL ([i915#2842])
>      * igt@gem_exec_fair@basic-none-solo@rcs0:
> 
>           * shard-kbl: NOTRUN -> FAIL ([i915#2842]) +2 similar issues
> 
>           * shard-glk: NOTRUN -> FAIL ([i915#2842])
> 
>           * shard-iclb: NOTRUN -> FAIL ([i915#2842])
> 
>      * igt@gem_exec_fair@basic-none@vcs0:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#2842]) +5 similar issues
>      * igt@gem_exec_fair@basic-pace-share@rcs0:
> 
>           * shard-glk: PASS -> FAIL ([i915#2842]) +1 similar issue
>      * igt@gem_exec_params@no-vebox:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109283] / [i915#4877])
>      * igt@gem_lmem_swapping@heavy-verify-multi:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +2 similar
>             issues
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
> 
>      * igt@gem_lmem_swapping@random:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +2 similar
>             issues
>      * igt@gem_lmem_swapping@random-engines:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4613]) +2 similar issues
>      * igt@gem_pxp@reject-modify-context-protection-on:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4270]) +2 similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#4270]) +1 similar issue
> 
>      * igt@gem_softpin@noreloc-s3:
> 
>           * shard-snb: PASS -> INCOMPLETE ([i915#5230])
>      * igt@gem_userptr_blits@create-destroy-unsync:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3297])
>      * igt@gen3_render_tiledy_blits:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109289]) +5 similar issues
>      * igt@gen9_exec_parse@allowed-all:
> 
>           * shard-glk: PASS -> DMESG-WARN ([i915#1436] / [i915#716])
>      * igt@gen9_exec_parse@allowed-single:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2527] / [i915#2856]) +3 similar
>             issues
>      * igt@gen9_exec_parse@bb-start-far:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2856]) +2 similar issues
>      * igt@i915_pm_dc@dc6-psr:
> 
>           * shard-iclb: NOTRUN -> FAIL ([i915#454])
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#454])
> 
>      * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111644] / [i915#1397] /
>             [i915#2411])
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110892])
> 
>      * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271]) +119 similar issues
>      * igt@i915_pm_rpm@pc8-residency:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109293] / [fdo#109506])
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109506] / [i915#2411])
> 
>      * igt@i915_pm_sseu@full-enable:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#4387])
>      * igt@kms_atomic_transition@plane-all-modeset-transition:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1769])
>      * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5286]) +1 similar issue
>      * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5286]) +6 similar issues
>      * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614])
>      * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111614]) +1 similar issue
>      * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +1 similar
>             issue
>      * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +3 similar
>             issues
>      * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
> 
>           * shard-glk: PASS -> DMESG-WARN ([i915#118])
>      * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3777])
>      * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111615]) +3 similar issues
>      * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#110723]) +1 similar issue
>      * igt@kms_big_joiner@invalid-modeset:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2705])
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2705])
> 
>      * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +9 similar
>             issues
>      * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +10
>             similar issues
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3689] / [i915#3886]) +3 similar
>             issues
> 
>      * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_ccs:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3689]) +7 similar issues
>      * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#111615] / [i915#3689]) +3
>             similar issues
>      * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +6 similar
>             issues
>      * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#3886]) +8
>             similar issues
>      * igt@kms_cdclk@plane-scaling:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3742])
>      * igt@kms_chamelium@dp-mode-timings:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +14
>             similar issues
>      * igt@kms_chamelium@hdmi-hpd-for-each-pipe:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +3
>             similar issues
>      * igt@kms_chamelium@vga-hpd-without-ddc:
> 
>           * shard-snb: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +3
>             similar issues
>      * igt@kms_color@pipe-d-gamma:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#1149])
>      * igt@kms_color_chamelium@pipe-a-degamma:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +12
>             similar issues
>      * igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +5
>             similar issues
>      * igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109284] /
>             [fdo#111827])
>      * igt@kms_color_chamelium@pipe-d-ctm-max:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +10
>             similar issues
>      * igt@kms_content_protection@content_type_change:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109300] / [fdo#111066]) +1
>             similar issue
>      * igt@kms_content_protection@dp-mst-lic-type-1:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3116])
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3116] / [i915#3299])
> 
>      * igt@kms_content_protection@srm:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1063]) +1 similar issue
> 
>           * shard-kbl: NOTRUN -> TIMEOUT ([i915#1319])
> 
>           * shard-apl: NOTRUN -> TIMEOUT ([i915#1319])
> 
>      * igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109279]) +1
>             similar issue
>      * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109279] / [i915#3359]) +3
>             similar issues
>      * igt@kms_cursor_crc@pipe-d-cursor-512x170-rapid-movement:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3359]) +6 similar issues
>      * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109274] / [fdo#111825]) +12
>             similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109274] / [fdo#109278]) +1
>             similar issue
> 
>      * igt@kms_cursor_legacy@pipe-d-single-move:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109278]) +18 similar issues
>      * igt@kms_display_modes@extended-mode-basic:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109274]) +1 similar issue
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109274])
> 
>      * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5287]) +2 similar issues
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5287])
> 
>      * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
> 
>           * shard-glk: PASS -> FAIL ([i915#79]) +1 similar issue
>      * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2587])
>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
> 
>           * shard-iclb: PASS -> SKIP ([i915#3701])
>      * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling:
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#2587])
>      * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109280]) +17 similar issues
>      * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
> 
>           * shard-tglb: NOTRUN -> SKIP ([fdo#109280] / [fdo#111825]) +37
>             similar issues
>      * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271]) +66 similar issues
>      * igt@kms_hdr@static-toggle-dpms:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3555])
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#3555])
> 
>      * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1839])
>      * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109289]) +1 similar issue
>      * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
> 
>           * shard-apl: PASS -> DMESG-WARN ([i915#180]) +1 similar issue
>      * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
> 
>           * shard-apl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +1 similar
>             issue
>      * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
> 
>           * shard-glk: NOTRUN -> FAIL ([i915#265])
> 
>           * shard-apl: NOTRUN -> FAIL ([i915#265])
> 
>      * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
> 
>           * shard-kbl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +1 similar
>             issue
>      * igt@kms_plane_lowres@pipe-c-tiling-4:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#5288]) +1 similar issue
> 
>           * shard-iclb: NOTRUN -> SKIP ([i915#5288])
> 
>      * igt@kms_plane_lowres@pipe-d-tiling-none:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#3536])
>      * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
> 
>           * shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +1 similar
>             issue
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +2 similar
>             issues
> 
>           * shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#658])
> 
>      * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#111068] / [i915#658]) +1 similar
>             issue
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#2920]) +1 similar issue
> 
>      * igt@kms_psr2_su@page_flip-p010:
> 
>           * shard-tglb: NOTRUN -> SKIP ([i915#1911])
>      * igt@kms_psr@psr2_dpms:
> 
>           * shard-tglb: NOTRUN -> FAIL ([i915#132] / [i915#3467]) +1 similar
>             issue
> 
>           * shard-iclb: NOTRUN -> SKIP ([fdo#109441])
> 
>      * igt@kms_psr@psr2_primary_blt:
> 
>           * shard-iclb: PASS -> SKIP ([fdo#109441]) +1 similar issue
>      * igt@kms_scaling_modes@scaling-mode-full-aspect:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271]) +158 similar issues
>      * igt@kms_vblank@pipe-d-wait-idle:
> 
>           * shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#533])