[Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Matt Roper]

Xe_HP removed "slice" as a first-class unit in the hardware design.
Instead we now have a single pool of subslices (which are now referred
to as "DSS") that different hardware units have different ways of
grouping ("compute slices," "geometry slices," etc.).  For the purposes
of topology representation, we treat Xe_HP-based platforms as having a
single slice that contains all of the platform's DSS.  There's no need
to allocate storage space for (max legacy slices * max dss); let's
update some of our macros to minimize the storage requirement for sseu
topology.  We'll also document some of the constants to make it a little
bit more clear what they represent.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
 2 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 4fbf45a74ec0..f9e246004bc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
 
 #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
-	     (iter_) < GEN_MAX_SUBSLICES; \
+	     (iter_) < GEN_SS_MASK_SIZE; \
 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 8a79cd8eaab4..4f59eadbb61a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,26 +15,49 @@ struct drm_i915_private;
 struct intel_gt;
 struct drm_printer;
 
-#define GEN_MAX_SLICES		(3) /* SKL upper bound */
-#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
-#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
-#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS		(16) /* TGL upper bound */
-#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
+/*
+ * Maximum number of legacy slices.  Legacy slices no longer exist starting on
+ * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
+ * concept and are not expressed through fusing).
+ */
+#define GEN_MAX_LEGACY_SLICES		3
+
+/*
+ * Maximum number of subslices that can exist within a legacy slice.  This is
+ * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
+ * value below).
+ */
+#define GEN_MAX_LEGACY_SUBSLICES	6
+
+/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
+#define GEN_MAX_DSS			32
+
+/* Maximum number of EUs that can exist within a subslice or DSS. */
+#define GEN_MAX_EUS_PER_SS		16
+
+#define MAX(a, b)			((a) > (b) ? (a) : (b))
+
+/* The maximum number of bits needed to express each subslice/DSS independently */
+#define GEN_SS_MASK_SIZE		MAX(GEN_MAX_DSS, \
+					    GEN_MAX_LEGACY_SLICES * GEN_MAX_LEGACY_SUBSLICES)
+
+#define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE		GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
+#define GEN_MAX_EU_STRIDE		GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
 
 #define GEN_DSS_PER_GSLICE	4
 #define GEN_DSS_PER_CSLICE	8
 #define GEN_DSS_PER_MSLICE	8
 
-#define GEN_MAX_GSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
 
 struct sseu_dev_info {
 	u8 slice_mask;
-	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
+	u8 subslice_mask[GEN_SS_MASK_SIZE];
+	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
+	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
 	u16 eu_total;
 	u8 eu_per_subslice;
 	u8 min_eu_in_pool;
-- 
2.34.1

[PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Matt Roper]

Xe_HP removed "slice" as a first-class unit in the hardware design.
Instead we now have a single pool of subslices (which are now referred
to as "DSS") that different hardware units have different ways of
grouping ("compute slices," "geometry slices," etc.).  For the purposes
of topology representation, we treat Xe_HP-based platforms as having a
single slice that contains all of the platform's DSS.  There's no need
to allocate storage space for (max legacy slices * max dss); let's
update some of our macros to minimize the storage requirement for sseu
topology.  We'll also document some of the constants to make it a little
bit more clear what they represent.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
 drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
 2 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 4fbf45a74ec0..f9e246004bc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
 
 #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
-	     (iter_) < GEN_MAX_SUBSLICES; \
+	     (iter_) < GEN_SS_MASK_SIZE; \
 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 8a79cd8eaab4..4f59eadbb61a 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -15,26 +15,49 @@ struct drm_i915_private;
 struct intel_gt;
 struct drm_printer;
 
-#define GEN_MAX_SLICES		(3) /* SKL upper bound */
-#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
-#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
-#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
-#define GEN_MAX_EUS		(16) /* TGL upper bound */
-#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
+/*
+ * Maximum number of legacy slices.  Legacy slices no longer exist starting on
+ * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
+ * concept and are not expressed through fusing).
+ */
+#define GEN_MAX_LEGACY_SLICES		3
+
+/*
+ * Maximum number of subslices that can exist within a legacy slice.  This is
+ * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
+ * value below).
+ */
+#define GEN_MAX_LEGACY_SUBSLICES	6
+
+/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
+#define GEN_MAX_DSS			32
+
+/* Maximum number of EUs that can exist within a subslice or DSS. */
+#define GEN_MAX_EUS_PER_SS		16
+
+#define MAX(a, b)			((a) > (b) ? (a) : (b))
+
+/* The maximum number of bits needed to express each subslice/DSS independently */
+#define GEN_SS_MASK_SIZE		MAX(GEN_MAX_DSS, \
+					    GEN_MAX_LEGACY_SLICES * GEN_MAX_LEGACY_SUBSLICES)
+
+#define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE		GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
+#define GEN_MAX_EU_STRIDE		GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
 
 #define GEN_DSS_PER_GSLICE	4
 #define GEN_DSS_PER_CSLICE	8
 #define GEN_DSS_PER_MSLICE	8
 
-#define GEN_MAX_GSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
 
 struct sseu_dev_info {
 	u8 slice_mask;
-	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
-	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
+	u8 subslice_mask[GEN_SS_MASK_SIZE];
+	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
+	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
 	u16 eu_total;
 	u8 eu_per_subslice;
 	u8 min_eu_in_pool;
-- 
2.34.1

[Intel-gfx] [PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[Matt Roper]

When running on Xe_HP or beyond, let's use an updated format for
describing topology in our error state dumps and debugfs to give a
more accurate view of the hardware:

 - Just report DSS directly without the legacy "slice0" output that's no
   longer meaningful.
 - Indicate whether each DSS is accessible for geometry and/or compute.
 - Rename "rcs_topology" to "sseu_topology" since the information
   reported is common to both RCS and CCS engines now.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c         | 48 +++++++++++++++++---
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  3 +-
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c |  8 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c        |  2 +-
 4 files changed, 48 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 614915ffbd37..4d28458ab768 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,6 +10,8 @@
 #include "intel_gt_regs.h"
 #include "intel_sseu.h"
 
+#include "linux/string_helpers.h"
+
 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 			 u8 max_subslices, u8 max_eus_per_subslice)
 {
@@ -54,6 +56,11 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
 	return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice);
 }
 
+u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
+{
+	return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
+}
+
 u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
 {
 	return _intel_sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
@@ -720,16 +727,11 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 		   str_yes_no(sseu->has_eu_pg));
 }
 
-void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
-			       struct drm_printer *p)
+static void intel_sseu_print_legacy_topology(const struct sseu_dev_info *sseu,
+					     struct drm_printer *p)
 {
 	int s, ss;
 
-	if (sseu->max_slices == 0) {
-		drm_printf(p, "Unavailable\n");
-		return;
-	}
-
 	for (s = 0; s < sseu->max_slices; s++) {
 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
 			   s, intel_sseu_subslices_per_slice(sseu, s),
@@ -744,6 +746,38 @@ void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
 	}
 }
 
+static void intel_sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
+					   struct drm_printer *p)
+{
+	u32 g_dss_mask = intel_sseu_get_geometry_subslices(sseu);
+	u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
+	int dss;
+
+	for (dss = 0; dss < sseu->max_subslices; dss++) {
+		u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
+
+		drm_printf(p, "DSS%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
+			   str_yes_no(g_dss_mask & BIT(dss)),
+			   str_yes_no(c_dss_mask & BIT(dss)),
+			   hweight16(enabled_eus), enabled_eus);
+	}
+}
+
+
+void intel_sseu_print_topology(struct drm_i915_private *i915,
+			       const struct sseu_dev_info *sseu,
+			       struct drm_printer *p)
+{
+	if (sseu->max_slices == 0) {
+		drm_printf(p, "Unavailable\n");
+		return;
+	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+		intel_sseu_print_xehp_topology(sseu, p);
+	} else {
+		intel_sseu_print_legacy_topology(sseu, p);
+	}
+}
+
 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
 {
 	u16 slice_mask = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4f59eadbb61a..fe22ea9bb213 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -139,7 +139,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 			 const struct intel_sseu *req_sseu);
 
 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
-void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
+void intel_sseu_print_topology(struct drm_i915_private *i915,
+			       const struct sseu_dev_info *sseu,
 			       struct drm_printer *p);
 
 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index a9d5bc49f361..6b944de48666 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -287,22 +287,22 @@ static int sseu_status_show(struct seq_file *m, void *unused)
 }
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_status);
 
-static int rcs_topology_show(struct seq_file *m, void *unused)
+static int sseu_topology_show(struct seq_file *m, void *unused)
 {
 	struct intel_gt *gt = m->private;
 	struct drm_printer p = drm_seq_file_printer(m);
 
-	intel_sseu_print_topology(&gt->info.sseu, &p);
+	intel_sseu_print_topology(gt->i915, &gt->info.sseu, &p);
 
 	return 0;
 }
-DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rcs_topology);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_topology);
 
 void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
 {
 	static const struct intel_gt_debugfs_file files[] = {
 		{ "sseu_status", &sseu_status_fops, NULL },
-		{ "rcs_topology", &rcs_topology_fops, NULL },
+		{ "sseu_topology", &sseu_topology_fops, NULL },
 	};
 
 	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5e09a4e4b01a..44ff2b899893 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -712,7 +712,7 @@ static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 	struct drm_printer p = i915_error_printer(m);
 
 	intel_gt_info_print(&gt->info, &p);
-	intel_sseu_print_topology(&gt->info.sseu, &p);
+	intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
 }
 
 static void err_print_gt(struct drm_i915_error_state_buf *m,
-- 
2.34.1

[PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[Matt Roper]

When running on Xe_HP or beyond, let's use an updated format for
describing topology in our error state dumps and debugfs to give a
more accurate view of the hardware:

 - Just report DSS directly without the legacy "slice0" output that's no
   longer meaningful.
 - Indicate whether each DSS is accessible for geometry and/or compute.
 - Rename "rcs_topology" to "sseu_topology" since the information
   reported is common to both RCS and CCS engines now.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c         | 48 +++++++++++++++++---
 drivers/gpu/drm/i915/gt/intel_sseu.h         |  3 +-
 drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c |  8 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c        |  2 +-
 4 files changed, 48 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 614915ffbd37..4d28458ab768 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,6 +10,8 @@
 #include "intel_gt_regs.h"
 #include "intel_sseu.h"
 
+#include "linux/string_helpers.h"
+
 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 			 u8 max_subslices, u8 max_eus_per_subslice)
 {
@@ -54,6 +56,11 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
 	return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice);
 }
 
+u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
+{
+	return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
+}
+
 u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
 {
 	return _intel_sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
@@ -720,16 +727,11 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 		   str_yes_no(sseu->has_eu_pg));
 }
 
-void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
-			       struct drm_printer *p)
+static void intel_sseu_print_legacy_topology(const struct sseu_dev_info *sseu,
+					     struct drm_printer *p)
 {
 	int s, ss;
 
-	if (sseu->max_slices == 0) {
-		drm_printf(p, "Unavailable\n");
-		return;
-	}
-
 	for (s = 0; s < sseu->max_slices; s++) {
 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
 			   s, intel_sseu_subslices_per_slice(sseu, s),
@@ -744,6 +746,38 @@ void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
 	}
 }
 
+static void intel_sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
+					   struct drm_printer *p)
+{
+	u32 g_dss_mask = intel_sseu_get_geometry_subslices(sseu);
+	u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
+	int dss;
+
+	for (dss = 0; dss < sseu->max_subslices; dss++) {
+		u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
+
+		drm_printf(p, "DSS%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
+			   str_yes_no(g_dss_mask & BIT(dss)),
+			   str_yes_no(c_dss_mask & BIT(dss)),
+			   hweight16(enabled_eus), enabled_eus);
+	}
+}
+
+
+void intel_sseu_print_topology(struct drm_i915_private *i915,
+			       const struct sseu_dev_info *sseu,
+			       struct drm_printer *p)
+{
+	if (sseu->max_slices == 0) {
+		drm_printf(p, "Unavailable\n");
+		return;
+	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+		intel_sseu_print_xehp_topology(sseu, p);
+	} else {
+		intel_sseu_print_legacy_topology(sseu, p);
+	}
+}
+
 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
 {
 	u16 slice_mask = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4f59eadbb61a..fe22ea9bb213 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -139,7 +139,8 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
 			 const struct intel_sseu *req_sseu);
 
 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
-void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
+void intel_sseu_print_topology(struct drm_i915_private *i915,
+			       const struct sseu_dev_info *sseu,
 			       struct drm_printer *p);
 
 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index a9d5bc49f361..6b944de48666 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -287,22 +287,22 @@ static int sseu_status_show(struct seq_file *m, void *unused)
 }
 DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_status);
 
-static int rcs_topology_show(struct seq_file *m, void *unused)
+static int sseu_topology_show(struct seq_file *m, void *unused)
 {
 	struct intel_gt *gt = m->private;
 	struct drm_printer p = drm_seq_file_printer(m);
 
-	intel_sseu_print_topology(&gt->info.sseu, &p);
+	intel_sseu_print_topology(gt->i915, &gt->info.sseu, &p);
 
 	return 0;
 }
-DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rcs_topology);
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(sseu_topology);
 
 void intel_sseu_debugfs_register(struct intel_gt *gt, struct dentry *root)
 {
 	static const struct intel_gt_debugfs_file files[] = {
 		{ "sseu_status", &sseu_status_fops, NULL },
-		{ "rcs_topology", &rcs_topology_fops, NULL },
+		{ "sseu_topology", &sseu_topology_fops, NULL },
 	};
 
 	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5e09a4e4b01a..44ff2b899893 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -712,7 +712,7 @@ static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 	struct drm_printer p = i915_error_printer(m);
 
 	intel_gt_info_print(&gt->info, &p);
-	intel_sseu_print_topology(&gt->info.sseu, &p);
+	intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
 }
 
 static void err_print_gt(struct drm_i915_error_state_buf *m,
-- 
2.34.1

Re: [Intel-gfx] [PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[kernel test robot]

Hi Matt,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next next-20220310]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-debian-10.3 (https://download.01.org/0day-ci/archive/20220311/202203112245.eDvNTHyE-lkp@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/38985b2e6acdbe67dedb5de8a8aeef917b746453
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
        git checkout 38985b2e6acdbe67dedb5de8a8aeef917b746453
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: warning: no previous prototype for 'intel_sseu_get_geometry_subslices' [-Wmissing-prototypes]
      59 | u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/intel_sseu_get_geometry_subslices +59 drivers/gpu/drm/i915/gt/intel_sseu.c

    58	
  > 59	u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
    60	{
    61		return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
    62	}
    63	

---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[kernel test robot]

Hi Matt,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next next-20220310]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next v5.17-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a013 (https://download.01.org/0day-ci/archive/20220311/202203112234.rtvKSbsq-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 276ca87382b8f16a65bddac700202924228982f6)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/38985b2e6acdbe67dedb5de8a8aeef917b746453
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
        git checkout 38985b2e6acdbe67dedb5de8a8aeef917b746453
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/ net/core/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: warning: no previous prototype for function 'intel_sseu_get_geometry_subslices' [-Wmissing-prototypes]
   u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
       ^
   drivers/gpu/drm/i915/gt/intel_sseu.c:59:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
   ^
   static 
   1 warning generated.


vim +/intel_sseu_get_geometry_subslices +59 drivers/gpu/drm/i915/gt/intel_sseu.c

    58	
  > 59	u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
    60	{
    61		return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
    62	}
    63	

---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[RFC PATCH] drm/i915/xehp: intel_sseu_get_geometry_subslices() can be static

[kernel test robot]

drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: warning: symbol 'intel_sseu_get_geometry_subslices' was not declared. Should it be static?

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 4d28458ab768d..99e31dcf3db06 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -56,7 +56,7 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
 	return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice);
 }
 
-u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
+static u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
 {
 	return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
 }

[Intel-gfx] [RFC PATCH] drm/i915/xehp: intel_sseu_get_geometry_subslices() can be static

[kernel test robot]

drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: warning: symbol 'intel_sseu_get_geometry_subslices' was not declared. Should it be static?

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 4d28458ab768d..99e31dcf3db06 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -56,7 +56,7 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
 	return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice);
 }
 
-u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
+static u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
 {
 	return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
 }

Re: [Intel-gfx] [PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[kernel test robot]

Hi Matt,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next next-20220310]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-rhel-8.3-kselftests (https://download.01.org/0day-ci/archive/20220312/202203120322.OkxCdfs7-lkp@intel.com/config)
compiler: gcc-9 (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.4-dirty
        # https://github.com/0day-ci/linux/commit/38985b2e6acdbe67dedb5de8a8aeef917b746453
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Matt-Roper/drm-i915-sseu-Don-t-overallocate-subslice-storage/20220311-141705
        git checkout 38985b2e6acdbe67dedb5de8a8aeef917b746453
        # save the config file to linux build tree
        mkdir build_dir
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_sseu.c:59:5: sparse: sparse: symbol 'intel_sseu_get_geometry_subslices' was not declared. Should it be static?

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH 2/2] drm/i915/xehp: Update topology dumps for Xe_HP

[Lucas De Marchi]

On Thu, Mar 10, 2022 at 10:15:43PM -0800, Matt Roper wrote:
>When running on Xe_HP or beyond, let's use an updated format for
>describing topology in our error state dumps and debugfs to give a
>more accurate view of the hardware:
>
> - Just report DSS directly without the legacy "slice0" output that's no
>   longer meaningful.
> - Indicate whether each DSS is accessible for geometry and/or compute.
> - Rename "rcs_topology" to "sseu_topology" since the information
>   reported is common to both RCS and CCS engines now.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_sseu.c         | 48 +++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_sseu.h         |  3 +-
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c |  8 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c        |  2 +-
> 4 files changed, 48 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
>index 614915ffbd37..4d28458ab768 100644
>--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
>+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
>@@ -10,6 +10,8 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu.h"
>
>+#include "linux/string_helpers.h"
>+
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> 			 u8 max_subslices, u8 max_eus_per_subslice)
> {
>@@ -54,6 +56,11 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> 	return _intel_sseu_get_subslices(sseu, sseu->subslice_mask, slice);

this func with a single underscore is the one inconsistent with the rest of the file.
Just rename it while touching this part of the code?

> }
>
>+u32 intel_sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)

since it's only local to this compilation unit, make it static and
remove the intel_ prefix?

>+{
>+	return _intel_sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
>+}
>+
> u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> {
> 	return _intel_sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
>@@ -720,16 +727,11 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> 		   str_yes_no(sseu->has_eu_pg));
> }
>
>-void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
>-			       struct drm_printer *p)
>+static void intel_sseu_print_legacy_topology(const struct sseu_dev_info *sseu,

removing the intel_ prefix would make it consistent with the rest of the file too

>+					     struct drm_printer *p)
> {
> 	int s, ss;
>
>-	if (sseu->max_slices == 0) {
>-		drm_printf(p, "Unavailable\n");
>-		return;
>-	}
>-
> 	for (s = 0; s < sseu->max_slices; s++) {
> 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> 			   s, intel_sseu_subslices_per_slice(sseu, s),
>@@ -744,6 +746,38 @@ void intel_sseu_print_topology(const struct sseu_dev_info *sseu,
> 	}
> }
>
>+static void intel_sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
>+					   struct drm_printer *p)

ditto

>+{
>+	u32 g_dss_mask = intel_sseu_get_geometry_subslices(sseu);
>+	u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
>+	int dss;
>+
>+	for (dss = 0; dss < sseu->max_subslices; dss++) {
>+		u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>+
>+		drm_printf(p, "DSS%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
>+			   str_yes_no(g_dss_mask & BIT(dss)),
>+			   str_yes_no(c_dss_mask & BIT(dss)),
>+			   hweight16(enabled_eus), enabled_eus);
>+	}
>+}
>+
>+
>+void intel_sseu_print_topology(struct drm_i915_private *i915,
>+			       const struct sseu_dev_info *sseu,
>+			       struct drm_printer *p)
>+{
>+	if (sseu->max_slices == 0) {
>+		drm_printf(p, "Unavailable\n");
>+		return;

either make this an early return, or remove the return

other than coding style nits metioned above,


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage
URL   : https://patchwork.freedesktop.org/series/101268/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5c1d208e40c1 drm/i915/sseu: Don't overallocate subslice storage
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'a' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:38:
+#define MAX(a, b)			((a) > (b) ? (a) : (b))

-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'b' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:38:
+#define MAX(a, b)			((a) > (b) ? (a) : (b))

total: 0 errors, 0 warnings, 2 checks, 69 lines checked
27d39ebcdbba drm/i915/xehp: Update topology dumps for Xe_HP
-:83: CHECK:LINE_SPACING: Please don't use multiple blank lines
#83: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:766:
+
+

total: 0 errors, 0 warnings, 1 checks, 118 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage
URL   : https://patchwork.freedesktop.org/series/101268/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9958 bytes --]

== Series Details ==

Series: series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage
URL   : https://patchwork.freedesktop.org/series/101268/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11350 -> Patchwork_22538
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/index.html

Participating hosts (48 -> 43)
------------------------------

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing    (7): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl shard-dg1 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_22538 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-hsw-4770:        NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-pnv-d510:        NOTRUN -> [SKIP][4] ([fdo#109271]) +58 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-6:          [PASS][7] -> [FAIL][8] ([i915#4032])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-dg1-6/igt@i915_pm_rps@basic-api.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-dg1-6/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][10] -> [INCOMPLETE][11] ([i915#3921])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-cfl-8109u:       [PASS][14] -> [DMESG-WARN][15] ([i915#295]) +12 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  * igt@runner@aborted:
    - fi-bdw-5557u:       NOTRUN -> [FAIL][16] ([i915#2426] / [i915#4312])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-bdw-5557u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-bwr-2160:        [FAIL][17] ([i915#3194]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-bdw-5557u:       [INCOMPLETE][19] ([i915#146]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@execlists:
    - fi-icl-u2:          [INCOMPLETE][21] ([i915#5060]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-icl-u2/igt@i915_selftest@live@execlists.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-icl-u2/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {bat-rpls-2}:       [DMESG-WARN][23] ([i915#4391]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-rpls-2/igt@i915_selftest@live@gt_heartbeat.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-rpls-2/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-6:          [DMESG-FAIL][25] ([i915#4494] / [i915#4957]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
    - fi-hsw-4770:        [INCOMPLETE][27] ([i915#3303]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@hugepages:
    - {bat-rpls-2}:       [DMESG-WARN][29] ([i915#5278]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-rpls-2/igt@i915_selftest@live@hugepages.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-rpls-2/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-2}:       [INCOMPLETE][31] ([i915#4983]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-rpls-2/igt@i915_selftest@live@reset.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-rpls-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@workarounds:
    - {bat-adlp-6}:       [DMESG-WARN][33] ([i915#5068]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-adlp-6/igt@i915_selftest@live@workarounds.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-adlp-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_busy@basic@flip:
    - {bat-adlp-6}:       [DMESG-WARN][35] ([i915#3576]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/bat-adlp-6/igt@kms_busy@basic@flip.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/bat-adlp-6/igt@kms_busy@basic@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5060]: https://gitlab.freedesktop.org/drm/intel/issues/5060
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
  [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * Linux: CI_DRM_11350 -> Patchwork_22538

  CI-20190529: 20190529
  CI_DRM_11350: 925314164278701a48bb63b89a95d6c7e179a02e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6375: aa6eb64bac510b7d617436997171bfe388943d89 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22538: 27d39ebcdbba3bc414a7cb8a82f5b35db2ffc30f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

27d39ebcdbba drm/i915/xehp: Update topology dumps for Xe_HP
5c1d208e40c1 drm/i915/sseu: Don't overallocate subslice storage

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/index.html

[-- Attachment #2: Type: text/html, Size: 11535 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30299 bytes --]

== Series Details ==

Series: series starting with [1/2] drm/i915/sseu: Don't overallocate subslice storage
URL   : https://patchwork.freedesktop.org/series/101268/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11350_full -> Patchwork_22538_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22538_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22538_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22538_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_whisper@basic-fds-forked-all:
    - shard-glk:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk4/igt@gem_exec_whisper@basic-fds-forked-all.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk1/igt@gem_exec_whisper@basic-fds-forked-all.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - {shard-tglu}:       [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-tglu-6/igt@i915_suspend@fence-restore-tiled2untiled.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglu-1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_plane_lowres@pipe-b-tiling-4:
    - {shard-rkl}:        [SKIP][5] ([i915#4098]) -> [SKIP][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-rkl-5/igt@kms_plane_lowres@pipe-b-tiling-4.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-rkl-1/igt@kms_plane_lowres@pipe-b-tiling-4.html

  
Known issues
------------

  Here are the changes found in Patchwork_22538_full that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - shard-skl:          ([PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [FAIL][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#5032])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl9/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl9/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl8/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl8/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl8/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl7/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl7/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl6/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl6/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl6/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl4/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl4/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl3/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl3/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl3/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl2/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl2/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl1/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl1/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl1/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl10/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl10/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl10/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl6/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl4/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl4/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl4/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl3/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl2/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl2/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl10/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl10/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl10/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl9/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl9/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl8/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl8/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl8/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl7/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl7/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl6/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl6/boot.html
    - shard-glk:          ([PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75]) -> ([FAIL][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100]) ([i915#4392])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk5/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk1/boot.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk1/boot.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk1/boot.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk2/boot.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk2/boot.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk3/boot.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk3/boot.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk3/boot.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk4/boot.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk9/boot.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk4/boot.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk9/boot.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk9/boot.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk4/boot.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk8/boot.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk8/boot.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk7/boot.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk7/boot.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk5/boot.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk5/boot.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk6/boot.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk6/boot.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk6/boot.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-glk5/boot.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk2/boot.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk2/boot.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk3/boot.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk3/boot.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk3/boot.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk4/boot.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk4/boot.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk5/boot.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk5/boot.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk5/boot.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/boot.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/boot.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk7/boot.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk7/boot.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk8/boot.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk8/boot.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk8/boot.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk9/boot.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk9/boot.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk9/boot.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk1/boot.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk1/boot.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk1/boot.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk1/boot.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk2/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][101] ([i915#4991])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl7/igt@gem_create@create-massive.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([i915#4525])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_capture@pi@bcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][103] ([i915#4547])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl7/igt@gem_exec_capture@pi@bcs0.html
    - shard-tglb:         [PASS][104] -> [INCOMPLETE][105] ([i915#3371] / [i915#3731])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-tglb1/igt@gem_exec_capture@pi@bcs0.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb3/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [PASS][106] -> [FAIL][107] ([i915#2842])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][108] ([i915#2842])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][109] ([fdo#109283])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@gem_exec_params@no-vebox.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-iclb:         NOTRUN -> [SKIP][110] ([i915#4613])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@gem_lmem_swapping@heavy-random.html
    - shard-apl:          NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#4613])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl7/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-glk:          NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#4613])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random:
    - shard-skl:          NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#4613])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@gem_lmem_swapping@random.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-iclb:         NOTRUN -> [SKIP][114] ([i915#4270])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-tglb:         NOTRUN -> [SKIP][115] ([i915#4270])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][116] ([i915#768]) +3 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-glk:          NOTRUN -> [SKIP][117] ([fdo#109271]) +35 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gen3_render_linear_blits:
    - shard-tglb:         NOTRUN -> [SKIP][118] ([fdo#109289])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@gen3_render_linear_blits.html

  * igt@gen7_exec_parse@basic-rejected:
    - shard-iclb:         NOTRUN -> [SKIP][119] ([fdo#109289])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@gen7_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-iclb:         NOTRUN -> [SKIP][120] ([i915#2856])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@gen9_exec_parse@secure-batches.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][121] -> [FAIL][122] ([i915#454])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-iclb:         NOTRUN -> [SKIP][123] ([i915#1902])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@i915_pm_lpsp@screens-disabled.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         NOTRUN -> [WARN][124] ([i915#1804] / [i915#2684])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-iclb:         NOTRUN -> [SKIP][125] ([fdo#110892])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][126] ([i915#5286]) +1 similar issue
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][127] ([fdo#110725] / [fdo#111614])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][128] ([i915#3743]) +2 similar issues
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
    - shard-snb:          [PASS][129] -> [SKIP][130] ([fdo#109271])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-snb4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-snb4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-skl:          NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#3777])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][132] ([i915#3763])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-iclb:         [PASS][133] -> [FAIL][134] ([i915#1888])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-iclb2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
    - shard-iclb:         NOTRUN -> [SKIP][135] ([fdo#110723])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-glk:          NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#3777]) +1 similar issue
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][137] ([fdo#109271]) +89 similar issues
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_joiner@2x-modeset:
    - shard-iclb:         NOTRUN -> [SKIP][138] ([i915#2705])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@kms_big_joiner@2x-modeset.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][139] ([fdo#109278] / [i915#3886]) +4 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][140] ([fdo#111615] / [i915#3689])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#3886]) +7 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][142] ([fdo#109271] / [i915#3886]) +3 similar issues
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#3886]) +1 similar issue
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][144] ([i915#3689])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-apl:          NOTRUN -> [SKIP][145] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl1/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
    - shard-glk:          NOTRUN -> [SKIP][146] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@kms_chamelium@hdmi-aspect-ratio.html

  * igt@kms_chamelium@hdmi-audio:
    - shard-iclb:         NOTRUN -> [SKIP][147] ([fdo#109284] / [fdo#111827]) +10 similar issues
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_chamelium@hdmi-audio.html

  * igt@kms_chamelium@hdmi-hpd-after-suspend:
    - shard-snb:          NOTRUN -> [SKIP][148] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-snb4/igt@kms_chamelium@hdmi-hpd-after-suspend.html

  * igt@kms_color@pipe-d-ctm-0-5:
    - shard-iclb:         NOTRUN -> [SKIP][149] ([fdo#109278] / [i915#1149])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@kms_color@pipe-d-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-b-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][150] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_color_chamelium@pipe-b-ctm-max.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][151] -> [DMESG-WARN][152] ([i915#180]) +1 similar issue
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][153] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][154] ([fdo#109278]) +20 similar issues
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-iclb:         NOTRUN -> [SKIP][155] ([fdo#109274] / [fdo#109278]) +2 similar issues
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-tglb:         NOTRUN -> [SKIP][156] ([fdo#109274] / [fdo#111825]) +1 similar issue
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][157] -> [FAIL][158] ([i915#2346] / [i915#533])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-iclb:         [PASS][159] -> [FAIL][160] ([i915#2346])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-iclb5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][161] ([fdo#109271] / [i915#533]) +1 similar issue
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl2/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
    - shard-iclb:         NOTRUN -> [SKIP][162] ([i915#5287]) +1 similar issue
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [PASS][163] -> [INCOMPLETE][164] ([i915#180] / [i915#636])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][165] ([fdo#109274]) +4 similar issues
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-skl:          [PASS][166] -> [INCOMPLETE][167] ([i915#4839])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][168] ([fdo#109271]) +154 similar issues
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][169] ([fdo#109280] / [fdo#111825]) +4 similar issues
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][170] ([fdo#109280]) +22 similar issues
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-skl:          NOTRUN -> [SKIP][171] ([fdo#109271] / [i915#533]) +1 similar issue
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-apl:          [PASS][172] -> [DMESG-WARN][173] ([i915#180]) +6 similar issues
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11350/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-skl:          NOTRUN -> [FAIL][174] ([fdo#108145] / [i915#265]) +1 similar issue
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][175] ([fdo#108145] / [i915#265])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-glk6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_lowres@pipe-a-tiling-4:
    - shard-iclb:         NOTRUN -> [SKIP][176] ([i915#5288]) +1 similar issue
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-4.html

  * igt@kms_plane_lowres@pipe-c-tiling-yf:
    - shard-iclb:         NOTRUN -> [SKIP][177] ([i915#3536])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-iclb5/igt@kms_plane_lowres@pipe-c-tiling-yf.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][178] ([fdo#109271] / [i915#658])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22538/index.html

[-- Attachment #2: Type: text/html, Size: 33177 bytes --]

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Lucas De Marchi]

On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
>Xe_HP removed "slice" as a first-class unit in the hardware design.
>Instead we now have a single pool of subslices (which are now referred
>to as "DSS") that different hardware units have different ways of
>grouping ("compute slices," "geometry slices," etc.).  For the purposes
>of topology representation, we treat Xe_HP-based platforms as having a
>single slice that contains all of the platform's DSS.  There's no need
>to allocate storage space for (max legacy slices * max dss); let's
>update some of our macros to minimize the storage requirement for sseu
>topology.  We'll also document some of the constants to make it a little
>bit more clear what they represent.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
> drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
> 2 files changed, 36 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>index 4fbf45a74ec0..f9e246004bc0 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>@@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
>
> #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
> 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
>-	     (iter_) < GEN_MAX_SUBSLICES; \
>+	     (iter_) < GEN_SS_MASK_SIZE; \
> 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
> 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
> 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
>diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
>index 8a79cd8eaab4..4f59eadbb61a 100644
>--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
>+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
>@@ -15,26 +15,49 @@ struct drm_i915_private;
> struct intel_gt;
> struct drm_printer;
>
>-#define GEN_MAX_SLICES		(3) /* SKL upper bound */
>-#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
>-#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
>-#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
>-#define GEN_MAX_EUS		(16) /* TGL upper bound */
>-#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
>+/*
>+ * Maximum number of legacy slices.  Legacy slices no longer exist starting on
>+ * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
>+ * concept and are not expressed through fusing).
>+ */
>+#define GEN_MAX_LEGACY_SLICES		3
>+
>+/*
>+ * Maximum number of subslices that can exist within a legacy slice.  This is
>+ * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
>+ * value below).
>+ */
>+#define GEN_MAX_LEGACY_SUBSLICES	6

instead of calling the old legacy, maybe just add the XEHP_ prefix to
the new ones?

>+
>+/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
>+#define GEN_MAX_DSS			32
>+
>+/* Maximum number of EUs that can exist within a subslice or DSS. */
>+#define GEN_MAX_EUS_PER_SS		16
>+
>+#define MAX(a, b)			((a) > (b) ? (a) : (b))

what's worse, include kernel.h in another header file or redefine MAX
everywhere? Re-defining it in headers we risk situations in which the
include order may create warnings about defining it in multiple places.


>+
>+/* The maximum number of bits needed to express each subslice/DSS independently */
>+#define GEN_SS_MASK_SIZE		MAX(GEN_MAX_DSS, \
>+					    GEN_MAX_LEGACY_SLICES * GEN_MAX_LEGACY_SUBSLICES)
>+
>+#define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
>+#define GEN_MAX_SUBSLICE_STRIDE		GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
>+#define GEN_MAX_EU_STRIDE		GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
>
> #define GEN_DSS_PER_GSLICE	4
> #define GEN_DSS_PER_CSLICE	8
> #define GEN_DSS_PER_MSLICE	8
>
>-#define GEN_MAX_GSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
>-#define GEN_MAX_CSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
>+#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
>+#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
>
> struct sseu_dev_info {
> 	u8 slice_mask;
>-	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
>-	u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
>-	u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
>-	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
>+	u8 subslice_mask[GEN_SS_MASK_SIZE];
>+	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
>+	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
>+	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];


Aside the minor things above, everything look correct.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

> 	u16 eu_total;
> 	u8 eu_per_subslice;
> 	u8 min_eu_in_pool;
>-- 
>2.34.1
>

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Matt Roper]

On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > Instead we now have a single pool of subslices (which are now referred
> > to as "DSS") that different hardware units have different ways of
> > grouping ("compute slices," "geometry slices," etc.).  For the purposes
> > of topology representation, we treat Xe_HP-based platforms as having a
> > single slice that contains all of the platform's DSS.  There's no need
> > to allocate storage space for (max legacy slices * max dss); let's
> > update some of our macros to minimize the storage requirement for sseu
> > topology.  We'll also document some of the constants to make it a little
> > bit more clear what they represent.
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
> > drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
> > 2 files changed, 36 insertions(+), 13 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index 4fbf45a74ec0..f9e246004bc0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
> > 
> > #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
> > 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
> > -	     (iter_) < GEN_MAX_SUBSLICES; \
> > +	     (iter_) < GEN_SS_MASK_SIZE; \
> > 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
> > 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
> > 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index 8a79cd8eaab4..4f59eadbb61a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -15,26 +15,49 @@ struct drm_i915_private;
> > struct intel_gt;
> > struct drm_printer;
> > 
> > -#define GEN_MAX_SLICES		(3) /* SKL upper bound */
> > -#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
> > -#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > -#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> > -#define GEN_MAX_EUS		(16) /* TGL upper bound */
> > -#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
> > +/*
> > + * Maximum number of legacy slices.  Legacy slices no longer exist starting on
> > + * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
> > + * concept and are not expressed through fusing).
> > + */
> > +#define GEN_MAX_LEGACY_SLICES		3
> > +
> > +/*
> > + * Maximum number of subslices that can exist within a legacy slice.  This is
> > + * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
> > + * value below).
> > + */
> > +#define GEN_MAX_LEGACY_SUBSLICES	6
> 
> instead of calling the old legacy, maybe just add the XEHP_ prefix to
> the new ones?

Maybe a "HSW_" prefix on the old ones would be better?  People still use
the termm 'subslice' in casual discussion when talking about DSS, so I
want to somehow distinguish that what we're talking about here is a
different, older design than we have on modern platforms.


Matt

> 
> > +
> > +/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> > +#define GEN_MAX_DSS			32
> > +
> > +/* Maximum number of EUs that can exist within a subslice or DSS. */
> > +#define GEN_MAX_EUS_PER_SS		16
> > +
> > +#define MAX(a, b)			((a) > (b) ? (a) : (b))
> 
> what's worse, include kernel.h in another header file or redefine MAX
> everywhere? Re-defining it in headers we risk situations in which the
> include order may create warnings about defining it in multiple places.
> 
> 
> > +
> > +/* The maximum number of bits needed to express each subslice/DSS independently */
> > +#define GEN_SS_MASK_SIZE		MAX(GEN_MAX_DSS, \
> > +					    GEN_MAX_LEGACY_SLICES * GEN_MAX_LEGACY_SUBSLICES)
> > +
> > +#define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > +#define GEN_MAX_SUBSLICE_STRIDE		GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
> > +#define GEN_MAX_EU_STRIDE		GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
> > 
> > #define GEN_DSS_PER_GSLICE	4
> > #define GEN_DSS_PER_CSLICE	8
> > #define GEN_DSS_PER_MSLICE	8
> > 
> > -#define GEN_MAX_GSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
> > -#define GEN_MAX_CSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
> > +#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> > +#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> > 
> > struct sseu_dev_info {
> > 	u8 slice_mask;
> > -	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > -	u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > -	u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > -	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
> > +	u8 subslice_mask[GEN_SS_MASK_SIZE];
> > +	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> > +	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> > +	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
> 
> 
> Aside the minor things above, everything look correct.
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> thanks
> Lucas De Marchi
> 
> > 	u16 eu_total;
> > 	u8 eu_per_subslice;
> > 	u8 min_eu_in_pool;
> > -- 
> > 2.34.1
> > 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Matt Roper]

On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > > Instead we now have a single pool of subslices (which are now referred
> > > to as "DSS") that different hardware units have different ways of
> > > grouping ("compute slices," "geometry slices," etc.).  For the purposes
> > > of topology representation, we treat Xe_HP-based platforms as having a
> > > single slice that contains all of the platform's DSS.  There's no need
> > > to allocate storage space for (max legacy slices * max dss); let's
> > > update some of our macros to minimize the storage requirement for sseu
> > > topology.  We'll also document some of the constants to make it a little
> > > bit more clear what they represent.
> > > 
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
> > > drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
> > > 2 files changed, 36 insertions(+), 13 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > index 4fbf45a74ec0..f9e246004bc0 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > > @@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
> > > 
> > > #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
> > > 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
> > > -	     (iter_) < GEN_MAX_SUBSLICES; \
> > > +	     (iter_) < GEN_SS_MASK_SIZE; \
> > > 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
> > > 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
> > > 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > index 8a79cd8eaab4..4f59eadbb61a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > > @@ -15,26 +15,49 @@ struct drm_i915_private;
> > > struct intel_gt;
> > > struct drm_printer;
> > > 
> > > -#define GEN_MAX_SLICES		(3) /* SKL upper bound */
> > > -#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
> > > -#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > > -#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> > > -#define GEN_MAX_EUS		(16) /* TGL upper bound */
> > > -#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
> > > +/*
> > > + * Maximum number of legacy slices.  Legacy slices no longer exist starting on
> > > + * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
> > > + * concept and are not expressed through fusing).
> > > + */
> > > +#define GEN_MAX_LEGACY_SLICES		3
> > > +
> > > +/*
> > > + * Maximum number of subslices that can exist within a legacy slice.  This is
> > > + * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
> > > + * value below).
> > > + */
> > > +#define GEN_MAX_LEGACY_SUBSLICES	6
> > 
> > instead of calling the old legacy, maybe just add the XEHP_ prefix to
> > the new ones?
> 
> Maybe a "HSW_" prefix on the old ones would be better?  People still use
> the termm 'subslice' in casual discussion when talking about DSS, so I
> want to somehow distinguish that what we're talking about here is a
> different, older design than we have on modern platforms.

Hmm, or maybe just "GEN_MAX_SUBSLICES_PER_LEGACY_SLICE" to tie it into
the slice definition above?


Matt

> 
> 
> Matt
> 
> > 
> > > +
> > > +/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> > > +#define GEN_MAX_DSS			32
> > > +
> > > +/* Maximum number of EUs that can exist within a subslice or DSS. */
> > > +#define GEN_MAX_EUS_PER_SS		16
> > > +
> > > +#define MAX(a, b)			((a) > (b) ? (a) : (b))
> > 
> > what's worse, include kernel.h in another header file or redefine MAX
> > everywhere? Re-defining it in headers we risk situations in which the
> > include order may create warnings about defining it in multiple places.
> > 
> > 
> > > +
> > > +/* The maximum number of bits needed to express each subslice/DSS independently */
> > > +#define GEN_SS_MASK_SIZE		MAX(GEN_MAX_DSS, \
> > > +					    GEN_MAX_LEGACY_SLICES * GEN_MAX_LEGACY_SUBSLICES)
> > > +
> > > +#define GEN_SSEU_STRIDE(max_entries)	DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > > +#define GEN_MAX_SUBSLICE_STRIDE		GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
> > > +#define GEN_MAX_EU_STRIDE		GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
> > > 
> > > #define GEN_DSS_PER_GSLICE	4
> > > #define GEN_DSS_PER_CSLICE	8
> > > #define GEN_DSS_PER_MSLICE	8
> > > 
> > > -#define GEN_MAX_GSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_GSLICE)
> > > -#define GEN_MAX_CSLICES		(GEN_MAX_SUBSLICES / GEN_DSS_PER_CSLICE)
> > > +#define GEN_MAX_GSLICES		(GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> > > +#define GEN_MAX_CSLICES		(GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> > > 
> > > struct sseu_dev_info {
> > > 	u8 slice_mask;
> > > -	u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > > -	u8 geometry_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > > -	u8 compute_subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
> > > -	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE];
> > > +	u8 subslice_mask[GEN_SS_MASK_SIZE];
> > > +	u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> > > +	u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> > > +	u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
> > 
> > 
> > Aside the minor things above, everything look correct.
> > 
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > 
> > thanks
> > Lucas De Marchi
> > 
> > > 	u16 eu_total;
> > > 	u8 eu_per_subslice;
> > > 	u8 min_eu_in_pool;
> > > -- 
> > > 2.34.1
> > > 
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Lucas De Marchi]

On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
>On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
>> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
>> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
>> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
>> > > Instead we now have a single pool of subslices (which are now referred
>> > > to as "DSS") that different hardware units have different ways of
>> > > grouping ("compute slices," "geometry slices," etc.).  For the purposes
>> > > of topology representation, we treat Xe_HP-based platforms as having a
>> > > single slice that contains all of the platform's DSS.  There's no need
>> > > to allocate storage space for (max legacy slices * max dss); let's
>> > > update some of our macros to minimize the storage requirement for sseu
>> > > topology.  We'll also document some of the constants to make it a little
>> > > bit more clear what they represent.
>> > >
>> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> > > ---
>> > > drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
>> > > drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
>> > > 2 files changed, 36 insertions(+), 13 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> > > index 4fbf45a74ec0..f9e246004bc0 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
>> > > @@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
>> > >
>> > > #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
>> > > 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
>> > > -	     (iter_) < GEN_MAX_SUBSLICES; \
>> > > +	     (iter_) < GEN_SS_MASK_SIZE; \
>> > > 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
>> > > 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
>> > > 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> > > index 8a79cd8eaab4..4f59eadbb61a 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
>> > > @@ -15,26 +15,49 @@ struct drm_i915_private;
>> > > struct intel_gt;
>> > > struct drm_printer;
>> > >
>> > > -#define GEN_MAX_SLICES		(3) /* SKL upper bound */
>> > > -#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
>> > > -#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
>> > > -#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
>> > > -#define GEN_MAX_EUS		(16) /* TGL upper bound */
>> > > -#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
>> > > +/*
>> > > + * Maximum number of legacy slices.  Legacy slices no longer exist starting on
>> > > + * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
>> > > + * concept and are not expressed through fusing).
>> > > + */
>> > > +#define GEN_MAX_LEGACY_SLICES		3
>> > > +
>> > > +/*
>> > > + * Maximum number of subslices that can exist within a legacy slice.  This is
>> > > + * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
>> > > + * value below).
>> > > + */
>> > > +#define GEN_MAX_LEGACY_SUBSLICES	6
>> >
>> > instead of calling the old legacy, maybe just add the XEHP_ prefix to
>> > the new ones?
>>
>> Maybe a "HSW_" prefix on the old ones would be better?  People still use
>> the termm 'subslice' in casual discussion when talking about DSS, so I
>> want to somehow distinguish that what we're talking about here is a
>> different, older design than we have on modern platforms.
>
>Hmm, or maybe just "GEN_MAX_SUBSLICES_PER_LEGACY_SLICE" to tie it into
>the slice definition above?

I'm not too fond of calling it "legacy" when everywhere else in the driver
we just use the platform as prefix/suffix. Some may see legacy as
< ver 12, others as 12.50, etc.

Well... but I will leave that up to you if you are convinced one is
better than the other.

thanks
Lucas De Marchi

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Ville Syrjälä]

On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> >> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> >> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> >> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
> >> > > Instead we now have a single pool of subslices (which are now referred
> >> > > to as "DSS") that different hardware units have different ways of
> >> > > grouping ("compute slices," "geometry slices," etc.).  For the purposes
> >> > > of topology representation, we treat Xe_HP-based platforms as having a
> >> > > single slice that contains all of the platform's DSS.  There's no need
> >> > > to allocate storage space for (max legacy slices * max dss); let's
> >> > > update some of our macros to minimize the storage requirement for sseu
> >> > > topology.  We'll also document some of the constants to make it a little
> >> > > bit more clear what they represent.
> >> > >
> >> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> > > ---
> >> > > drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
> >> > > drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
> >> > > 2 files changed, 36 insertions(+), 13 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> >> > > index 4fbf45a74ec0..f9e246004bc0 100644
> >> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> >> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> >> > > @@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
> >> > >
> >> > > #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
> >> > > 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
> >> > > -	     (iter_) < GEN_MAX_SUBSLICES; \
> >> > > +	     (iter_) < GEN_SS_MASK_SIZE; \
> >> > > 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
> >> > > 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
> >> > > 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
> >> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> >> > > index 8a79cd8eaab4..4f59eadbb61a 100644
> >> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> >> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> >> > > @@ -15,26 +15,49 @@ struct drm_i915_private;
> >> > > struct intel_gt;
> >> > > struct drm_printer;
> >> > >
> >> > > -#define GEN_MAX_SLICES		(3) /* SKL upper bound */
> >> > > -#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
> >> > > -#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> >> > > -#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> >> > > -#define GEN_MAX_EUS		(16) /* TGL upper bound */
> >> > > -#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
> >> > > +/*
> >> > > + * Maximum number of legacy slices.  Legacy slices no longer exist starting on
> >> > > + * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
> >> > > + * concept and are not expressed through fusing).
> >> > > + */
> >> > > +#define GEN_MAX_LEGACY_SLICES		3
> >> > > +
> >> > > +/*
> >> > > + * Maximum number of subslices that can exist within a legacy slice.  This is
> >> > > + * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
> >> > > + * value below).
> >> > > + */
> >> > > +#define GEN_MAX_LEGACY_SUBSLICES	6
> >> >
> >> > instead of calling the old legacy, maybe just add the XEHP_ prefix to
> >> > the new ones?
> >>
> >> Maybe a "HSW_" prefix on the old ones would be better?  People still use
> >> the termm 'subslice' in casual discussion when talking about DSS, so I
> >> want to somehow distinguish that what we're talking about here is a
> >> different, older design than we have on modern platforms.
> >
> >Hmm, or maybe just "GEN_MAX_SUBSLICES_PER_LEGACY_SLICE" to tie it into
> >the slice definition above?
> 
> I'm not too fond of calling it "legacy" when everywhere else in the driver
> we just use the platform as prefix/suffix. Some may see legacy as
> < ver 12, others as 12.50, etc.

Everything will become legacy at some point. This kind of naming
scheme falls apart when the next shiny new thing comes around
and we end up with multiple different leagacies. Are we going
to have ANCIENT_LEGACY, RECENT_LEGACY, NOT_YET_LEGACY etc?

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 1/2] drm/i915/sseu: Don't overallocate subslice storage

[Matt Roper]

On Fri, Mar 11, 2022 at 11:01:01PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 11, 2022 at 12:52:33PM -0800, Lucas De Marchi wrote:
> > On Fri, Mar 11, 2022 at 12:43:40PM -0800, Matt Roper wrote:
> > >On Fri, Mar 11, 2022 at 12:38:17PM -0800, Matt Roper wrote:
> > >> On Fri, Mar 11, 2022 at 11:00:09AM -0800, Lucas De Marchi wrote:
> > >> > On Thu, Mar 10, 2022 at 10:15:42PM -0800, Matt Roper wrote:
> > >> > > Xe_HP removed "slice" as a first-class unit in the hardware design.
> > >> > > Instead we now have a single pool of subslices (which are now referred
> > >> > > to as "DSS") that different hardware units have different ways of
> > >> > > grouping ("compute slices," "geometry slices," etc.).  For the purposes
> > >> > > of topology representation, we treat Xe_HP-based platforms as having a
> > >> > > single slice that contains all of the platform's DSS.  There's no need
> > >> > > to allocate storage space for (max legacy slices * max dss); let's
> > >> > > update some of our macros to minimize the storage requirement for sseu
> > >> > > topology.  We'll also document some of the constants to make it a little
> > >> > > bit more clear what they represent.
> > >> > >
> > >> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > >> > > ---
> > >> > > drivers/gpu/drm/i915/gt/intel_engine_types.h |  2 +-
> > >> > > drivers/gpu/drm/i915/gt/intel_sseu.h         | 47 +++++++++++++++-----
> > >> > > 2 files changed, 36 insertions(+), 13 deletions(-)
> > >> > >
> > >> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > >> > > index 4fbf45a74ec0..f9e246004bc0 100644
> > >> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > >> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > >> > > @@ -645,7 +645,7 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
> > >> > >
> > >> > > #define for_each_instdone_gslice_dss_xehp(dev_priv_, sseu_, iter_, gslice_, dss_) \
> > >> > > 	for ((iter_) = 0, (gslice_) = 0, (dss_) = 0; \
> > >> > > -	     (iter_) < GEN_MAX_SUBSLICES; \
> > >> > > +	     (iter_) < GEN_SS_MASK_SIZE; \
> > >> > > 	     (iter_)++, (gslice_) = (iter_) / GEN_DSS_PER_GSLICE, \
> > >> > > 	     (dss_) = (iter_) % GEN_DSS_PER_GSLICE) \
> > >> > > 		for_each_if(intel_sseu_has_subslice((sseu_), 0, (iter_)))
> > >> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > >> > > index 8a79cd8eaab4..4f59eadbb61a 100644
> > >> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > >> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > >> > > @@ -15,26 +15,49 @@ struct drm_i915_private;
> > >> > > struct intel_gt;
> > >> > > struct drm_printer;
> > >> > >
> > >> > > -#define GEN_MAX_SLICES		(3) /* SKL upper bound */
> > >> > > -#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
> > >> > > -#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > >> > > -#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
> > >> > > -#define GEN_MAX_EUS		(16) /* TGL upper bound */
> > >> > > -#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS)
> > >> > > +/*
> > >> > > + * Maximum number of legacy slices.  Legacy slices no longer exist starting on
> > >> > > + * Xe_HP ("gslices," "cslices," etc. on Xe_HP and beyond are a different
> > >> > > + * concept and are not expressed through fusing).
> > >> > > + */
> > >> > > +#define GEN_MAX_LEGACY_SLICES		3
> > >> > > +
> > >> > > +/*
> > >> > > + * Maximum number of subslices that can exist within a legacy slice.  This is
> > >> > > + * only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the GEN_MAX_DSS
> > >> > > + * value below).
> > >> > > + */
> > >> > > +#define GEN_MAX_LEGACY_SUBSLICES	6
> > >> >
> > >> > instead of calling the old legacy, maybe just add the XEHP_ prefix to
> > >> > the new ones?
> > >>
> > >> Maybe a "HSW_" prefix on the old ones would be better?  People still use
> > >> the termm 'subslice' in casual discussion when talking about DSS, so I
> > >> want to somehow distinguish that what we're talking about here is a
> > >> different, older design than we have on modern platforms.
> > >
> > >Hmm, or maybe just "GEN_MAX_SUBSLICES_PER_LEGACY_SLICE" to tie it into
> > >the slice definition above?
> > 
> > I'm not too fond of calling it "legacy" when everywhere else in the driver
> > we just use the platform as prefix/suffix. Some may see legacy as
> > < ver 12, others as 12.50, etc.
> 
> Everything will become legacy at some point. This kind of naming
> scheme falls apart when the next shiny new thing comes around
> and we end up with multiple different leagacies. Are we going
> to have ANCIENT_LEGACY, RECENT_LEGACY, NOT_YET_LEGACY etc?

Well that's kind of the point --- there is no shiny new thing and never
will be.  "slice" is gone for good and the places we use the term are
_not_ the same thing as similar-sounding terms like gslice, cslice,
mslice, etc.

But I'll go ahead and switch it to "HSW_" and hope people figure out
that it stops being a meaningful concept Xe_HP.


Matt

> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795