* [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups
@ 2022-03-17 18:36 Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions Jani Nikula
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Clean up dmc code to hide details better in intel_dmc.c.
Jani Nikula (8):
drm/i915/dmc: simplify intel_dmc_load_program() conditions
drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
drm/i915/dmc: move dmc debugfs to intel_dmc.c
drm/i915/dmc: fix i915_reg_t usage
drm/i915/dmc: don't register DMC debugfs file if there's no DMC
drm/i915/dmc: abstract GPU error state dump
drm/i915/dmc: hide DMC version macros
drm/i915/dmc: split out dmc registers to a separate file
.../drm/i915/display/intel_display_debugfs.c | 75 +----------
.../drm/i915/display/intel_display_power.c | 18 +--
drivers/gpu/drm/i915/display/intel_dmc.c | 125 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dmc.h | 10 +-
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 21 ---
8 files changed, 158 insertions(+), 133 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
--
2.30.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:35 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c Jani Nikula
` (10 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
intel_dmc_load_program() is only ever called when
intel_dmc_has_payload() is true. Move the condition within
intel_dmc_load_program() to let it be called directly.
Also note that intel_dmc_has_payload() will always return false when
HAS_DMC() is false. Remove the redundant check.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dmc.c | 11 +----------
2 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3dc859032bac..b3efe345567f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5387,7 +5387,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
}
@@ -5454,7 +5454,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
}
@@ -5618,7 +5618,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
if (IS_DG2(dev_priv))
intel_snps_phy_wait_for_calibration(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index a719c0f379ba..66fd69259e73 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -276,17 +276,8 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
struct intel_dmc *dmc = &dev_priv->dmc;
u32 id, i;
- if (!HAS_DMC(dev_priv)) {
- drm_err(&dev_priv->drm,
- "No DMC support available for this platform\n");
- return;
- }
-
- if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
- drm_err(&dev_priv->drm,
- "Tried to program CSR with empty payload\n");
+ if (!intel_dmc_has_payload(dev_priv))
return;
- }
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:36 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs " Jani Nikula
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Start localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 12 ------------
drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b3efe345567f..6a5695008f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -905,18 +905,6 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
intel_pps_unlock_regs_wa(dev_priv);
}
-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
-{
- drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv,
- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
- "DMC program storage start is NULL\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
- "DMC SSP Base Not fine\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
- "DMC HTP Not fine\n");
-}
-
/**
* intel_display_power_set_target_dc_state - Set target dc state.
* @dev_priv: i915 device
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 66fd69259e73..63ae16622c3e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -305,6 +305,17 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
gen9_set_dc_state_debugmask(dev_priv);
}
+void assert_dmc_loaded(struct drm_i915_private *i915)
+{
+ drm_WARN_ONCE(&i915->drm,
+ !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ "DMC program storage start is NULL\n");
+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
+ "DMC SSP Base Not fine\n");
+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
+ "DMC HTP Not fine\n");
+}
+
static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
const struct stepping_info *si)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 7c590309a3a9..326f80ad0f31 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -55,4 +55,6 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
bool intel_dmc_has_payload(struct drm_i915_private *i915);
+void assert_dmc_loaded(struct drm_i915_private *i915);
+
#endif /* __INTEL_DMC_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs to intel_dmc.c
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:41 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage Jani Nikula
` (8 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Continue localizing DMC register and data access to intel_dmc.c.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 75 +----------------
drivers/gpu/drm/i915/display/intel_dmc.c | 83 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 1 +
3 files changed, 85 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index e0a126e7ebb8..b43ac1c20653 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -436,79 +436,6 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
return 0;
}
-static int i915_dmc_info(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- intel_wakeref_t wakeref;
- struct intel_dmc *dmc;
- i915_reg_t dc5_reg, dc6_reg = {};
-
- if (!HAS_DMC(dev_priv))
- return -ENODEV;
-
- dmc = &dev_priv->dmc;
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
-
- seq_printf(m, "fw loaded: %s\n",
- str_yes_no(intel_dmc_has_payload(dev_priv)));
- seq_printf(m, "path: %s\n", dmc->fw_path);
- seq_printf(m, "Pipe A fw support: %s\n",
- str_yes_no(GRAPHICS_VER(dev_priv) >= 12));
- seq_printf(m, "Pipe A fw loaded: %s\n",
- str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
- seq_printf(m, "Pipe B fw support: %s\n",
- str_yes_no(IS_ALDERLAKE_P(dev_priv)));
- seq_printf(m, "Pipe B fw loaded: %s\n",
- str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
-
- if (!intel_dmc_has_payload(dev_priv))
- goto out;
-
- seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
- DMC_VERSION_MINOR(dmc->version));
-
- if (DISPLAY_VER(dev_priv) >= 12) {
- if (IS_DGFX(dev_priv)) {
- dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
- } else {
- dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
- dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
- }
-
- /*
- * NOTE: DMC_DEBUG3 is a general purpose reg.
- * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
- * reg for DC3CO debugging and validation,
- * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
- */
- seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv, IS_DGFX(dev_priv) ?
- DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
- } else {
- dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
- SKL_DMC_DC3_DC5_COUNT;
- if (!IS_GEMINILAKE(dev_priv) && !IS_BROXTON(dev_priv))
- dc6_reg = SKL_DMC_DC5_DC6_COUNT;
- }
-
- seq_printf(m, "DC3 -> DC5 count: %d\n",
- intel_de_read(dev_priv, dc5_reg));
- if (dc6_reg.reg)
- seq_printf(m, "DC5 -> DC6 count: %d\n",
- intel_de_read(dev_priv, dc6_reg));
-
-out:
- seq_printf(m, "program base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
- seq_printf(m, "ssp base: 0x%08x\n",
- intel_de_read(dev_priv, DMC_SSP_BASE));
- seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
-
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-
- return 0;
-}
-
static void intel_seq_print_mode(struct seq_file *m, int tabs,
const struct drm_display_mode *mode)
{
@@ -1952,7 +1879,6 @@ static const struct drm_info_list intel_display_debugfs_list[] = {
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_power_domain_info", i915_power_domain_info, 0},
- {"i915_dmc_info", i915_dmc_info, 0},
{"i915_display_info", i915_display_info, 0},
{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
{"i915_dp_mst_info", i915_dp_mst_info, 0},
@@ -1996,6 +1922,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
ARRAY_SIZE(intel_display_debugfs_list),
minor->debugfs_root, minor);
+ intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 63ae16622c3e..2e11725a0828 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -810,3 +810,86 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
for (id = 0; id < DMC_FW_MAX; id++)
kfree(dev_priv->dmc.dmc_info[id].payload);
}
+
+static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = m->private;
+ intel_wakeref_t wakeref;
+ struct intel_dmc *dmc;
+ i915_reg_t dc5_reg, dc6_reg = {};
+
+ if (!HAS_DMC(i915))
+ return -ENODEV;
+
+ dmc = &i915->dmc;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ seq_printf(m, "fw loaded: %s\n",
+ str_yes_no(intel_dmc_has_payload(i915)));
+ seq_printf(m, "path: %s\n", dmc->fw_path);
+ seq_printf(m, "Pipe A fw support: %s\n",
+ str_yes_no(GRAPHICS_VER(i915) >= 12));
+ seq_printf(m, "Pipe A fw loaded: %s\n",
+ str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload));
+ seq_printf(m, "Pipe B fw support: %s\n",
+ str_yes_no(IS_ALDERLAKE_P(i915)));
+ seq_printf(m, "Pipe B fw loaded: %s\n",
+ str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload));
+
+ if (!intel_dmc_has_payload(i915))
+ goto out;
+
+ seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
+
+ if (DISPLAY_VER(i915) >= 12) {
+ if (IS_DGFX(i915)) {
+ dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+ } else {
+ dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+ dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+ }
+
+ /*
+ * NOTE: DMC_DEBUG3 is a general purpose reg.
+ * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
+ * reg for DC3CO debugging and validation,
+ * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
+ */
+ seq_printf(m, "DC3CO count: %d\n",
+ intel_de_read(i915, IS_DGFX(i915) ?
+ DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
+ } else {
+ dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT :
+ SKL_DMC_DC3_DC5_COUNT;
+ if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915))
+ dc6_reg = SKL_DMC_DC5_DC6_COUNT;
+ }
+
+ seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
+ if (dc6_reg.reg)
+ seq_printf(m, "DC5 -> DC6 count: %d\n",
+ intel_de_read(i915, dc6_reg));
+
+out:
+ seq_printf(m, "program base: 0x%08x\n",
+ intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
+ seq_printf(m, "ssp base: 0x%08x\n",
+ intel_de_read(i915, DMC_SSP_BASE));
+ seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL));
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status);
+
+void intel_dmc_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
+ i915, &intel_dmc_debugfs_status_fops);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 326f80ad0f31..b9f608057700 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -54,6 +54,7 @@ void intel_dmc_ucode_fini(struct drm_i915_private *i915);
void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
bool intel_dmc_has_payload(struct drm_i915_private *i915);
+void intel_dmc_debugfs_register(struct drm_i915_private *i915);
void assert_dmc_loaded(struct drm_i915_private *i915);
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (2 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs " Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:43 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC Jani Nikula
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
i915_reg_t is supposed to be a somewhat opaque data type, not to be
looked inside.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2e11725a0828..5de13f978e57 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -816,7 +816,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
struct drm_i915_private *i915 = m->private;
intel_wakeref_t wakeref;
struct intel_dmc *dmc;
- i915_reg_t dc5_reg, dc6_reg = {};
+ i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
if (!HAS_DMC(i915))
return -ENODEV;
@@ -868,7 +868,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
}
seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
- if (dc6_reg.reg)
+ if (i915_mmio_reg_valid(dc6_reg))
seq_printf(m, "DC5 -> DC6 count: %d\n",
intel_de_read(i915, dc6_reg));
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (3 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:55 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump Jani Nikula
` (6 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Register the DMC debugfs file only on platforms that support
DMC. There's no point in having a no-op debugfs file.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5de13f978e57..8dfa2aa9f8bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -818,9 +818,6 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
struct intel_dmc *dmc;
i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
- if (!HAS_DMC(i915))
- return -ENODEV;
-
dmc = &i915->dmc;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
@@ -890,6 +887,9 @@ void intel_dmc_debugfs_register(struct drm_i915_private *i915)
{
struct drm_minor *minor = i915->drm.primary;
+ if (!HAS_DMC(i915))
+ return;
+
debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
i915, &intel_dmc_debugfs_status_fops);
}
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (4 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:56 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros Jani Nikula
` (5 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Only intel_dmc.c should be accessing dmc details directly.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 10 +---------
3 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 8dfa2aa9f8bd..86d48029d488 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -811,6 +811,21 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
kfree(dev_priv->dmc.dmc_info[id].payload);
}
+void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
+ struct drm_i915_private *i915)
+{
+ struct intel_dmc *dmc = &i915->dmc;
+
+ if (!HAS_DMC(i915))
+ return;
+
+ i915_error_printf(m, "DMC loaded: %s\n",
+ str_yes_no(intel_dmc_has_payload(i915)));
+ i915_error_printf(m, "DMC fw version: %d.%d\n",
+ DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
+}
+
static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = m->private;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b9f608057700..dd8880d2cbed 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -10,6 +10,7 @@
#include "intel_wakeref.h"
#include <linux/workqueue.h>
+struct drm_i915_error_state_buf;
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
@@ -55,6 +56,8 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
bool intel_dmc_has_payload(struct drm_i915_private *i915);
void intel_dmc_debugfs_register(struct drm_i915_private *i915);
+void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
+ struct drm_i915_private *i915);
void assert_dmc_loaded(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index a8acc6fbb299..fb3baf4af792 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -825,15 +825,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
- if (HAS_DMC(m->i915)) {
- struct intel_dmc *dmc = &m->i915->dmc;
-
- err_printf(m, "DMC loaded: %s\n",
- str_yes_no(intel_dmc_has_payload(m->i915) != 0));
- err_printf(m, "DMC fw version: %d.%d\n",
- DMC_VERSION_MAJOR(dmc->version),
- DMC_VERSION_MINOR(dmc->version));
- }
+ intel_dmc_print_error_state(m, m->i915);
err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (5 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:57 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file Jani Nikula
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The macros are now only needed within intel_dmc.c, so move them there.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++++
drivers/gpu/drm/i915/display/intel_dmc.h | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 86d48029d488..7b7c757ce0ee 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -37,6 +37,10 @@
* low-power state and comes back to normal.
*/
+#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
+#define DMC_VERSION_MAJOR(version) ((version) >> 16)
+#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
+
#define DMC_PATH(platform, major, minor) \
"i915/" \
__stringify(platform) "_dmc_ver" \
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index dd8880d2cbed..41091aee3b47 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -13,10 +13,6 @@
struct drm_i915_error_state_buf;
struct drm_i915_private;
-#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
-#define DMC_VERSION_MAJOR(version) ((version) >> 16)
-#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
-
enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (6 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros Jani Nikula
@ 2022-03-17 18:36 ` Jani Nikula
2022-03-17 19:59 ` Lucas De Marchi
2022-03-17 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: cleanups Patchwork
` (3 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-17 18:36 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Clean up the massive i915_reg.h a bit with this isolated set of
registers.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++++++++++++++++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 21 -------------
4 files changed, 33 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 7b7c757ce0ee..4d292a016ca0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_dmc.h"
+#include "intel_dmc_regs.h"
/**
* DOC: DMC Firmware Support
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
new file mode 100644
index 000000000000..e436fe93a2da
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DMC_REGS_H__
+#define __INTEL_DMC_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
+#define DMC_HTP_ADDR_SKL 0x00500034
+#define DMC_SSP_BASE _MMIO(0x8F074)
+#define DMC_HTP_SKL _MMIO(0x8F004)
+#define DMC_LAST_WRITE _MMIO(0x8F034)
+#define DMC_LAST_WRITE_VALUE 0xc003b400
+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
+#define DMC_MMIO_START_RANGE 0x80000
+#define DMC_MMIO_END_RANGE 0x8FFFF
+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
+#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
+#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
+
+#define TGL_DMC_DEBUG3 _MMIO(0x101090)
+#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
+
+#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 0ee3ecc83234..57b0f4977760 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
#include "display/intel_display_types.h"
+#include "display/intel_dmc_regs.h"
#include "display/intel_fbc.h"
#include "display/vlv_dsi_pll_regs.h"
#include "gt/intel_gt_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a10b00a585b..25e981406170 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5493,27 +5493,6 @@
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
-/* DMC */
-#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
-#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
-#define DMC_HTP_ADDR_SKL 0x00500034
-#define DMC_SSP_BASE _MMIO(0x8F074)
-#define DMC_HTP_SKL _MMIO(0x8F004)
-#define DMC_LAST_WRITE _MMIO(0x8F034)
-#define DMC_LAST_WRITE_VALUE 0xc003b400
-/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
-#define DMC_MMIO_START_RANGE 0x80000
-#define DMC_MMIO_END_RANGE 0x8FFFF
-#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
-#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
-#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
-#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
-#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
-#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
-
-#define TGL_DMC_DEBUG3 _MMIO(0x101090)
-#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
-
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
--
2.30.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions
2022-03-17 18:36 ` [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions Jani Nikula
@ 2022-03-17 19:35 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:35 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:13PM +0200, Jani Nikula wrote:
>intel_dmc_load_program() is only ever called when
>intel_dmc_has_payload() is true. Move the condition within
>intel_dmc_load_program() to let it be called directly.
>
>Also note that intel_dmc_has_payload() will always return false when
>HAS_DMC() is false. Remove the redundant check.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_dmc.c | 11 +----------
> 2 files changed, 4 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 3dc859032bac..b3efe345567f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -5387,7 +5387,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> gen9_dbuf_enable(dev_priv);
>
>- if (resume && intel_dmc_has_payload(dev_priv))
>+ if (resume)
> intel_dmc_load_program(dev_priv);
> }
>
>@@ -5454,7 +5454,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> gen9_dbuf_enable(dev_priv);
>
>- if (resume && intel_dmc_has_payload(dev_priv))
>+ if (resume)
> intel_dmc_load_program(dev_priv);
> }
>
>@@ -5618,7 +5618,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> if (IS_DG2(dev_priv))
> intel_snps_phy_wait_for_calibration(dev_priv);
>
>- if (resume && intel_dmc_has_payload(dev_priv))
>+ if (resume)
> intel_dmc_load_program(dev_priv);
>
> /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index a719c0f379ba..66fd69259e73 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -276,17 +276,8 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> struct intel_dmc *dmc = &dev_priv->dmc;
> u32 id, i;
>
>- if (!HAS_DMC(dev_priv)) {
>- drm_err(&dev_priv->drm,
>- "No DMC support available for this platform\n");
>- return;
>- }
>-
>- if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
>- drm_err(&dev_priv->drm,
>- "Tried to program CSR with empty payload\n");
>+ if (!intel_dmc_has_payload(dev_priv))
> return;
>- }
>
> assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
>--
>2.30.2
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
2022-03-17 18:36 ` [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c Jani Nikula
@ 2022-03-17 19:36 ` Lucas De Marchi
2022-03-18 9:19 ` Jani Nikula
0 siblings, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
>Start localizing DMC register and data access to intel_dmc.c.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ------------
> drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
> 3 files changed, 13 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index b3efe345567f..6a5695008f7c 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -905,18 +905,6 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> intel_pps_unlock_regs_wa(dev_priv);
> }
>
>-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
>-{
>- drm_WARN_ONCE(&dev_priv->drm,
>- !intel_de_read(dev_priv,
>- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>- "DMC program storage start is NULL\n");
>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>- "DMC SSP Base Not fine\n");
>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>- "DMC HTP Not fine\n");
>-}
>-
> /**
> * intel_display_power_set_target_dc_state - Set target dc state.
> * @dev_priv: i915 device
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 66fd69259e73..63ae16622c3e 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -305,6 +305,17 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> gen9_set_dc_state_debugmask(dev_priv);
> }
>
>+void assert_dmc_loaded(struct drm_i915_private *i915)
>+{
>+ drm_WARN_ONCE(&i915->drm,
>+ !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>+ "DMC program storage start is NULL\n");
>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
>+ "DMC SSP Base Not fine\n");
>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
>+ "DMC HTP Not fine\n");
>+}
>+
> static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
> const struct stepping_info *si)
> {
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index 7c590309a3a9..326f80ad0f31 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -55,4 +55,6 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> bool intel_dmc_has_payload(struct drm_i915_private *i915);
>
>+void assert_dmc_loaded(struct drm_i915_private *i915);
intel_dmc_assert_loaded()?
Lucas De Marchi
>+
> #endif /* __INTEL_DMC_H__ */
>--
>2.30.2
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs to intel_dmc.c
2022-03-17 18:36 ` [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs " Jani Nikula
@ 2022-03-17 19:41 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:15PM +0200, Jani Nikula wrote:
>Continue localizing DMC register and data access to intel_dmc.c.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage
2022-03-17 18:36 ` [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage Jani Nikula
@ 2022-03-17 19:43 ` Lucas De Marchi
2022-03-18 9:21 ` Jani Nikula
0 siblings, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:16PM +0200, Jani Nikula wrote:
>i915_reg_t is supposed to be a somewhat opaque data type, not to be
>looked inside.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
but maybe also already clean up the remaining one?
$ git grep "i915_reg_t.*= *{ *}"
drivers/gpu/drm/i915/display/intel_display_debugfs.c: i915_reg_t dc5_reg, dc6_reg = {};
drivers/gpu/drm/i915/gt/intel_ring_submission.c: i915_reg_t last_reg = {}; /* keep gcc quiet */
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 2e11725a0828..5de13f978e57 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -816,7 +816,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> struct drm_i915_private *i915 = m->private;
> intel_wakeref_t wakeref;
> struct intel_dmc *dmc;
>- i915_reg_t dc5_reg, dc6_reg = {};
>+ i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>
> if (!HAS_DMC(i915))
> return -ENODEV;
>@@ -868,7 +868,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> }
>
> seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
>- if (dc6_reg.reg)
>+ if (i915_mmio_reg_valid(dc6_reg))
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> intel_de_read(i915, dc6_reg));
>
>--
>2.30.2
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC
2022-03-17 18:36 ` [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC Jani Nikula
@ 2022-03-17 19:55 ` Lucas De Marchi
2022-03-18 9:22 ` Jani Nikula
0 siblings, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:17PM +0200, Jani Nikula wrote:
>Register the DMC debugfs file only on platforms that support
>DMC. There's no point in having a no-op debugfs file.
It seems this would not change much the behavior (fail on open vs fail
on read). But the code in igt is suspicious:
bool igt_pm_dmc_loaded(int debugfs)
{
char buf[15];
int len;
len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
if (len < 0)
return true; /* no CSR support, no DMC requirement */
From a quick inspection of igt_sysfs_read() it seems it would just
return 0 if there's nothing to be read. And it would return < 0 on
failure to open the file.
These would be the affected tests:
tests/i915/i915_pm_rpm.c:
tests/i915/i915_pm_lpsp.c:
tests/i915/i915_pm_dc.c:
igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
Lucas De Marchi
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 5de13f978e57..8dfa2aa9f8bd 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -818,9 +818,6 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> struct intel_dmc *dmc;
> i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>
>- if (!HAS_DMC(i915))
>- return -ENODEV;
>-
> dmc = &i915->dmc;
>
> wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>@@ -890,6 +887,9 @@ void intel_dmc_debugfs_register(struct drm_i915_private *i915)
> {
> struct drm_minor *minor = i915->drm.primary;
>
>+ if (!HAS_DMC(i915))
>+ return;
>+
> debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
> i915, &intel_dmc_debugfs_status_fops);
> }
>--
>2.30.2
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump
2022-03-17 18:36 ` [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump Jani Nikula
@ 2022-03-17 19:56 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:18PM +0200, Jani Nikula wrote:
>Only intel_dmc.c should be accessing dmc details directly.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros
2022-03-17 18:36 ` [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros Jani Nikula
@ 2022-03-17 19:57 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:19PM +0200, Jani Nikula wrote:
>The macros are now only needed within intel_dmc.c, so move them there.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file
2022-03-17 18:36 ` [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file Jani Nikula
@ 2022-03-17 19:59 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-17 19:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Mar 17, 2022 at 08:36:20PM +0200, Jani Nikula wrote:
>Clean up the massive i915_reg.h a bit with this isolated set of
>registers.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 1 +
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 31 +++++++++++++++++++
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 21 -------------
> 4 files changed, 33 insertions(+), 21 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_regs.h
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 7b7c757ce0ee..4d292a016ca0 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -28,6 +28,7 @@
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_dmc.h"
>+#include "intel_dmc_regs.h"
>
> /**
> * DOC: DMC Firmware Support
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>new file mode 100644
>index 000000000000..e436fe93a2da
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>@@ -0,0 +1,31 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_DMC_REGS_H__
>+#define __INTEL_DMC_REGS_H__
>+
>+#include "i915_reg_defs.h"
>+
>+#define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
>+#define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0
>+#define DMC_HTP_ADDR_SKL 0x00500034
>+#define DMC_SSP_BASE _MMIO(0x8F074)
>+#define DMC_HTP_SKL _MMIO(0x8F004)
>+#define DMC_LAST_WRITE _MMIO(0x8F034)
>+#define DMC_LAST_WRITE_VALUE 0xc003b400
>+/* MMIO address range for DMC program (0x80000 - 0x82FFF) */
this comment seems outdated. Or at least unneeded
Anyway:
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>+#define DMC_MMIO_START_RANGE 0x80000
>+#define DMC_MMIO_END_RANGE 0x8FFFF
>+#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
>+#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
>+#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
>+#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
>+#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
>+#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
>+
>+#define TGL_DMC_DEBUG3 _MMIO(0x101090)
>+#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
>+
>+#endif /* __INTEL_DMC_REGS_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: cleanups
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (7 preceding siblings ...)
2022-03-17 18:36 ` [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file Jani Nikula
@ 2022-03-17 20:36 ` Patchwork
2022-03-17 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2022-03-17 20:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
148ae63a423d drm/i915/dmc: simplify intel_dmc_load_program() conditions
f5b3417a7183 drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
-:44: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:311:
+ !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
total: 0 errors, 1 warnings, 0 checks, 41 lines checked
f22b25aa0be3 drm/i915/dmc: move dmc debugfs to intel_dmc.c
2a37260cdcf5 drm/i915/dmc: fix i915_reg_t usage
16d7cf76f90d drm/i915/dmc: don't register DMC debugfs file if there's no DMC
1b7ec1b7a556 drm/i915/dmc: abstract GPU error state dump
2c93821f352b drm/i915/dmc: hide DMC version macros
15377b5193fb drm/i915/dmc: split out dmc registers to a separate file
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#25:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 72 lines checked
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dmc: cleanups
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (8 preceding siblings ...)
2022-03-17 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: cleanups Patchwork
@ 2022-03-17 20:37 ` Patchwork
2022-03-17 21:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-18 1:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2022-03-17 20:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dmc: cleanups
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (9 preceding siblings ...)
2022-03-17 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-17 21:16 ` Patchwork
2022-03-18 1:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2022-03-17 21:16 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6686 bytes --]
== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11378 -> Patchwork_22597
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/index.html
Participating hosts (46 -> 44)
------------------------------
Additional (1): fi-pnv-d510
Missing (3): bat-dg2-8 fi-bsw-cyan fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22597:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@evict:
- {bat-rpls-2}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/bat-rpls-2/igt@i915_selftest@live@evict.html
Known issues
------------
Here are the changes found in Patchwork_22597 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][2] -> [INCOMPLETE][3] ([i915#2373])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][4] -> [INCOMPLETE][5] ([i915#3303])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][6] ([i915#3921])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#5341])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-bdw-5557u: NOTRUN -> [SKIP][9] ([fdo#109271]) +14 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][10] ([fdo#109271]) +57 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#1436] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][12] ([i915#3194]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][14] ([i915#4391]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/bat-rpls-2/igt@i915_module_load@reload.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/bat-rpls-2/igt@i915_module_load@reload.html
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [INCOMPLETE][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][18] ([i915#3576]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/bat-adlp-6/igt@kms_busy@basic@modeset.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/bat-adlp-6/igt@kms_busy@basic@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-------------
* Linux: CI_DRM_11378 -> Patchwork_22597
CI-20190529: 20190529
CI_DRM_11378: 3ec612f871c18232b04e5530e485992c76bf13a6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6385: f3df40281d93d5a63ee98fa30e90852d780673c9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22597: 15377b5193fbb3c89e40426719b44baba27a6185 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
15377b5193fb drm/i915/dmc: split out dmc registers to a separate file
2c93821f352b drm/i915/dmc: hide DMC version macros
1b7ec1b7a556 drm/i915/dmc: abstract GPU error state dump
16d7cf76f90d drm/i915/dmc: don't register DMC debugfs file if there's no DMC
2a37260cdcf5 drm/i915/dmc: fix i915_reg_t usage
f22b25aa0be3 drm/i915/dmc: move dmc debugfs to intel_dmc.c
f5b3417a7183 drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
148ae63a423d drm/i915/dmc: simplify intel_dmc_load_program() conditions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/index.html
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dmc: cleanups
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
` (10 preceding siblings ...)
2022-03-17 21:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-18 1:15 ` Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2022-03-18 1:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/dmc: cleanups
URL : https://patchwork.freedesktop.org/series/101499/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11378_full -> Patchwork_22597_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22597_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22597_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22597_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb4/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
Known issues
------------
Here are the changes found in Patchwork_22597_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb2/igt@feature_discovery@psr2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb1/igt@feature_discovery@psr2.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][5] ([i915#4991]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl6/igt@gem_create@create-massive.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063] / [i915#3648])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglb7/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb8/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-kbl: NOTRUN -> [DMESG-FAIL][10] ([i915#5076])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#4547])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl10/igt@gem_exec_capture@pi@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl7/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271]) +119 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@gem_exec_fair@basic-flow@rcs0.html
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
- shard-apl: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#2849])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([i915#1895])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb6/igt@gem_exec_whisper@basic-fds-forked-all.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb3/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][27] -> [SKIP][28] ([i915#2190])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#4613])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl4/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_pxp@create-valid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#4270])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#768])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109290])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#3323])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gen3_render_linear_blits:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109289])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb7/igt@gen3_render_linear_blits.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: NOTRUN -> [SKIP][35] ([i915#658])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][36] -> [FAIL][37] ([i915#454]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb2/igt@i915_pm_dc@dc6-dpms.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109293] / [fdo#109506])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-kbl6/igt@i915_suspend@fence-restore-untiled.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#5286]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#3743])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3777])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#1888] / [i915#3886])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk2/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3689])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb1/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +7 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl3/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@vga-edid-read:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_chamelium@vga-edid-read.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][55] ([i915#1319])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl3/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][56] ([i915#2105])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-256x256-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271]) +39 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][59] -> [FAIL][60] ([i915#72])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#2346])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109274] / [fdo#111825])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb1/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#2122]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-glk7/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a1-hdmi-a2.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
- shard-apl: [PASS][66] -> [FAIL][67] ([i915#79])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][68] -> [FAIL][69] ([i915#79])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][70] -> [DMESG-WARN][71] ([i915#180]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: NOTRUN -> [FAIL][72] ([i915#2122]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl3/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][73] -> [SKIP][74] ([i915#3701])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][75] -> [FAIL][76] ([i915#4911]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109280]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#1839])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#533])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][82] -> [FAIL][83] ([fdo#108145] / [i915#265])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][85] ([fdo#108145] / [i915#265])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#658]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl8/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][87] -> [SKIP][88] ([fdo#109441]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb2/igt@kms_psr@psr2_suspend.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@kms_psr@psr2_suspend.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][89] ([IGT#2])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl4/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][90] -> [DMESG-WARN][91] ([i915#180] / [i915#295])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@short-reads:
- shard-skl: [PASS][92] -> [FAIL][93] ([i915#51])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl10/igt@perf@short-reads.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl6/igt@perf@short-reads.html
* igt@prime_vgem@basic-userptr:
- shard-iclb: NOTRUN -> [SKIP][94] ([i915#3301])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@prime_vgem@basic-userptr.html
* igt@syncobj_timeline@transfer-timeline-point:
- shard-iclb: NOTRUN -> [DMESG-FAIL][95] ([i915#5098])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-iclb6/igt@syncobj_timeline@transfer-timeline-point.html
* igt@sysfs_clients@split-25:
- shard-skl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl9/igt@sysfs_clients@split-25.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [PASS][97] -> [WARN][98] ([i915#4055])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl7/igt@sysfs_heartbeat_interval@mixed@vcs0.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-skl: [PASS][99] -> [FAIL][100] ([i915#1731])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl7/igt@sysfs_heartbeat_interval@mixed@vecs0.html
* igt@tools_test@sysfs_l3_parity:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271]) +75 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][102] ([i915#180]) -> [PASS][103] +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][104] ([i915#232]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglb1/igt@gem_eio@kms.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglb6/igt@gem_eio@kms.html
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][106] ([i915#3063] / [i915#3648]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglu-4/igt@gem_eio@unwedge-stress.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglu-5/igt@gem_eio@unwedge-stress.html
- {shard-rkl}: [TIMEOUT][108] ([i915#3063]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-6/igt@gem_eio@unwedge-stress.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][110] ([i915#2846]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][112] ([i915#1436] / [i915#716]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-glk2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][114] ([i915#4281]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: ([SKIP][116], [SKIP][117]) ([fdo#109308]) -> [PASS][118]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@i915_pm_rpm@system-suspend-modeset.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-4/igt@i915_pm_rpm@system-suspend-modeset.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][119] ([i915#402]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-tglu-5/igt@kms_big_fb@linear-16bpp-rotate-0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-tglu-6/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- {shard-rkl}: ([SKIP][121], [SKIP][122]) ([i915#1845] / [i915#4098]) -> [PASS][123]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_big_fb@linear-64bpp-rotate-0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-0.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- {shard-rkl}: [SKIP][124] ([i915#1845] / [i915#4098]) -> [PASS][125] +6 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_color@pipe-a-gamma:
- {shard-rkl}: [SKIP][126] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_color@pipe-a-gamma.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_color@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen:
- {shard-rkl}: [SKIP][128] ([fdo#112022] / [i915#4070]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- {shard-rkl}: ([SKIP][130], [PASS][131]) ([fdo#112022] / [i915#4070]) -> [PASS][132]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
- {shard-rkl}: [SKIP][133] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {shard-rkl}: [SKIP][135] ([fdo#111825] / [i915#4070]) -> [PASS][136] +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- shard-skl: [DMESG-WARN][137] ([i915#1982]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-skl1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- {shard-rkl}: [SKIP][139] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][140] +3 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-iclb: [FAIL][141] ([i915#79]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11378/shard-iclb8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22597/index.html
[-- Attachment #2: Type: text/html, Size: 33313 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
2022-03-17 19:36 ` Lucas De Marchi
@ 2022-03-18 9:19 ` Jani Nikula
2022-03-18 14:49 ` Lucas De Marchi
0 siblings, 1 reply; 25+ messages in thread
From: Jani Nikula @ 2022-03-18 9:19 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, 17 Mar 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
>>Start localizing DMC register and data access to intel_dmc.c.
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ------------
>> drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++++++++++
>> drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
>> 3 files changed, 13 insertions(+), 12 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>index b3efe345567f..6a5695008f7c 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>@@ -905,18 +905,6 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
>> intel_pps_unlock_regs_wa(dev_priv);
>> }
>>
>>-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
>>-{
>>- drm_WARN_ONCE(&dev_priv->drm,
>>- !intel_de_read(dev_priv,
>>- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>>- "DMC program storage start is NULL\n");
>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>>- "DMC SSP Base Not fine\n");
>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>>- "DMC HTP Not fine\n");
>>-}
>>-
>> /**
>> * intel_display_power_set_target_dc_state - Set target dc state.
>> * @dev_priv: i915 device
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>>index 66fd69259e73..63ae16622c3e 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>@@ -305,6 +305,17 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
>> gen9_set_dc_state_debugmask(dev_priv);
>> }
>>
>>+void assert_dmc_loaded(struct drm_i915_private *i915)
>>+{
>>+ drm_WARN_ONCE(&i915->drm,
>>+ !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>>+ "DMC program storage start is NULL\n");
>>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
>>+ "DMC SSP Base Not fine\n");
>>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
>>+ "DMC HTP Not fine\n");
>>+}
>>+
>> static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
>> const struct stepping_info *si)
>> {
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>>index 7c590309a3a9..326f80ad0f31 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>>@@ -55,4 +55,6 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
>> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
>> bool intel_dmc_has_payload(struct drm_i915_private *i915);
>>
>>+void assert_dmc_loaded(struct drm_i915_private *i915);
>
>
> intel_dmc_assert_loaded()?
assert_dmc_loaded() is in line with the display asserts we have:
git grep assert_ -- drivers/gpu/drm/i915/display/*.h
I'd rather stick with that convention for now, and moving away from it
should be a separate conversation.
BR,
Jani.
>
> Lucas De Marchi
>
>>+
>> #endif /* __INTEL_DMC_H__ */
>>--
>>2.30.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage
2022-03-17 19:43 ` Lucas De Marchi
@ 2022-03-18 9:21 ` Jani Nikula
0 siblings, 0 replies; 25+ messages in thread
From: Jani Nikula @ 2022-03-18 9:21 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, 17 Mar 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Mar 17, 2022 at 08:36:16PM +0200, Jani Nikula wrote:
>>i915_reg_t is supposed to be a somewhat opaque data type, not to be
>>looked inside.
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> but maybe also already clean up the remaining one?
>
> $ git grep "i915_reg_t.*= *{ *}"
> drivers/gpu/drm/i915/display/intel_display_debugfs.c: i915_reg_t dc5_reg, dc6_reg = {};
So that's the one being fixed here.
> drivers/gpu/drm/i915/gt/intel_ring_submission.c: i915_reg_t last_reg = {}; /* keep gcc quiet */
I'll send a separate fix for that, not part of this series.
Thanks,
Jani.
>
> Lucas De Marchi
>
>>---
>> drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>>index 2e11725a0828..5de13f978e57 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>@@ -816,7 +816,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> struct drm_i915_private *i915 = m->private;
>> intel_wakeref_t wakeref;
>> struct intel_dmc *dmc;
>>- i915_reg_t dc5_reg, dc6_reg = {};
>>+ i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>>
>> if (!HAS_DMC(i915))
>> return -ENODEV;
>>@@ -868,7 +868,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> }
>>
>> seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg));
>>- if (dc6_reg.reg)
>>+ if (i915_mmio_reg_valid(dc6_reg))
>> seq_printf(m, "DC5 -> DC6 count: %d\n",
>> intel_de_read(i915, dc6_reg));
>>
>>--
>>2.30.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC
2022-03-17 19:55 ` Lucas De Marchi
@ 2022-03-18 9:22 ` Jani Nikula
0 siblings, 0 replies; 25+ messages in thread
From: Jani Nikula @ 2022-03-18 9:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, 17 Mar 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Mar 17, 2022 at 08:36:17PM +0200, Jani Nikula wrote:
>>Register the DMC debugfs file only on platforms that support
>>DMC. There's no point in having a no-op debugfs file.
>
> It seems this would not change much the behavior (fail on open vs fail
> on read). But the code in igt is suspicious:
>
>
> bool igt_pm_dmc_loaded(int debugfs)
> {
> char buf[15];
> int len;
>
> len = igt_sysfs_read(debugfs, "i915_dmc_info", buf, sizeof(buf) - 1);
> if (len < 0)
> return true; /* no CSR support, no DMC requirement */
>
> From a quick inspection of igt_sysfs_read() it seems it would just
> return 0 if there's nothing to be read. And it would return < 0 on
> failure to open the file.
>
> These would be the affected tests:
>
> tests/i915/i915_pm_rpm.c:
> tests/i915/i915_pm_lpsp.c:
> tests/i915/i915_pm_dc.c:
> igt_require(igt_pm_dmc_loaded(data.debugfs_fd));
Ok, I think I'll just drop this patch for now, don't have the time to go
down that rabbit hole...
Thanks,
Jani.
>
>
> Lucas De Marchi
>
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_dmc.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>>index 5de13f978e57..8dfa2aa9f8bd 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>@@ -818,9 +818,6 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> struct intel_dmc *dmc;
>> i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>>
>>- if (!HAS_DMC(i915))
>>- return -ENODEV;
>>-
>> dmc = &i915->dmc;
>>
>> wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>>@@ -890,6 +887,9 @@ void intel_dmc_debugfs_register(struct drm_i915_private *i915)
>> {
>> struct drm_minor *minor = i915->drm.primary;
>>
>>+ if (!HAS_DMC(i915))
>>+ return;
>>+
>> debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
>> i915, &intel_dmc_debugfs_status_fops);
>> }
>>--
>>2.30.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c
2022-03-18 9:19 ` Jani Nikula
@ 2022-03-18 14:49 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2022-03-18 14:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Mar 18, 2022 at 11:19:46AM +0200, Jani Nikula wrote:
>On Thu, 17 Mar 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Thu, Mar 17, 2022 at 08:36:14PM +0200, Jani Nikula wrote:
>>>Start localizing DMC register and data access to intel_dmc.c.
>>>
>>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>>---
>>> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ------------
>>> drivers/gpu/drm/i915/display/intel_dmc.c | 11 +++++++++++
>>> drivers/gpu/drm/i915/display/intel_dmc.h | 2 ++
>>> 3 files changed, 13 insertions(+), 12 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>index b3efe345567f..6a5695008f7c 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>>@@ -905,18 +905,6 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
>>> intel_pps_unlock_regs_wa(dev_priv);
>>> }
>>>
>>>-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
>>>-{
>>>- drm_WARN_ONCE(&dev_priv->drm,
>>>- !intel_de_read(dev_priv,
>>>- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>>>- "DMC program storage start is NULL\n");
>>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
>>>- "DMC SSP Base Not fine\n");
>>>- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>>>- "DMC HTP Not fine\n");
>>>-}
>>>-
>>> /**
>>> * intel_display_power_set_target_dc_state - Set target dc state.
>>> * @dev_priv: i915 device
>>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>>>index 66fd69259e73..63ae16622c3e 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>>@@ -305,6 +305,17 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
>>> gen9_set_dc_state_debugmask(dev_priv);
>>> }
>>>
>>>+void assert_dmc_loaded(struct drm_i915_private *i915)
>>>+{
>>>+ drm_WARN_ONCE(&i915->drm,
>>>+ !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>>>+ "DMC program storage start is NULL\n");
>>>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
>>>+ "DMC SSP Base Not fine\n");
>>>+ drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL),
>>>+ "DMC HTP Not fine\n");
>>>+}
>>>+
>>> static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
>>> const struct stepping_info *si)
>>> {
>>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>>>index 7c590309a3a9..326f80ad0f31 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>>>@@ -55,4 +55,6 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
>>> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
>>> bool intel_dmc_has_payload(struct drm_i915_private *i915);
>>>
>>>+void assert_dmc_loaded(struct drm_i915_private *i915);
>>
>>
>> intel_dmc_assert_loaded()?
>
>assert_dmc_loaded() is in line with the display asserts we have:
>
>git grep assert_ -- drivers/gpu/drm/i915/display/*.h
>
>I'd rather stick with that convention for now, and moving away from it
>should be a separate conversation.
ok, fair enough.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>
>BR,
>Jani.
>
>>
>> Lucas De Marchi
>>
>>>+
>>> #endif /* __INTEL_DMC_H__ */
>>>--
>>>2.30.2
>>>
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2022-03-18 14:49 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-17 18:36 [Intel-gfx] [PATCH 0/8] drm/i915/dmc: cleanups Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 1/8] drm/i915/dmc: simplify intel_dmc_load_program() conditions Jani Nikula
2022-03-17 19:35 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 2/8] drm/i915/dmc: move assert_dmc_loaded() to intel_dmc.c Jani Nikula
2022-03-17 19:36 ` Lucas De Marchi
2022-03-18 9:19 ` Jani Nikula
2022-03-18 14:49 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 3/8] drm/i915/dmc: move dmc debugfs " Jani Nikula
2022-03-17 19:41 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 4/8] drm/i915/dmc: fix i915_reg_t usage Jani Nikula
2022-03-17 19:43 ` Lucas De Marchi
2022-03-18 9:21 ` Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 5/8] drm/i915/dmc: don't register DMC debugfs file if there's no DMC Jani Nikula
2022-03-17 19:55 ` Lucas De Marchi
2022-03-18 9:22 ` Jani Nikula
2022-03-17 18:36 ` [Intel-gfx] [PATCH 6/8] drm/i915/dmc: abstract GPU error state dump Jani Nikula
2022-03-17 19:56 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 7/8] drm/i915/dmc: hide DMC version macros Jani Nikula
2022-03-17 19:57 ` Lucas De Marchi
2022-03-17 18:36 ` [Intel-gfx] [PATCH 8/8] drm/i915/dmc: split out dmc registers to a separate file Jani Nikula
2022-03-17 19:59 ` Lucas De Marchi
2022-03-17 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: cleanups Patchwork
2022-03-17 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-17 21:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-18 1:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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