* [PATCH] drm/i915: avoid concurrent writes to aux_inv
@ 2022-03-18 5:12 ` fei.yang
0 siblings, 0 replies; 4+ messages in thread
From: fei.yang @ 2022-03-18 5:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, Fei Yang, dri-devel, Tvrtko Ursulin
From: Fei Yang <fei.yang@intel.com>
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the rq->engine is not necessarily the engine
eventually carrying out the request, and potentially the engine
could even be a virtual one (with engine->instance being -1).
With the MMIO remap feature, we can actually set bit 17 of MI_LRI
instruction and let the hardware to figure out the local aux_inv
register at runtime to avoid invalidating auxiliary table for all
engines.
Bspec: 45728
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 42 +++++---------------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
2 files changed, 11 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 36148887c699..af5daaf934b5 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -165,30 +165,6 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
-static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
-{
- static const i915_reg_t vd[] = {
- GEN12_VD0_AUX_NV,
- GEN12_VD1_AUX_NV,
- GEN12_VD2_AUX_NV,
- GEN12_VD3_AUX_NV,
- };
-
- static const i915_reg_t ve[] = {
- GEN12_VE0_AUX_NV,
- GEN12_VE1_AUX_NV,
- };
-
- if (engine->class == VIDEO_DECODE_CLASS)
- return vd[engine->instance];
-
- if (engine->class == VIDEO_ENHANCEMENT_CLASS)
- return ve[engine->instance];
-
- GEM_BUG_ON("unknown aux_inv reg\n");
- return INVALID_MMIO_REG;
-}
-
static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
@@ -296,7 +272,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (!HAS_FLAT_CCS(rq->engine->i915)) {
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
- cmd += 2 * hweight32(aux_inv) + 2;
+ cmd += 4;
}
}
@@ -329,14 +305,16 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
*cs++ = 0; /* value */
if (aux_inv) { /* hsdes: 1809175790 */
- struct intel_engine_cs *engine;
- unsigned int tmp;
-
- *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
- for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
- *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
- *cs++ = AUX_INV;
+ *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
+ *cs++ = i915_mmio_reg_offset(GEN12_VD0_AUX_NV);
+ else if (rq->engine->class == VIDEO_ENHANCEMENT_CLASS)
+ *cs++ = i915_mmio_reg_offset(GEN12_VE0_AUX_NV);
+ else {
+ GEM_BUG_ON("unknown aux_inv reg\n");
+ *cs++ = i915_mmio_reg_offset(INVALID_MMIO_REG);
}
+ *cs++ = AUX_INV;
*cs++ = MI_NOOP;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d112ffd56418..54fdf1882cae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -144,6 +144,7 @@
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
+#define MI_LRI_MMIO_REMAP_EN (1<<17)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv
@ 2022-03-18 5:12 ` fei.yang
0 siblings, 0 replies; 4+ messages in thread
From: fei.yang @ 2022-03-18 5:12 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Fei Yang <fei.yang@intel.com>
GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the rq->engine is not necessarily the engine
eventually carrying out the request, and potentially the engine
could even be a virtual one (with engine->instance being -1).
With the MMIO remap feature, we can actually set bit 17 of MI_LRI
instruction and let the hardware to figure out the local aux_inv
register at runtime to avoid invalidating auxiliary table for all
engines.
Bspec: 45728
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 42 +++++---------------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
2 files changed, 11 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 36148887c699..af5daaf934b5 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -165,30 +165,6 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
-static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
-{
- static const i915_reg_t vd[] = {
- GEN12_VD0_AUX_NV,
- GEN12_VD1_AUX_NV,
- GEN12_VD2_AUX_NV,
- GEN12_VD3_AUX_NV,
- };
-
- static const i915_reg_t ve[] = {
- GEN12_VE0_AUX_NV,
- GEN12_VE1_AUX_NV,
- };
-
- if (engine->class == VIDEO_DECODE_CLASS)
- return vd[engine->instance];
-
- if (engine->class == VIDEO_ENHANCEMENT_CLASS)
- return ve[engine->instance];
-
- GEM_BUG_ON("unknown aux_inv reg\n");
- return INVALID_MMIO_REG;
-}
-
static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
@@ -296,7 +272,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (!HAS_FLAT_CCS(rq->engine->i915)) {
aux_inv = rq->engine->mask & ~BIT(BCS0);
if (aux_inv)
- cmd += 2 * hweight32(aux_inv) + 2;
+ cmd += 4;
}
}
@@ -329,14 +305,16 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
*cs++ = 0; /* value */
if (aux_inv) { /* hsdes: 1809175790 */
- struct intel_engine_cs *engine;
- unsigned int tmp;
-
- *cs++ = MI_LOAD_REGISTER_IMM(hweight32(aux_inv));
- for_each_engine_masked(engine, rq->engine->gt, aux_inv, tmp) {
- *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
- *cs++ = AUX_INV;
+ *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
+ *cs++ = i915_mmio_reg_offset(GEN12_VD0_AUX_NV);
+ else if (rq->engine->class == VIDEO_ENHANCEMENT_CLASS)
+ *cs++ = i915_mmio_reg_offset(GEN12_VE0_AUX_NV);
+ else {
+ GEM_BUG_ON("unknown aux_inv reg\n");
+ *cs++ = i915_mmio_reg_offset(INVALID_MMIO_REG);
}
+ *cs++ = AUX_INV;
*cs++ = MI_NOOP;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d112ffd56418..54fdf1882cae 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -144,6 +144,7 @@
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
/* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */
#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
+#define MI_LRI_MMIO_REMAP_EN (1<<17)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: avoid concurrent writes to aux_inv (rev6)
2022-03-18 5:12 ` [Intel-gfx] " fei.yang
(?)
@ 2022-03-18 5:26 ` Patchwork
-1 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-03-18 5:26 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev6)
URL : https://patchwork.freedesktop.org/series/100772/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d9e840b8dd7a drm/i915: avoid concurrent writes to aux_inv
-:81: CHECK:BRACES: braces {} should be used on all arms of this statement
#81: FILE: drivers/gpu/drm/i915/gt/gen8_engine_cs.c:309:
+ if (rq->engine->class == VIDEO_DECODE_CLASS)
[...]
+ else if (rq->engine->class == VIDEO_ENHANCEMENT_CLASS)
[...]
+ else {
[...]
-:85: CHECK:BRACES: Unbalanced braces around else statement
#85: FILE: drivers/gpu/drm/i915/gt/gen8_engine_cs.c:313:
+ else {
-:101: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#101: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:147:
+#define MI_LRI_MMIO_REMAP_EN (1<<17)
^
total: 0 errors, 0 warnings, 3 checks, 68 lines checked
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: avoid concurrent writes to aux_inv (rev6)
2022-03-18 5:12 ` [Intel-gfx] " fei.yang
(?)
(?)
@ 2022-03-18 6:12 ` Patchwork
-1 siblings, 0 replies; 4+ messages in thread
From: Patchwork @ 2022-03-18 6:12 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5915 bytes --]
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev6)
URL : https://patchwork.freedesktop.org/series/100772/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11380 -> Patchwork_22605
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/index.html
Participating hosts (47 -> 43)
------------------------------
Additional (1): bat-jsl-2
Missing (5): shard-tglu bat-dg1-5 fi-bsw-cyan shard-rkl fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22605:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11380/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
Known issues
------------
Here are the changes found in Patchwork_22605 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][3] -> [INCOMPLETE][4] ([i915#4418])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11380/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@kms_flip@basic-plain-flip:
- bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4078])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/bat-dg1-6/igt@kms_flip@basic-plain-flip.html
* igt@runner@aborted:
- bat-dg1-6: NOTRUN -> [FAIL][6] ([i915#4312] / [i915#5257])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/bat-dg1-6/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][7] ([i915#5127]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11380/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}: [DMESG-WARN][9] ([i915#4391]) -> [PASS][10] +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11380/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5276]: https://gitlab.freedesktop.org/drm/intel/issues/5276
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5338]: https://gitlab.freedesktop.org/drm/intel/issues/5338
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-------------
* Linux: CI_DRM_11380 -> Patchwork_22605
CI-20190529: 20190529
CI_DRM_11380: fe83949cd4316608ea785fc376b6ed444224adad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6385: f3df40281d93d5a63ee98fa30e90852d780673c9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22605: d9e840b8dd7affcd3c466d8073349a44e03c7b82 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d9e840b8dd7a drm/i915: avoid concurrent writes to aux_inv
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22605/index.html
[-- Attachment #2: Type: text/html, Size: 4710 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-03-18 5:12 [PATCH] drm/i915: avoid concurrent writes to aux_inv fei.yang
2022-03-18 5:12 ` [Intel-gfx] " fei.yang
2022-03-18 5:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: avoid concurrent writes to aux_inv (rev6) Patchwork
2022-03-18 6:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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