* [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
@ 2022-03-17 7:09 ` ~eopxd
0 siblings, 0 replies; 6+ messages in thread
From: ~eopxd @ 2022-03-17 7:09 UTC (permalink / raw)
To: qemu-devel; +Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, qemu-riscv
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
According to v-spec (section 7.9):
The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
regardless of current settings in vtype and vl. The usual property that no
elements are written if vstart ≥ vl does not apply to these instructions.
Instead, no elements are written if vstart ≥ evl.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 275fded6e4..4ea7e41e1a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
gen_helper_ldst_whole *fn, DisasContext *s,
bool is_store)
{
+ uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
+
TCGv_ptr dest;
TCGv base;
TCGv_i32 desc;
@@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
if (!is_store) {
mark_vs_dirty(s);
}
+ gen_set_label(over);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
@ 2022-03-17 7:09 ` ~eopxd
0 siblings, 0 replies; 6+ messages in thread
From: ~eopxd @ 2022-03-17 7:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Bin Meng
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
According to v-spec (section 7.9):
The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
regardless of current settings in vtype and vl. The usual property that no
elements are written if vstart ≥ vl does not apply to these instructions.
Instead, no elements are written if vstart ≥ evl.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 275fded6e4..4ea7e41e1a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
gen_helper_ldst_whole *fn, DisasContext *s,
bool is_store)
{
+ uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
+
TCGv_ptr dest;
TCGv base;
TCGv_i32 desc;
@@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
if (!is_store) {
mark_vs_dirty(s);
}
+ gen_set_label(over);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
2022-03-17 7:09 ` ~eopxd
@ 2022-03-20 23:48 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-03-20 23:48 UTC (permalink / raw)
To: ~eopxd
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Sat, Mar 19, 2022 at 6:59 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> According to v-spec (section 7.9):
> The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
> regardless of current settings in vtype and vl. The usual property that no
> elements are written if vstart ≥ vl does not apply to these instructions.
> Instead, no elements are written if vstart ≥ evl.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 275fded6e4..4ea7e41e1a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> gen_helper_ldst_whole *fn, DisasContext *s,
> bool is_store)
> {
> + uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> +
> TCGv_ptr dest;
> TCGv base;
> TCGv_i32 desc;
> @@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> if (!is_store) {
> mark_vs_dirty(s);
> }
> + gen_set_label(over);
>
> return true;
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
@ 2022-03-20 23:48 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-03-20 23:48 UTC (permalink / raw)
To: ~eopxd
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, open list:RISC-V
On Sat, Mar 19, 2022 at 6:59 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> According to v-spec (section 7.9):
> The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
> regardless of current settings in vtype and vl. The usual property that no
> elements are written if vstart ≥ vl does not apply to these instructions.
> Instead, no elements are written if vstart ≥ evl.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 275fded6e4..4ea7e41e1a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> gen_helper_ldst_whole *fn, DisasContext *s,
> bool is_store)
> {
> + uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> +
> TCGv_ptr dest;
> TCGv base;
> TCGv_i32 desc;
> @@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> if (!is_store) {
> mark_vs_dirty(s);
> }
> + gen_set_label(over);
>
> return true;
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
2022-03-17 7:09 ` ~eopxd
@ 2022-03-21 0:20 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-03-21 0:20 UTC (permalink / raw)
To: ~eopxd
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt,
qemu-devel@nongnu.org Developers, open list:RISC-V
On Sat, Mar 19, 2022 at 6:59 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> According to v-spec (section 7.9):
> The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
> regardless of current settings in vtype and vl. The usual property that no
> elements are written if vstart ≥ vl does not apply to these instructions.
> Instead, no elements are written if vstart ≥ evl.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 275fded6e4..4ea7e41e1a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> gen_helper_ldst_whole *fn, DisasContext *s,
> bool is_store)
> {
> + uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> +
> TCGv_ptr dest;
> TCGv base;
> TCGv_i32 desc;
> @@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> if (!is_store) {
> mark_vs_dirty(s);
> }
> + gen_set_label(over);
>
> return true;
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store
@ 2022-03-21 0:20 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2022-03-21 0:20 UTC (permalink / raw)
To: ~eopxd
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, open list:RISC-V
On Sat, Mar 19, 2022 at 6:59 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> According to v-spec (section 7.9):
> The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
> regardless of current settings in vtype and vl. The usual property that no
> elements are written if vstart ≥ vl does not apply to these instructions.
> Instead, no elements are written if vstart ≥ evl.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 275fded6e4..4ea7e41e1a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> gen_helper_ldst_whole *fn, DisasContext *s,
> bool is_store)
> {
> + uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
> +
> TCGv_ptr dest;
> TCGv base;
> TCGv_i32 desc;
> @@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
> if (!is_store) {
> mark_vs_dirty(s);
> }
> + gen_set_label(over);
>
> return true;
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-03-21 0:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-17 7:09 [PATCH qemu] target/riscv: rvv: Add missing early exit condition for whole register load/store ~eopxd
2022-03-17 7:09 ` ~eopxd
2022-03-20 23:48 ` Alistair Francis
2022-03-20 23:48 ` Alistair Francis
2022-03-21 0:20 ` Alistair Francis
2022-03-21 0:20 ` Alistair Francis
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