* [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915
@ 2022-03-21 11:03 Stanislav Lisovskiy
2022-03-21 11:03 ` [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Stanislav Lisovskiy @ 2022-03-21 11:03 UTC (permalink / raw)
To: intel-gfx
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/dp/drm_dp.c | 25 ++++
drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++-----
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++
include/drm/dp/drm_dp_helper.h | 11 +-
5 files changed, 226 insertions(+), 45 deletions(-)
--
2.24.1.485.gad05a3d8e5
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-03-21 11:03 ` Stanislav Lisovskiy 2022-03-21 12:44 ` Jani Nikula 2022-03-21 11:03 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy ` (4 subsequent siblings) 5 siblings, 1 reply; 9+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 11:03 UTC (permalink / raw) To: intel-gfx Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..45815745ba7b 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-03-21 11:03 ` [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy @ 2022-03-21 12:44 ` Jani Nikula 2022-03-21 14:08 ` Lisovskiy, Stanislav 0 siblings, 1 reply; 9+ messages in thread From: Jani Nikula @ 2022-03-21 12:44 UTC (permalink / raw) To: Stanislav Lisovskiy, intel-gfx On Mon, 21 Mar 2022, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote: > Adding DP DSC register definitions, we might need for further > DSC implementation, supporting MST and DP branch pass-through mode. > > v2: - Fixed checkpatch comment warning > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ > include/drm/dp/drm_dp_helper.h | 11 ++++++++++- > 2 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c > index 703972ae14c6..45815745ba7b 100644 > --- a/drivers/gpu/drm/dp/drm_dp.c > +++ b/drivers/gpu/drm/dp/drm_dp.c > @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], > } > EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); > > +/** > + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision > + * which DP DSC sink device supports. > + */ > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) > +{ > + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; > + > + switch (bpp_increment_dpcd) { So I didn't look this up in the spec, but later in the patch you're adding masks for the dpcd register in question, so I presume it's not fine to assume the whole register is about bbp. > + case DP_DSC_BITS_PER_PIXEL_1_16: > + return 16; > + case DP_DSC_BITS_PER_PIXEL_1_8: > + return 8; > + case DP_DSC_BITS_PER_PIXEL_1_4: > + return 4; > + case DP_DSC_BITS_PER_PIXEL_1_2: > + return 2; > + case DP_DSC_BITS_PER_PIXEL_1_1: > + return 1; > + } > + > + return 0; > +} > + > + Didn't checkpatch complain about the double newline? You don't use the function for anything in patch 2. And you couldn't because it's not exported to drivers. BR, Jani. > /** > * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits > * @dsc_dpcd: DSC capabilities from DPCD > diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h > index 51e02cf75277..e4c9f4438ccb 100644 > --- a/include/drm/dp/drm_dp_helper.h > +++ b/include/drm/dp/drm_dp_helper.h > @@ -246,6 +246,9 @@ struct drm_panel; > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) > > #define DP_DSC_REV 0x061 > # define DP_DSC_MAJOR_MASK (0xf << 0) > @@ -284,12 +287,15 @@ struct drm_panel; > > #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 > # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) > +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) > > #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ > > #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ > # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) > # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 > +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 > +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 > > #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 > # define DP_DSC_RGB (1 << 0) > @@ -351,11 +357,13 @@ struct drm_panel; > # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) > > #define DP_DSC_BITS_PER_PIXEL_INC 0x06F > +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f > +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 > # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 > # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 > # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 > # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 > -# define DP_DSC_BITS_PER_PIXEL_1 0x4 > +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 > > #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ > # define DP_PSR_IS_SUPPORTED 1 > @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], > u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); > int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], > u8 dsc_bpc[3]); > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); > > static inline bool > drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-03-21 12:44 ` Jani Nikula @ 2022-03-21 14:08 ` Lisovskiy, Stanislav 0 siblings, 0 replies; 9+ messages in thread From: Lisovskiy, Stanislav @ 2022-03-21 14:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Mon, Mar 21, 2022 at 02:44:20PM +0200, Jani Nikula wrote: > On Mon, 21 Mar 2022, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote: > > Adding DP DSC register definitions, we might need for further > > DSC implementation, supporting MST and DP branch pass-through mode. > > > > v2: - Fixed checkpatch comment warning > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ > > include/drm/dp/drm_dp_helper.h | 11 ++++++++++- > > 2 files changed, 35 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c > > index 703972ae14c6..45815745ba7b 100644 > > --- a/drivers/gpu/drm/dp/drm_dp.c > > +++ b/drivers/gpu/drm/dp/drm_dp.c > > @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], > > } > > EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); > > > > +/** > > + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision > > + * which DP DSC sink device supports. > > + */ > > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) > > +{ > > + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; > > + > > + switch (bpp_increment_dpcd) { > > So I didn't look this up in the spec, but later in the patch you're > adding masks for the dpcd register in question, so I presume it's not > fine to assume the whole register is about bbp. In spec its called MAX_BPP_DELTA_AND_MAX_BPP_INCREMENT, for DP 1.4 rest bits are reserved, except those for bpp increment, while in DP 2.0, rest are for max bpp delta(table 2-183) I thought that full name would be too long and also confusing. > > > + case DP_DSC_BITS_PER_PIXEL_1_16: > > + return 16; > > + case DP_DSC_BITS_PER_PIXEL_1_8: > > + return 8; > > + case DP_DSC_BITS_PER_PIXEL_1_4: > > + return 4; > > + case DP_DSC_BITS_PER_PIXEL_1_2: > > + return 2; > > + case DP_DSC_BITS_PER_PIXEL_1_1: > > + return 1; > > + } > > + > > + return 0; > > +} > > + > > + > > Didn't checkpatch complain about the double newline? Actually it did. Fixed rest of warns, but for some reason didn't spot this one. > > You don't use the function for anything in patch 2. And you couldn't > because it's not exported to drivers. Yes, I think we don't support currently those increments, but I guess we will need those in future. Should I remove it until we actually start using them? Stan > > BR, > Jani. > > > /** > > * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits > > * @dsc_dpcd: DSC capabilities from DPCD > > diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h > > index 51e02cf75277..e4c9f4438ccb 100644 > > --- a/include/drm/dp/drm_dp_helper.h > > +++ b/include/drm/dp/drm_dp_helper.h > > @@ -246,6 +246,9 @@ struct drm_panel; > > > > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ > > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) > > +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) > > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) > > +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) > > > > #define DP_DSC_REV 0x061 > > # define DP_DSC_MAJOR_MASK (0xf << 0) > > @@ -284,12 +287,15 @@ struct drm_panel; > > > > #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 > > # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) > > +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) > > > > #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ > > > > #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ > > # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) > > # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 > > +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 > > +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 > > > > #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 > > # define DP_DSC_RGB (1 << 0) > > @@ -351,11 +357,13 @@ struct drm_panel; > > # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) > > > > #define DP_DSC_BITS_PER_PIXEL_INC 0x06F > > +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f > > +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 > > # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 > > # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 > > # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 > > # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 > > -# define DP_DSC_BITS_PER_PIXEL_1 0x4 > > +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 > > > > #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ > > # define DP_PSR_IS_SUPPORTED 1 > > @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], > > u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); > > int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], > > u8 dsc_bpc[3]); > > +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); > > > > static inline bool > > drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-03-21 11:03 ` [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy @ 2022-03-21 11:03 ` Stanislav Lisovskiy 2022-03-21 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev3) Patchwork ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 11:03 UTC (permalink / raw) To: intel-gfx Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ 3 files changed, 191 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9e19165fd175..b8e1561b5eca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for MST -> TimeSlotsPerMTP has to be calculated */ bits_per_pixel = (link_clock * lane_count * 8) / - intel_dp_mode_to_fec_clock(mode_clock); + (intel_dp_mode_to_fec_clock(mode_clock) * timeslots); drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ @@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1375,10 +1375,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1429,7 +1430,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1441,41 +1443,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1558,7 +1545,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes)) { ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index d457e17bdc57..4c0ad3158ee7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,6 +55,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -94,6 +99,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e30e698aa684..778ca6283b8e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,82 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -175,6 +251,27 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -715,6 +812,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -752,6 +853,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev3) 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-03-21 11:03 ` [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-03-21 11:03 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy @ 2022-03-21 18:37 ` Patchwork 2022-03-21 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-03-21 18:37 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx == Series Details == Series: Add DP MST DSC support to i915 (rev3) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5e516f0e4e89 drm: Add missing DP DSC extended capability definitions. -:45: CHECK:LINE_SPACING: Please don't use multiple blank lines #45: FILE: drivers/gpu/drm/dp/drm_dp.c:2339: + + total: 0 errors, 0 warnings, 1 checks, 76 lines checked 307fe46d0c18 drm/i915: Add DSC support to MST path ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DP MST DSC support to i915 (rev3) 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy ` (2 preceding siblings ...) 2022-03-21 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev3) Patchwork @ 2022-03-21 18:39 ` Patchwork 2022-03-21 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-22 2:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-03-21 18:39 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx == Series Details == Series: Add DP MST DSC support to i915 (rev3) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: error: incompatible types in comparison expression (different type sizes): +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: unsigned long * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: unsigned long long * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev3) 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy ` (3 preceding siblings ...) 2022-03-21 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-03-21 19:04 ` Patchwork 2022-03-22 2:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-03-21 19:04 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 6122 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev3) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11393 -> Patchwork_22626 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/index.html Participating hosts (46 -> 41) ------------------------------ Missing (5): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Known issues ------------ Here are the changes found in Patchwork_22626 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html * igt@i915_selftest@live@gt_engines: - bat-dg1-6: [PASS][2] -> [INCOMPLETE][3] ([i915#4418]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/bat-dg1-6/igt@i915_selftest@live@gt_engines.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-dg1-6/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_mocs: - fi-tgl-1115g4: [PASS][4] -> [DMESG-WARN][5] ([i915#2867]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/fi-tgl-1115g4/igt@i915_selftest@live@gt_mocs.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/fi-tgl-1115g4/igt@i915_selftest@live@gt_mocs.html * igt@runner@aborted: - bat-dg1-6: NOTRUN -> [FAIL][6] ([i915#4312] / [i915#5257]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-dg1-6/igt@runner@aborted.html #### Possible fixes #### * igt@gem_busy@busy@all: - {bat-dg2-9}: [DMESG-WARN][7] ([i915#5195]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/bat-dg2-9/igt@gem_busy@busy@all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-dg2-9/igt@gem_busy@busy@all.html * igt@i915_selftest@live@coherency: - {bat-rpls-2}: [INCOMPLETE][9] -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/bat-rpls-2/igt@i915_selftest@live@coherency.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-rpls-2/igt@i915_selftest@live@coherency.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [INCOMPLETE][11] ([i915#4785]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html - {bat-jsl-2}: [INCOMPLETE][13] ([i915#5153]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/bat-jsl-2/igt@i915_selftest@live@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-jsl-2/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@perf: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#2867]) -> [PASS][16] +16 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/fi-tgl-dsi/igt@i915_selftest@live@perf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/fi-tgl-dsi/igt@i915_selftest@live@perf.html * igt@i915_selftest@live@sanitycheck: - {bat-rpls-2}: [DMESG-WARN][17] ([i915#4391]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/bat-rpls-2/igt@i915_selftest@live@sanitycheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/bat-rpls-2/igt@i915_selftest@live@sanitycheck.html * igt@vgem_basic@unload: - {fi-tgl-dsi}: [DMESG-WARN][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/fi-tgl-dsi/igt@vgem_basic@unload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/fi-tgl-dsi/igt@vgem_basic@unload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068 [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153 [i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192 [i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193 [i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5337]: https://gitlab.freedesktop.org/drm/intel/issues/5337 [i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339 [i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342 Build changes ------------- * Linux: CI_DRM_11393 -> Patchwork_22626 CI-20190529: 20190529 CI_DRM_11393: bb39f08a81da1a7e2d82026eac394394504b7126 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6387: 04d012b18355b53798af5a55a8915afb1a421bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22626: 307fe46d0c184925462e281ca879d6642c60e721 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 307fe46d0c18 drm/i915: Add DSC support to MST path 5e516f0e4e89 drm: Add missing DP DSC extended capability definitions. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/index.html [-- Attachment #2: Type: text/html, Size: 6529 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Add DP MST DSC support to i915 (rev3) 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy ` (4 preceding siblings ...) 2022-03-21 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-03-22 2:43 ` Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2022-03-22 2:43 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30261 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev3) URL : https://patchwork.freedesktop.org/series/101492/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11393_full -> Patchwork_22626_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22626_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22626_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22626_full: ### IGT changes ### #### Possible regressions #### * igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-tglb3/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-tglb8/igt@kms_atomic_transition@modeset-transition-nonblocking@1x-outputs.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_exec_flush@basic-uc-set-default: - {shard-rkl}: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-2/igt@gem_exec_flush@basic-uc-set-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-5/igt@gem_exec_flush@basic-uc-set-default.html Known issues ------------ Here are the changes found in Patchwork_22626_full that come from known issues: ### CI changes ### #### Issues hit #### * boot: - shard-skl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [FAIL][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47]) ([i915#5032]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl9/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl9/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl9/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl8/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl10/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl10/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl3/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl2/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl2/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl1/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl1/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl1/boot.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl10/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl10/boot.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl10/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-contexts-1us: - shard-iclb: [PASS][48] -> [TIMEOUT][49] ([i915#3070]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb8/igt@gem_eio@in-flight-contexts-1us.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb5/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_exec_balancer@parallel-ordering: - shard-kbl: NOTRUN -> [DMESG-FAIL][50] ([i915#5076]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl1/igt@gem_exec_balancer@parallel-ordering.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][51] ([i915#2846]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@gem_exec_fair@basic-deadline.html - shard-glk: [PASS][52] -> [FAIL][53] ([i915#2846]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk2/igt@gem_exec_fair@basic-deadline.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk9/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: [PASS][54] -> [FAIL][55] ([i915#2842]) +2 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][56] -> [FAIL][57] ([i915#2842]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][58] -> [FAIL][59] ([i915#2842]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_fence_thrash@bo-write-verify-threaded-none: - shard-glk: [PASS][60] -> [DMESG-WARN][61] ([i915#118]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk6/igt@gem_fence_thrash@bo-write-verify-threaded-none.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk4/igt@gem_fence_thrash@bo-write-verify-threaded-none.html * igt@gem_lmem_swapping@heavy-multi: - shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4613]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@gem_lmem_swapping@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#4613]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl7/igt@gem_lmem_swapping@heavy-verify-multi.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271]) +74 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@gem_media_vme.html * igt@gem_softpin@full: - shard-snb: NOTRUN -> [SKIP][65] ([fdo#109271]) +60 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-snb2/igt@gem_softpin@full.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][66] -> [FAIL][67] ([i915#454]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb7/igt@i915_pm_dc@dc6-psr.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb6/igt@i915_pm_dc@dc6-psr.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][68] ([i915#1886]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][69] -> [INCOMPLETE][70] ([i915#3921]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-snb5/igt@i915_selftest@live@hangcheck.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-snb5/igt@i915_selftest@live@hangcheck.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-tglb: [PASS][71] -> [FAIL][72] ([i915#3743]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-tglb6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-tglb3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][73] ([i915#3743]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3777]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][75] ([i915#3763]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3777]) +2 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +7 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +4 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_chamelium@vga-hpd-without-ddc: - shard-snb: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +4 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-snb2/igt@kms_chamelium@vga-hpd-without-ddc.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +19 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-d-ctm-0-25: - shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +4 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html * igt@kms_content_protection@atomic-dpms: - shard-kbl: NOTRUN -> [TIMEOUT][84] ([i915#1319]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl6/igt@kms_content_protection@atomic-dpms.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: NOTRUN -> [FAIL][85] ([i915#2346]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html - shard-glk: [PASS][86] -> [FAIL][87] ([i915#2346]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium: - shard-iclb: NOTRUN -> [SKIP][88] ([i915#3528]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb7/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][89] -> [INCOMPLETE][90] ([i915#180]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible: - shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271]) +45 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [PASS][92] -> [DMESG-WARN][93] ([i915#180]) +1 similar issue [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@plain-flip-fb-recreate@b-edp1: - shard-skl: [PASS][94] -> [FAIL][95] ([i915#2122]) +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling: - shard-iclb: [PASS][96] -> [SKIP][97] ([i915#3701]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling: - shard-glk: [PASS][98] -> [FAIL][99] ([i915#4911]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][100] -> [DMESG-WARN][101] ([i915#180]) +2 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc: - shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271]) +214 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html * igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a: - shard-skl: NOTRUN -> [FAIL][103] ([i915#1188]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-skl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-kbl: NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html - shard-apl: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][107] ([i915#265]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale: - shard-iclb: [PASS][109] -> [SKIP][110] ([i915#5235]) +2 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#658]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@kms_psr2_su@page_flip-p010: - shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#658]) +1 similar issue [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl4/igt@kms_psr2_su@page_flip-p010.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][113] -> [SKIP][114] ([fdo#109441]) +2 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_sysfs_edid_timing: - shard-kbl: NOTRUN -> [FAIL][115] ([IGT#2]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl4/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-d-wait-idle: - shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#533]) +2 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html - shard-apl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#533]) +2 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html * igt@sysfs_clients@recycle: - shard-skl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#2994]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl8/igt@sysfs_clients@recycle.html * igt@sysfs_clients@sema-25: - shard-kbl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2994]) +2 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl4/igt@sysfs_clients@sema-25.html #### Possible fixes #### * igt@fbdev@write: - {shard-rkl}: [SKIP][120] ([i915#2582]) -> [PASS][121] +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-2/igt@fbdev@write.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@fbdev@write.html * igt@feature_discovery@psr1: - {shard-rkl}: [SKIP][122] ([i915#658]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-4/igt@feature_discovery@psr1.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@feature_discovery@psr1.html * igt@gem_ctx_persistence@smoketest: - {shard-tglu}: [FAIL][124] ([i915#5099]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-tglu-3/igt@gem_ctx_persistence@smoketest.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-tglu-3/igt@gem_ctx_persistence@smoketest.html * igt@gem_eio@unwedge-stress: - {shard-tglu}: [TIMEOUT][126] ([i915#3063] / [i915#3648]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-tglu-5/igt@gem_eio@unwedge-stress.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-tglu-1/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [FAIL][128] ([i915#2842]) -> [PASS][129] [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [FAIL][130] ([i915#2842]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [FAIL][132] ([i915#2842]) -> [PASS][133] [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk4/igt@gem_exec_fair@basic-pace-solo@rcs0.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][134] ([i915#1436] / [i915#716]) -> [PASS][135] [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl4/igt@gen9_exec_parse@allowed-single.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl7/igt@gen9_exec_parse@allowed-single.html * igt@i915_pm_rpm@basic-pci-d3-state: - shard-skl: [FAIL][136] ([i915#5290]) -> [PASS][137] [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl10/igt@i915_pm_rpm@basic-pci-d3-state.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl9/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_pm_rpm@basic-rte: - {shard-rkl}: [SKIP][138] ([fdo#109308]) -> [PASS][139] [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-2/igt@i915_pm_rpm@basic-rte.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@i915_pm_rpm@basic-rte.html * igt@i915_pm_rpm@i2c: - shard-glk: [FAIL][140] ([i915#68]) -> [PASS][141] [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-glk4/igt@i915_pm_rpm@i2c.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-glk2/igt@i915_pm_rpm@i2c.html * igt@i915_pm_rps@reset: - {shard-dg1}: [FAIL][142] ([i915#3719]) -> [PASS][143] [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-dg1-12/igt@i915_pm_rps@reset.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-dg1-17/igt@i915_pm_rps@reset.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [DMESG-WARN][144] ([i915#180]) -> [PASS][145] +1 similar issue [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-apl6/igt@i915_suspend@fence-restore-untiled.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-apl3/igt@i915_suspend@fence-restore-untiled.html * igt@kms_big_fb@x-tiled-32bpp-rotate-0: - {shard-tglu}: [DMESG-WARN][146] ([i915#402]) -> [PASS][147] [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-tglu-3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-tglu-3/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs: - {shard-rkl}: [SKIP][148] ([i915#1845] / [i915#4098]) -> [PASS][149] +24 similar issues [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-4/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html * igt@kms_color@pipe-b-ctm-green-to-red: - {shard-rkl}: [SKIP][150] ([i915#1149] / [i915#4098]) -> [PASS][151] [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-4/igt@kms_color@pipe-b-ctm-green-to-red.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@kms_color@pipe-b-ctm-green-to-red.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - {shard-rkl}: [SKIP][152] ([fdo#112022]) -> [PASS][153] [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-4/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-random: - {shard-rkl}: [SKIP][154] ([fdo#112022] / [i915#4070]) -> [PASS][155] +6 similar issues [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x85-random.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][156] ([i915#180]) -> [PASS][157] +7 similar issues [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge: - {shard-rkl}: [SKIP][158] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][159] +3 similar issues [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-top-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [FAIL][160] ([i915#2346]) -> [PASS][161] [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - {shard-rkl}: [SKIP][162] ([fdo#111825]) -> [PASS][163] [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11393/shard-rkl-4/igt@kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/shard-rkl-6/i == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22626/index.html [-- Attachment #2: Type: text/html, Size: 33403 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-03-22 2:43 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-21 11:03 [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-03-21 11:03 ` [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-03-21 12:44 ` Jani Nikula 2022-03-21 14:08 ` Lisovskiy, Stanislav 2022-03-21 11:03 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy 2022-03-21 18:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev3) Patchwork 2022-03-21 18:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-21 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-22 2:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.