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From: Vinod Polimera <quic_vpolimer@quicinc.com>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: Vinod Polimera <quic_vpolimer@quicinc.com>,
	linux-kernel@vger.kernel.org, robdclark@gmail.com,
	dmitry.baryshkov@linaro.org, dianders@chromium.org,
	quic_kalyant@quicinc.com
Subject: [PATCH v7 4/5] arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk
Date: Tue, 22 Mar 2022 08:57:10 +0530	[thread overview]
Message-ID: <1647919631-14447-5-git-send-email-quic_vpolimer@quicinc.com> (raw)
In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com>

Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.

This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].

[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 41f4e46..c0771d2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4240,9 +4240,6 @@
 				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 			clock-names = "iface", "core";
 
-			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
-			assigned-clock-rates = <300000000>;
-
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
@@ -4273,10 +4270,8 @@
 					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 				clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 
-				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
-						  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-				assigned-clock-rates = <300000000>,
-						       <19200000>;
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
 				operating-points-v2 = <&mdp_opp_table>;
 				power-domains = <&rpmhpd SDM845_CX>;
 
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Vinod Polimera <quic_vpolimer@quicinc.com>
To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
	freedreno@lists.freedesktop.org, devicetree@vger.kernel.org
Cc: quic_kalyant@quicinc.com, dianders@chromium.org,
	linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org,
	Vinod Polimera <quic_vpolimer@quicinc.com>
Subject: [PATCH v7 4/5] arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk
Date: Tue, 22 Mar 2022 08:57:10 +0530	[thread overview]
Message-ID: <1647919631-14447-5-git-send-email-quic_vpolimer@quicinc.com> (raw)
In-Reply-To: <1647919631-14447-1-git-send-email-quic_vpolimer@quicinc.com>

Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.

This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].

[1] https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpolimer@quicinc.com/

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 41f4e46..c0771d2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4240,9 +4240,6 @@
 				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 			clock-names = "iface", "core";
 
-			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
-			assigned-clock-rates = <300000000>;
-
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
@@ -4273,10 +4270,8 @@
 					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 				clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 
-				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
-						  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
-				assigned-clock-rates = <300000000>,
-						       <19200000>;
+				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
 				operating-points-v2 = <&mdp_opp_table>;
 				power-domains = <&rpmhpd SDM845_CX>;
 
-- 
2.7.4


  parent reply	other threads:[~2022-03-22  3:27 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-22  3:27 [PATCH v7 0/5] Update mdp clk to max supported value to support higher refresh rates Vinod Polimera
2022-03-22  3:27 ` Vinod Polimera
2022-03-22  3:27 ` [PATCH v7 1/5] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table during probe Vinod Polimera
2022-03-22  3:27   ` Vinod Polimera
2022-04-22 15:16   ` Doug Anderson
2022-04-22 15:16     ` Doug Anderson
2022-03-22  3:27 ` [PATCH v7 2/5] arm64: dts: qcom: sm7280: remove assigned-clock-rate property for mdp clk Vinod Polimera
2022-03-22  3:27   ` Vinod Polimera
2022-03-22  3:27 ` [PATCH v7 3/5] arm64: dts: qcom: sm7180: " Vinod Polimera
2022-03-22  3:27   ` Vinod Polimera
2022-03-22  3:27 ` Vinod Polimera [this message]
2022-03-22  3:27   ` [PATCH v7 4/5] arm64: dts: qcom: sdm845: " Vinod Polimera
2022-03-22  3:27 ` [PATCH v7 5/5] arm64: dts: qcom: sm8250: " Vinod Polimera
2022-03-22  3:27   ` Vinod Polimera
2022-06-27 20:03 ` (subset) [PATCH v7 0/5] Update mdp clk to max supported value to support higher refresh rates Bjorn Andersson
2022-06-27 20:03   ` Bjorn Andersson

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