* [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-02-28 20:12 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-02-28 20:12 UTC (permalink / raw)
To: intel-gfx, dri-devel
At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
DPCD register values when reading from the 0xF0000- LTTPR range with an
AUX transaction block size bigger than 1. The DP standard requires 0 to
be returned - as for any other reserved/invalid addresses - but these
monitors return the DPCD_REV register value repeated in each byte of the
read buffer. This will in turn corrupt the values returned by the LTTPRs
between the source and the monitor: LTTPRs must adjust the values they
read from the downstream DPRX, for instance left-shift/init the
downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
monitor's DPRX is non-zero the adjusted values will be corrupt.
Reading the LTTPR registers one-by-one instead of reading all of them
with a single AUX transfer works around the issue.
According to the DP standard's 0xF0000 register description:
"LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
refers to the DPCD_REV or to the
LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
at the VESA site to clarify this haven't been addressed), one
possibility is that it's a restriction due to non-compliant monitors
described above. Disabling the non-transparent LTTPR mode for all such
monitors is not a viable solution: the transparent LTTPR mode has its
own issue causing link training failures and this would affect a lot of
monitors in use with DPCD_REV < 1.4. Instead this patch works around
the problem by reading the LTTPR common and PHY cap registers one-by-one
for any monitor with a DPCD_REV < 1.4.
The standard requires the DPCD capabilites to be read after the LTTPR
common capabilities are read, so re-read the DPCD capabilities after
the LTTPR common and PHY caps were read out.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
.../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
include/drm/dp/drm_dp_helper.h | 2 +
3 files changed, 59 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 703972ae14c64..f3950d42980f9 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
+ u8 *buf, int buf_size)
+{
+ /*
+ * Some monitors with a DPCD_REV < 0x14 return corrupted values when
+ * reading from the 0xF0000- range with a block size bigger than 1.
+ */
+ int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
+ int offset = 0;
+ int ret;
+
+ while (offset < buf_size) {
+ ret = drm_dp_dpcd_read(aux,
+ address + offset,
+ &buf[offset], block_size);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != block_size);
+
+ offset += block_size;
+ }
+
+ return 0;
+}
+
/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @caps: buffer to return the capability info in
*
* Read capabilities common to all LTTPRs.
@@ -2400,25 +2427,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
- caps, DP_LTTPR_COMMON_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+ caps, DP_LTTPR_COMMON_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
/**
* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @dp_phy: LTTPR PHY to read the capabilities for
* @caps: buffer to return the capability info in
*
@@ -2427,20 +2448,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
- caps, DP_LTTPR_PHY_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+ caps, DP_LTTPR_PHY_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 5d98773efd1b3..fbee20a76cf44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
}
static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
- if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
+ if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
phy_caps);
}
-static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ int ret;
if (intel_dp_is_edp(intel_dp))
return false;
@@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
return false;
- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
- intel_dp->lttpr_common_caps) < 0)
+ ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
+ intel_dp->lttpr_common_caps);
+ if (ret < 0)
goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
@@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
}
-static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
+static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int lttpr_count;
int i;
- if (!intel_dp_read_lttpr_common_caps(intel_dp))
+ if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
return 0;
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
@@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
}
for (i = 0; i < lttpr_count; i++)
- intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
+ intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
return lttpr_count;
}
@@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
*/
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
{
- int lttpr_count = intel_dp_init_lttpr(intel_dp);
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ int lttpr_count;
- /* The DPTX shall read the DPRX caps after LTTPR detection. */
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
+
+ /*
+ * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
+ * it here.
+ */
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);
return -EIO;
diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
index 51e02cf75277e..1eccd97419436 100644
--- a/include/drm/dp/drm_dp_helper.h
+++ b/include/drm/dp/drm_dp_helper.h
@@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
--
2.27.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-02-28 20:12 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-02-28 20:12 UTC (permalink / raw)
To: intel-gfx, dri-devel
At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
DPCD register values when reading from the 0xF0000- LTTPR range with an
AUX transaction block size bigger than 1. The DP standard requires 0 to
be returned - as for any other reserved/invalid addresses - but these
monitors return the DPCD_REV register value repeated in each byte of the
read buffer. This will in turn corrupt the values returned by the LTTPRs
between the source and the monitor: LTTPRs must adjust the values they
read from the downstream DPRX, for instance left-shift/init the
downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
monitor's DPRX is non-zero the adjusted values will be corrupt.
Reading the LTTPR registers one-by-one instead of reading all of them
with a single AUX transfer works around the issue.
According to the DP standard's 0xF0000 register description:
"LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
refers to the DPCD_REV or to the
LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
at the VESA site to clarify this haven't been addressed), one
possibility is that it's a restriction due to non-compliant monitors
described above. Disabling the non-transparent LTTPR mode for all such
monitors is not a viable solution: the transparent LTTPR mode has its
own issue causing link training failures and this would affect a lot of
monitors in use with DPCD_REV < 1.4. Instead this patch works around
the problem by reading the LTTPR common and PHY cap registers one-by-one
for any monitor with a DPCD_REV < 1.4.
The standard requires the DPCD capabilites to be read after the LTTPR
common capabilities are read, so re-read the DPCD capabilities after
the LTTPR common and PHY caps were read out.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
.../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
include/drm/dp/drm_dp_helper.h | 2 +
3 files changed, 59 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 703972ae14c64..f3950d42980f9 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
+ u8 *buf, int buf_size)
+{
+ /*
+ * Some monitors with a DPCD_REV < 0x14 return corrupted values when
+ * reading from the 0xF0000- range with a block size bigger than 1.
+ */
+ int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
+ int offset = 0;
+ int ret;
+
+ while (offset < buf_size) {
+ ret = drm_dp_dpcd_read(aux,
+ address + offset,
+ &buf[offset], block_size);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != block_size);
+
+ offset += block_size;
+ }
+
+ return 0;
+}
+
/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @caps: buffer to return the capability info in
*
* Read capabilities common to all LTTPRs.
@@ -2400,25 +2427,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
- caps, DP_LTTPR_COMMON_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+ caps, DP_LTTPR_COMMON_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
/**
* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @dp_phy: LTTPR PHY to read the capabilities for
* @caps: buffer to return the capability info in
*
@@ -2427,20 +2448,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
- caps, DP_LTTPR_PHY_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+ caps, DP_LTTPR_PHY_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 5d98773efd1b3..fbee20a76cf44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
}
static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
- if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
+ if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
phy_caps);
}
-static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ int ret;
if (intel_dp_is_edp(intel_dp))
return false;
@@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
return false;
- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
- intel_dp->lttpr_common_caps) < 0)
+ ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
+ intel_dp->lttpr_common_caps);
+ if (ret < 0)
goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
@@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
}
-static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
+static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int lttpr_count;
int i;
- if (!intel_dp_read_lttpr_common_caps(intel_dp))
+ if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
return 0;
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
@@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
}
for (i = 0; i < lttpr_count; i++)
- intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
+ intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
return lttpr_count;
}
@@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
*/
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
{
- int lttpr_count = intel_dp_init_lttpr(intel_dp);
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ int lttpr_count;
- /* The DPTX shall read the DPRX caps after LTTPR detection. */
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
+
+ /*
+ * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
+ * it here.
+ */
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);
return -EIO;
diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
index 51e02cf75277e..1eccd97419436 100644
--- a/include/drm/dp/drm_dp_helper.h
+++ b/include/drm/dp/drm_dp_helper.h
@@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
--
2.27.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
(?)
@ 2022-03-01 0:35 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-01 0:35 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
URL : https://patchwork.freedesktop.org/series/100851/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7ba5645d82fa drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
-:35: WARNING:TYPO_SPELLING: 'capabilites' may be misspelled - perhaps 'capabilities'?
#35:
The standard requires the DPCD capabilites to be read after the LTTPR
^^^^^^^^^^^
-:50: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#50: FILE: drivers/gpu/drm/dp/drm_dp.c:2393:
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
-:165: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#165: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:81:
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
total: 0 errors, 3 warnings, 0 checks, 182 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
(?)
(?)
@ 2022-03-01 1:08 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-01 1:08 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4573 bytes --]
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
URL : https://patchwork.freedesktop.org/series/100851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11300 -> Patchwork_22441
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/index.html
Participating hosts (46 -> 33)
------------------------------
Missing (13): fi-bdw-samus shard-tglu bat-dg1-6 bat-dg1-5 shard-rkl bat-dg2-9 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-rpls-2 shard-dg1 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_22441 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-blb-e6850/igt@amdgpu/amd_basic@cs-multi-fence.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][2] -> [INCOMPLETE][3] ([i915#4547])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live@hangcheck:
- fi-rkl-guc: [PASS][4] -> [INCOMPLETE][5] ([i915#4983])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-dsi: [DMESG-FAIL][6] ([i915#541]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-glk-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][8] ([i915#5026]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-blb-e6850/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-cfl-8109u: [DMESG-WARN][10] ([i915#165]) -> [PASS][11] +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-cfl-8109u/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#165] / [i915#295]) -> [PASS][13] +13 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11300/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Build changes
-------------
* Linux: CI_DRM_11300 -> Patchwork_22441
CI-20190529: 20190529
CI_DRM_11300: 10eb9bc8729d3da3fe8f53c8e5b70b8a9a52b6e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6361: 2372a4beb6a33c5f0799a4a8ccbb93794f52dbca @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22441: 7ba5645d82fa47b563026775f555df287a6d59bb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7ba5645d82fa drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22441/index.html
[-- Attachment #2: Type: text/html, Size: 5355 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
@ 2022-03-01 14:14 ` Ville Syrjälä
-1 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-01 14:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> DPCD register values when reading from the 0xF0000- LTTPR range with an
> AUX transaction block size bigger than 1. The DP standard requires 0 to
> be returned - as for any other reserved/invalid addresses - but these
> monitors return the DPCD_REV register value repeated in each byte of the
> read buffer. This will in turn corrupt the values returned by the LTTPRs
> between the source and the monitor: LTTPRs must adjust the values they
> read from the downstream DPRX, for instance left-shift/init the
> downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> monitor's DPRX is non-zero the adjusted values will be corrupt.
>
> Reading the LTTPR registers one-by-one instead of reading all of them
> with a single AUX transfer works around the issue.
>
> According to the DP standard's 0xF0000 register description:
> "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> refers to the DPCD_REV or to the
> LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> at the VESA site to clarify this haven't been addressed), one
> possibility is that it's a restriction due to non-compliant monitors
> described above. Disabling the non-transparent LTTPR mode for all such
> monitors is not a viable solution: the transparent LTTPR mode has its
> own issue causing link training failures and this would affect a lot of
> monitors in use with DPCD_REV < 1.4. Instead this patch works around
> the problem by reading the LTTPR common and PHY cap registers one-by-one
> for any monitor with a DPCD_REV < 1.4.
>
> The standard requires the DPCD capabilites to be read after the LTTPR
> common capabilities are read, so re-read the DPCD capabilities after
> the LTTPR common and PHY caps were read out.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> include/drm/dp/drm_dp_helper.h | 2 +
> 3 files changed, 59 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c64..f3950d42980f9 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> + u8 *buf, int buf_size)
> +{
> + /*
> + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> + * reading from the 0xF0000- range with a block size bigger than 1.
> + */
This sounds really scary. Have we checked what other registers might
end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
dd bs=16.
> + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> + int offset = 0;
> + int ret;
> +
> + while (offset < buf_size) {
Can we use a for loop?
> + ret = drm_dp_dpcd_read(aux,
> + address + offset,
> + &buf[offset], block_size);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != block_size);
> +
> + offset += block_size;
> + }
> +
> + return 0;
> +}
> +
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-03-01 14:14 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-01 14:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> DPCD register values when reading from the 0xF0000- LTTPR range with an
> AUX transaction block size bigger than 1. The DP standard requires 0 to
> be returned - as for any other reserved/invalid addresses - but these
> monitors return the DPCD_REV register value repeated in each byte of the
> read buffer. This will in turn corrupt the values returned by the LTTPRs
> between the source and the monitor: LTTPRs must adjust the values they
> read from the downstream DPRX, for instance left-shift/init the
> downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> monitor's DPRX is non-zero the adjusted values will be corrupt.
>
> Reading the LTTPR registers one-by-one instead of reading all of them
> with a single AUX transfer works around the issue.
>
> According to the DP standard's 0xF0000 register description:
> "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> refers to the DPCD_REV or to the
> LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> at the VESA site to clarify this haven't been addressed), one
> possibility is that it's a restriction due to non-compliant monitors
> described above. Disabling the non-transparent LTTPR mode for all such
> monitors is not a viable solution: the transparent LTTPR mode has its
> own issue causing link training failures and this would affect a lot of
> monitors in use with DPCD_REV < 1.4. Instead this patch works around
> the problem by reading the LTTPR common and PHY cap registers one-by-one
> for any monitor with a DPCD_REV < 1.4.
>
> The standard requires the DPCD capabilites to be read after the LTTPR
> common capabilities are read, so re-read the DPCD capabilities after
> the LTTPR common and PHY caps were read out.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> include/drm/dp/drm_dp_helper.h | 2 +
> 3 files changed, 59 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c64..f3950d42980f9 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> + u8 *buf, int buf_size)
> +{
> + /*
> + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> + * reading from the 0xF0000- range with a block size bigger than 1.
> + */
This sounds really scary. Have we checked what other registers might
end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
dd bs=16.
> + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> + int offset = 0;
> + int ret;
> +
> + while (offset < buf_size) {
Can we use a for loop?
> + ret = drm_dp_dpcd_read(aux,
> + address + offset,
> + &buf[offset], block_size);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != block_size);
> +
> + offset += block_size;
> + }
> +
> + return 0;
> +}
> +
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-03-01 14:14 ` [Intel-gfx] " Ville Syrjälä
@ 2022-03-01 18:14 ` Imre Deak
-1 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-03-01 18:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Tue, Mar 01, 2022 at 04:14:24PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> > At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> > DPCD register values when reading from the 0xF0000- LTTPR range with an
> > AUX transaction block size bigger than 1. The DP standard requires 0 to
> > be returned - as for any other reserved/invalid addresses - but these
> > monitors return the DPCD_REV register value repeated in each byte of the
> > read buffer. This will in turn corrupt the values returned by the LTTPRs
> > between the source and the monitor: LTTPRs must adjust the values they
> > read from the downstream DPRX, for instance left-shift/init the
> > downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> > monitor's DPRX is non-zero the adjusted values will be corrupt.
> >
> > Reading the LTTPR registers one-by-one instead of reading all of them
> > with a single AUX transfer works around the issue.
> >
> > According to the DP standard's 0xF0000 register description:
> > "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> > valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> > refers to the DPCD_REV or to the
> > LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> > at the VESA site to clarify this haven't been addressed), one
> > possibility is that it's a restriction due to non-compliant monitors
> > described above. Disabling the non-transparent LTTPR mode for all such
> > monitors is not a viable solution: the transparent LTTPR mode has its
> > own issue causing link training failures and this would affect a lot of
> > monitors in use with DPCD_REV < 1.4. Instead this patch works around
> > the problem by reading the LTTPR common and PHY cap registers one-by-one
> > for any monitor with a DPCD_REV < 1.4.
> >
> > The standard requires the DPCD capabilites to be read after the LTTPR
> > common capabilities are read, so re-read the DPCD capabilities after
> > the LTTPR common and PHY caps were read out.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> > .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> > include/drm/dp/drm_dp_helper.h | 2 +
> > 3 files changed, 59 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> > index 703972ae14c64..f3950d42980f9 100644
> > --- a/drivers/gpu/drm/dp/drm_dp.c
> > +++ b/drivers/gpu/drm/dp/drm_dp.c
> > @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > }
> > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> >
> > +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> > + u8 *buf, int buf_size)
> > +{
> > + /*
> > + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> > + * reading from the 0xF0000- range with a block size bigger than 1.
> > + */
>
> This sounds really scary. Have we checked what other registers might
> end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
> dd bs=16.
Yes, checked now on a DELL P2715Q/ADLP/native-DP (w/o any LTTPR):
dd bs=1 count=1M failes at offset 81 and 83, bs=16 doesn't have this
problem.
Replacing the above two bytes with 0s in the bs=1 output, the only
difference is at 0xf0000:
bs=1: 0x12 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
bs=16: 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12
I attached the edid and bin files to the bugzilla ticket.
> > + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> > + int offset = 0;
> > + int ret;
> > +
> > + while (offset < buf_size) {
>
> Can we use a for loop?
Yes, will change this.
> > + ret = drm_dp_dpcd_read(aux,
> > + address + offset,
> > + &buf[offset], block_size);
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != block_size);
> > +
> > + offset += block_size;
> > + }
> > +
> > + return 0;
> > +}
> > +
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-03-01 18:14 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-03-01 18:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Tue, Mar 01, 2022 at 04:14:24PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> > At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> > DPCD register values when reading from the 0xF0000- LTTPR range with an
> > AUX transaction block size bigger than 1. The DP standard requires 0 to
> > be returned - as for any other reserved/invalid addresses - but these
> > monitors return the DPCD_REV register value repeated in each byte of the
> > read buffer. This will in turn corrupt the values returned by the LTTPRs
> > between the source and the monitor: LTTPRs must adjust the values they
> > read from the downstream DPRX, for instance left-shift/init the
> > downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> > monitor's DPRX is non-zero the adjusted values will be corrupt.
> >
> > Reading the LTTPR registers one-by-one instead of reading all of them
> > with a single AUX transfer works around the issue.
> >
> > According to the DP standard's 0xF0000 register description:
> > "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> > valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> > refers to the DPCD_REV or to the
> > LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> > at the VESA site to clarify this haven't been addressed), one
> > possibility is that it's a restriction due to non-compliant monitors
> > described above. Disabling the non-transparent LTTPR mode for all such
> > monitors is not a viable solution: the transparent LTTPR mode has its
> > own issue causing link training failures and this would affect a lot of
> > monitors in use with DPCD_REV < 1.4. Instead this patch works around
> > the problem by reading the LTTPR common and PHY cap registers one-by-one
> > for any monitor with a DPCD_REV < 1.4.
> >
> > The standard requires the DPCD capabilites to be read after the LTTPR
> > common capabilities are read, so re-read the DPCD capabilities after
> > the LTTPR common and PHY caps were read out.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> > .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> > include/drm/dp/drm_dp_helper.h | 2 +
> > 3 files changed, 59 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> > index 703972ae14c64..f3950d42980f9 100644
> > --- a/drivers/gpu/drm/dp/drm_dp.c
> > +++ b/drivers/gpu/drm/dp/drm_dp.c
> > @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > }
> > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> >
> > +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> > + u8 *buf, int buf_size)
> > +{
> > + /*
> > + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> > + * reading from the 0xF0000- range with a block size bigger than 1.
> > + */
>
> This sounds really scary. Have we checked what other registers might
> end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
> dd bs=16.
Yes, checked now on a DELL P2715Q/ADLP/native-DP (w/o any LTTPR):
dd bs=1 count=1M failes at offset 81 and 83, bs=16 doesn't have this
problem.
Replacing the above two bytes with 0s in the bs=1 output, the only
difference is at 0xf0000:
bs=1: 0x12 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
bs=16: 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12
I attached the edid and bin files to the bugzilla ticket.
> > + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> > + int offset = 0;
> > + int ret;
> > +
> > + while (offset < buf_size) {
>
> Can we use a for loop?
Yes, will change this.
> > + ret = drm_dp_dpcd_read(aux,
> > + address + offset,
> > + &buf[offset], block_size);
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != block_size);
> > +
> > + offset += block_size;
> > + }
> > +
> > + return 0;
> > +}
> > +
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-03-01 18:14 ` [Intel-gfx] " Imre Deak
@ 2022-03-01 18:24 ` Ville Syrjälä
-1 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-01 18:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Tue, Mar 01, 2022 at 08:14:25PM +0200, Imre Deak wrote:
> On Tue, Mar 01, 2022 at 04:14:24PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> > > At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> > > DPCD register values when reading from the 0xF0000- LTTPR range with an
> > > AUX transaction block size bigger than 1. The DP standard requires 0 to
> > > be returned - as for any other reserved/invalid addresses - but these
> > > monitors return the DPCD_REV register value repeated in each byte of the
> > > read buffer. This will in turn corrupt the values returned by the LTTPRs
> > > between the source and the monitor: LTTPRs must adjust the values they
> > > read from the downstream DPRX, for instance left-shift/init the
> > > downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> > > monitor's DPRX is non-zero the adjusted values will be corrupt.
> > >
> > > Reading the LTTPR registers one-by-one instead of reading all of them
> > > with a single AUX transfer works around the issue.
> > >
> > > According to the DP standard's 0xF0000 register description:
> > > "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> > > valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> > > refers to the DPCD_REV or to the
> > > LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> > > at the VESA site to clarify this haven't been addressed), one
> > > possibility is that it's a restriction due to non-compliant monitors
> > > described above. Disabling the non-transparent LTTPR mode for all such
> > > monitors is not a viable solution: the transparent LTTPR mode has its
> > > own issue causing link training failures and this would affect a lot of
> > > monitors in use with DPCD_REV < 1.4. Instead this patch works around
> > > the problem by reading the LTTPR common and PHY cap registers one-by-one
> > > for any monitor with a DPCD_REV < 1.4.
> > >
> > > The standard requires the DPCD capabilites to be read after the LTTPR
> > > common capabilities are read, so re-read the DPCD capabilities after
> > > the LTTPR common and PHY caps were read out.
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> > > .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> > > include/drm/dp/drm_dp_helper.h | 2 +
> > > 3 files changed, 59 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> > > index 703972ae14c64..f3950d42980f9 100644
> > > --- a/drivers/gpu/drm/dp/drm_dp.c
> > > +++ b/drivers/gpu/drm/dp/drm_dp.c
> > > @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > > }
> > > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> > >
> > > +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> > > + u8 *buf, int buf_size)
> > > +{
> > > + /*
> > > + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> > > + * reading from the 0xF0000- range with a block size bigger than 1.
> > > + */
> >
> > This sounds really scary. Have we checked what other registers might
> > end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
> > dd bs=16.
>
> Yes, checked now on a DELL P2715Q/ADLP/native-DP (w/o any LTTPR):
>
> dd bs=1 count=1M failes at offset 81 and 83, bs=16 doesn't have this
> problem.
Huh. Oh well, it's a Dell monitor after all. Not sure what else I was
expecting tbh.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-03-01 18:24 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-01 18:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Tue, Mar 01, 2022 at 08:14:25PM +0200, Imre Deak wrote:
> On Tue, Mar 01, 2022 at 04:14:24PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 28, 2022 at 10:12:34PM +0200, Imre Deak wrote:
> > > At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> > > DPCD register values when reading from the 0xF0000- LTTPR range with an
> > > AUX transaction block size bigger than 1. The DP standard requires 0 to
> > > be returned - as for any other reserved/invalid addresses - but these
> > > monitors return the DPCD_REV register value repeated in each byte of the
> > > read buffer. This will in turn corrupt the values returned by the LTTPRs
> > > between the source and the monitor: LTTPRs must adjust the values they
> > > read from the downstream DPRX, for instance left-shift/init the
> > > downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> > > monitor's DPRX is non-zero the adjusted values will be corrupt.
> > >
> > > Reading the LTTPR registers one-by-one instead of reading all of them
> > > with a single AUX transfer works around the issue.
> > >
> > > According to the DP standard's 0xF0000 register description:
> > > "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> > > valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> > > refers to the DPCD_REV or to the
> > > LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> > > at the VESA site to clarify this haven't been addressed), one
> > > possibility is that it's a restriction due to non-compliant monitors
> > > described above. Disabling the non-transparent LTTPR mode for all such
> > > monitors is not a viable solution: the transparent LTTPR mode has its
> > > own issue causing link training failures and this would affect a lot of
> > > monitors in use with DPCD_REV < 1.4. Instead this patch works around
> > > the problem by reading the LTTPR common and PHY cap registers one-by-one
> > > for any monitor with a DPCD_REV < 1.4.
> > >
> > > The standard requires the DPCD capabilites to be read after the LTTPR
> > > common capabilities are read, so re-read the DPCD capabilities after
> > > the LTTPR common and PHY caps were read out.
> > >
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/dp/drm_dp.c | 58 ++++++++++++-------
> > > .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> > > include/drm/dp/drm_dp_helper.h | 2 +
> > > 3 files changed, 59 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> > > index 703972ae14c64..f3950d42980f9 100644
> > > --- a/drivers/gpu/drm/dp/drm_dp.c
> > > +++ b/drivers/gpu/drm/dp/drm_dp.c
> > > @@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > > }
> > > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> > >
> > > +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> > > + u8 *buf, int buf_size)
> > > +{
> > > + /*
> > > + * Some monitors with a DPCD_REV < 0x14 return corrupted values when
> > > + * reading from the 0xF0000- range with a block size bigger than 1.
> > > + */
> >
> > This sounds really scary. Have we checked what other registers might
> > end up corrupted? Eg. couple of rounds of comparing full dd bs=1 vs.
> > dd bs=16.
>
> Yes, checked now on a DELL P2715Q/ADLP/native-DP (w/o any LTTPR):
>
> dd bs=1 count=1M failes at offset 81 and 83, bs=16 doesn't have this
> problem.
Huh. Oh well, it's a Dell monitor after all. Not sure what else I was
expecting tbh.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
@ 2022-03-22 14:38 ` Imre Deak
-1 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-03-22 14:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
DPCD register values when reading from the 0xF0000- LTTPR range with an
AUX transaction block size bigger than 1. The DP standard requires 0 to
be returned - as for any other reserved/invalid addresses - but these
monitors return the DPCD_REV register value repeated in each byte of the
read buffer. This will in turn corrupt the values returned by the LTTPRs
between the source and the monitor: LTTPRs must adjust the values they
read from the downstream DPRX, for instance left-shift/init the
downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
monitor's DPRX is non-zero the adjusted values will be corrupt.
Reading the LTTPR registers one-by-one instead of reading all of them
with a single AUX transfer works around the issue.
According to the DP standard's 0xF0000 register description:
"LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
refers to the DPCD_REV or to the
LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
at the VESA site to clarify this haven't been addressed), one
possibility is that it's a restriction due to non-compliant monitors
described above. Disabling the non-transparent LTTPR mode for all such
monitors is not a viable solution: the transparent LTTPR mode has its
own issue causing link training failures and this would affect a lot of
monitors in use with DPCD_REV < 1.4. Instead this patch works around
the problem by reading the LTTPR common and PHY cap registers one-by-one
for any monitor with a DPCD_REV < 1.4.
The standard requires the DPCD capabilites to be read after the LTTPR
common capabilities are read, so re-read the DPCD capabilities after
the LTTPR common and PHY caps were read out.
v2:
- Use for instead of a while loop. (Ville)
- Add to code comment the monitor model with the problem.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/dp/drm_dp.c | 57 ++++++++++++-------
.../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
include/drm/dp/drm_dp_helper.h | 2 +
3 files changed, 58 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 703972ae14c64..58744f83931af 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2390,9 +2390,35 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
+ u8 *buf, int buf_size)
+{
+ /*
+ * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
+ * corrupted values when reading from the 0xF0000- range with a block
+ * size bigger than 1.
+ */
+ int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
+ int offset;
+ int ret;
+
+ for (offset = 0; offset < buf_size; offset += block_size) {
+ ret = drm_dp_dpcd_read(aux,
+ address + offset,
+ &buf[offset], block_size);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != block_size);
+ }
+
+ return 0;
+}
+
/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @caps: buffer to return the capability info in
*
* Read capabilities common to all LTTPRs.
@@ -2400,25 +2426,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
- caps, DP_LTTPR_COMMON_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+ caps, DP_LTTPR_COMMON_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
/**
* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @dp_phy: LTTPR PHY to read the capabilities for
* @caps: buffer to return the capability info in
*
@@ -2427,20 +2447,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
- caps, DP_LTTPR_PHY_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+ caps, DP_LTTPR_PHY_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 5d98773efd1b3..fbee20a76cf44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
}
static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
- if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
+ if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
phy_caps);
}
-static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ int ret;
if (intel_dp_is_edp(intel_dp))
return false;
@@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
return false;
- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
- intel_dp->lttpr_common_caps) < 0)
+ ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
+ intel_dp->lttpr_common_caps);
+ if (ret < 0)
goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
@@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
}
-static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
+static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int lttpr_count;
int i;
- if (!intel_dp_read_lttpr_common_caps(intel_dp))
+ if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
return 0;
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
@@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
}
for (i = 0; i < lttpr_count; i++)
- intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
+ intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
return lttpr_count;
}
@@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
*/
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
{
- int lttpr_count = intel_dp_init_lttpr(intel_dp);
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ int lttpr_count;
- /* The DPTX shall read the DPRX caps after LTTPR detection. */
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
+
+ /*
+ * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
+ * it here.
+ */
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);
return -EIO;
diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
index 51e02cf75277e..1eccd97419436 100644
--- a/include/drm/dp/drm_dp_helper.h
+++ b/include/drm/dp/drm_dp_helper.h
@@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-03-22 14:38 ` Imre Deak
0 siblings, 0 replies; 18+ messages in thread
From: Imre Deak @ 2022-03-22 14:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
DPCD register values when reading from the 0xF0000- LTTPR range with an
AUX transaction block size bigger than 1. The DP standard requires 0 to
be returned - as for any other reserved/invalid addresses - but these
monitors return the DPCD_REV register value repeated in each byte of the
read buffer. This will in turn corrupt the values returned by the LTTPRs
between the source and the monitor: LTTPRs must adjust the values they
read from the downstream DPRX, for instance left-shift/init the
downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
monitor's DPRX is non-zero the adjusted values will be corrupt.
Reading the LTTPR registers one-by-one instead of reading all of them
with a single AUX transfer works around the issue.
According to the DP standard's 0xF0000 register description:
"LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
refers to the DPCD_REV or to the
LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
at the VESA site to clarify this haven't been addressed), one
possibility is that it's a restriction due to non-compliant monitors
described above. Disabling the non-transparent LTTPR mode for all such
monitors is not a viable solution: the transparent LTTPR mode has its
own issue causing link training failures and this would affect a lot of
monitors in use with DPCD_REV < 1.4. Instead this patch works around
the problem by reading the LTTPR common and PHY cap registers one-by-one
for any monitor with a DPCD_REV < 1.4.
The standard requires the DPCD capabilites to be read after the LTTPR
common capabilities are read, so re-read the DPCD capabilities after
the LTTPR common and PHY caps were read out.
v2:
- Use for instead of a while loop. (Ville)
- Add to code comment the monitor model with the problem.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/dp/drm_dp.c | 57 ++++++++++++-------
.../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
include/drm/dp/drm_dp_helper.h | 2 +
3 files changed, 58 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
index 703972ae14c64..58744f83931af 100644
--- a/drivers/gpu/drm/dp/drm_dp.c
+++ b/drivers/gpu/drm/dp/drm_dp.c
@@ -2390,9 +2390,35 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
+ u8 *buf, int buf_size)
+{
+ /*
+ * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
+ * corrupted values when reading from the 0xF0000- range with a block
+ * size bigger than 1.
+ */
+ int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
+ int offset;
+ int ret;
+
+ for (offset = 0; offset < buf_size; offset += block_size) {
+ ret = drm_dp_dpcd_read(aux,
+ address + offset,
+ &buf[offset], block_size);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != block_size);
+ }
+
+ return 0;
+}
+
/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @caps: buffer to return the capability info in
*
* Read capabilities common to all LTTPRs.
@@ -2400,25 +2426,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
- caps, DP_LTTPR_COMMON_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+ caps, DP_LTTPR_COMMON_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
/**
* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
* @aux: DisplayPort AUX channel
+ * @dpcd: DisplayPort configuration data
* @dp_phy: LTTPR PHY to read the capabilities for
* @caps: buffer to return the capability info in
*
@@ -2427,20 +2447,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE])
{
- int ret;
-
- ret = drm_dp_dpcd_read(aux,
- DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
- caps, DP_LTTPR_PHY_CAP_SIZE);
- if (ret < 0)
- return ret;
-
- WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
-
- return 0;
+ return drm_dp_read_lttpr_regs(aux, dpcd,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+ caps, DP_LTTPR_PHY_CAP_SIZE);
}
EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 5d98773efd1b3..fbee20a76cf44 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
}
static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
- if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
+ if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
"[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
encoder->base.base.id, encoder->base.name, phy_name);
@@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
phy_caps);
}
-static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ int ret;
if (intel_dp_is_edp(intel_dp))
return false;
@@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
return false;
- if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
- intel_dp->lttpr_common_caps) < 0)
+ ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
+ intel_dp->lttpr_common_caps);
+ if (ret < 0)
goto reset_caps;
drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
@@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
}
-static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
+static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
int lttpr_count;
int i;
- if (!intel_dp_read_lttpr_common_caps(intel_dp))
+ if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
return 0;
lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
@@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
}
for (i = 0; i < lttpr_count; i++)
- intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
+ intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
return lttpr_count;
}
@@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
*/
int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
{
- int lttpr_count = intel_dp_init_lttpr(intel_dp);
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ int lttpr_count;
- /* The DPTX shall read the DPRX caps after LTTPR detection. */
+ if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
+ return -EIO;
+
+ lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
+
+ /*
+ * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
+ * it here.
+ */
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
intel_dp_reset_lttpr_common_caps(intel_dp);
return -EIO;
diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
index 51e02cf75277e..1eccd97419436 100644
--- a/include/drm/dp/drm_dp_helper.h
+++ b/include/drm/dp/drm_dp_helper.h
@@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ const u8 dpcd[DP_RECEIVER_CAP_SIZE],
enum drm_dp_phy dp_phy,
u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
--
2.30.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
` (4 preceding siblings ...)
(?)
@ 2022-03-22 14:48 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-22 14:48 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
URL : https://patchwork.freedesktop.org/series/100851/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8d7fe49b240d drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
-:38: WARNING:TYPO_SPELLING: 'capabilites' may be misspelled - perhaps 'capabilities'?
#38:
The standard requires the DPCD capabilites to be read after the LTTPR
^^^^^^^^^^^
-:58: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#58: FILE: drivers/gpu/drm/dp/drm_dp.c:2393:
+static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
-:172: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#172: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:81:
+static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
total: 0 errors, 3 warnings, 0 checks, 181 lines checked
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
` (5 preceding siblings ...)
(?)
@ 2022-03-22 14:55 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-22 14:55 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
URL : https://patchwork.freedesktop.org/series/100851/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
` (6 preceding siblings ...)
(?)
@ 2022-03-22 15:20 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-22 15:20 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5023 bytes --]
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
URL : https://patchwork.freedesktop.org/series/100851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11396 -> Patchwork_22643
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/index.html
Participating hosts (49 -> 43)
------------------------------
Missing (6): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22643:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/bat-adlm-1/igt@i915_selftest@live@requests.html
Known issues
------------
Here are the changes found in Patchwork_22643 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][2] -> [DMESG-WARN][3] ([i915#2943])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/fi-glk-dsi/igt@gem_exec_suspend@basic-s0@smem.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/fi-glk-dsi/igt@gem_exec_suspend@basic-s0@smem.html
#### Possible fixes ####
* igt@i915_selftest@live@evict:
- {bat-rpls-2}: [INCOMPLETE][4] -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/bat-rpls-2/igt@i915_selftest@live@evict.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/bat-rpls-2/igt@i915_selftest@live@evict.html
* igt@i915_selftest@live@objects:
- {bat-rpls-2}: [DMESG-WARN][6] ([i915#4391]) -> [PASS][7] +4 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/bat-rpls-2/igt@i915_selftest@live@objects.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/bat-rpls-2/igt@i915_selftest@live@objects.html
* igt@kms_force_connector_basic@force-connector-state:
- {bat-adlm-1}: [INCOMPLETE][8] ([i915#5361]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/bat-adlm-1/igt@kms_force_connector_basic@force-connector-state.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/bat-adlm-1/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][10] ([i915#295] / [i915#5341]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#295]) -> [PASS][13] +10 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2943]: https://gitlab.freedesktop.org/drm/intel/issues/2943
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5361]: https://gitlab.freedesktop.org/drm/intel/issues/5361
Build changes
-------------
* Linux: CI_DRM_11396 -> Patchwork_22643
CI-20190529: 20190529
CI_DRM_11396: 18b88414e6c9660022bb464d4d5fadb07d38cf04 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6387: 04d012b18355b53798af5a55a8915afb1a421bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22643: 8d7fe49b240d8f4fb1a167594706ab916e4a78cb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8d7fe49b240d drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/index.html
[-- Attachment #2: Type: text/html, Size: 5392 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
2022-03-22 14:38 ` [Intel-gfx] " Imre Deak
@ 2022-03-22 17:31 ` Ville Syrjälä
-1 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-22 17:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Tue, Mar 22, 2022 at 04:38:44PM +0200, Imre Deak wrote:
> At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> DPCD register values when reading from the 0xF0000- LTTPR range with an
> AUX transaction block size bigger than 1. The DP standard requires 0 to
> be returned - as for any other reserved/invalid addresses - but these
> monitors return the DPCD_REV register value repeated in each byte of the
> read buffer. This will in turn corrupt the values returned by the LTTPRs
> between the source and the monitor: LTTPRs must adjust the values they
> read from the downstream DPRX, for instance left-shift/init the
> downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> monitor's DPRX is non-zero the adjusted values will be corrupt.
>
> Reading the LTTPR registers one-by-one instead of reading all of them
> with a single AUX transfer works around the issue.
>
> According to the DP standard's 0xF0000 register description:
> "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> refers to the DPCD_REV or to the
> LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> at the VESA site to clarify this haven't been addressed), one
> possibility is that it's a restriction due to non-compliant monitors
> described above. Disabling the non-transparent LTTPR mode for all such
> monitors is not a viable solution: the transparent LTTPR mode has its
> own issue causing link training failures and this would affect a lot of
> monitors in use with DPCD_REV < 1.4. Instead this patch works around
> the problem by reading the LTTPR common and PHY cap registers one-by-one
> for any monitor with a DPCD_REV < 1.4.
>
> The standard requires the DPCD capabilites to be read after the LTTPR
> common capabilities are read, so re-read the DPCD capabilities after
> the LTTPR common and PHY caps were read out.
>
> v2:
> - Use for instead of a while loop. (Ville)
> - Add to code comment the monitor model with the problem.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/dp/drm_dp.c | 57 ++++++++++++-------
> .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> include/drm/dp/drm_dp_helper.h | 2 +
> 3 files changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c64..58744f83931af 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2390,9 +2390,35 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> + u8 *buf, int buf_size)
> +{
> + /*
> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
> + * corrupted values when reading from the 0xF0000- range with a block
> + * size bigger than 1.
> + */
> + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> + int offset;
> + int ret;
> +
> + for (offset = 0; offset < buf_size; offset += block_size) {
> + ret = drm_dp_dpcd_read(aux,
> + address + offset,
> + &buf[offset], block_size);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != block_size);
> + }
> +
> + return 0;
> +}
> +
> /**
> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> * @aux: DisplayPort AUX channel
> + * @dpcd: DisplayPort configuration data
> * @caps: buffer to return the capability info in
> *
> * Read capabilities common to all LTTPRs.
> @@ -2400,25 +2426,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> * Returns 0 on success or a negative error code on failure.
> */
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> {
> - int ret;
> -
> - ret = drm_dp_dpcd_read(aux,
> - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> - caps, DP_LTTPR_COMMON_CAP_SIZE);
> - if (ret < 0)
> - return ret;
> -
> - WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
> -
> - return 0;
> + return drm_dp_read_lttpr_regs(aux, dpcd,
> + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> + caps, DP_LTTPR_COMMON_CAP_SIZE);
> }
> EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
>
> /**
> * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
> * @aux: DisplayPort AUX channel
> + * @dpcd: DisplayPort configuration data
> * @dp_phy: LTTPR PHY to read the capabilities for
> * @caps: buffer to return the capability info in
> *
> @@ -2427,20 +2447,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
> * Returns 0 on success or a negative error code on failure.
> */
> int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy,
> u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> {
> - int ret;
> -
> - ret = drm_dp_dpcd_read(aux,
> - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> - caps, DP_LTTPR_PHY_CAP_SIZE);
> - if (ret < 0)
> - return ret;
> -
> - WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
> -
> - return 0;
> + return drm_dp_read_lttpr_regs(aux, dpcd,
> + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> + caps, DP_LTTPR_PHY_CAP_SIZE);
> }
> EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 5d98773efd1b3..fbee20a76cf44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
> }
>
> static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> @@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
>
> intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> - if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
> + if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> "[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
> encoder->base.base.id, encoder->base.name, phy_name);
> @@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
> phy_caps);
> }
>
> -static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> +static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + int ret;
>
> if (intel_dp_is_edp(intel_dp))
> return false;
> @@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
> return false;
>
> - if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
> - intel_dp->lttpr_common_caps) < 0)
> + ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
> + intel_dp->lttpr_common_caps);
> + if (ret < 0)
> goto reset_caps;
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> @@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
> return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
> }
>
> -static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> +static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> int lttpr_count;
> int i;
>
> - if (!intel_dp_read_lttpr_common_caps(intel_dp))
> + if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
> return 0;
>
> lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> @@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> }
>
> for (i = 0; i < lttpr_count; i++)
> - intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
> + intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
>
> return lttpr_count;
> }
> @@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> */
> int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> {
> - int lttpr_count = intel_dp_init_lttpr(intel_dp);
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> + int lttpr_count;
>
> - /* The DPTX shall read the DPRX caps after LTTPR detection. */
> + if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
> + return -EIO;
> +
> + lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> +
> + /*
> + * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> + * it here.
> + */
> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
> intel_dp_reset_lttpr_common_caps(intel_dp);
> return -EIO;
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index 51e02cf75277e..1eccd97419436 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy,
> u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
> --
> 2.30.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities
@ 2022-03-22 17:31 ` Ville Syrjälä
0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-03-22 17:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Tue, Mar 22, 2022 at 04:38:44PM +0200, Imre Deak wrote:
> At least some DELL monitors (P2715Q) with DPCD_REV 1.2 return corrupted
> DPCD register values when reading from the 0xF0000- LTTPR range with an
> AUX transaction block size bigger than 1. The DP standard requires 0 to
> be returned - as for any other reserved/invalid addresses - but these
> monitors return the DPCD_REV register value repeated in each byte of the
> read buffer. This will in turn corrupt the values returned by the LTTPRs
> between the source and the monitor: LTTPRs must adjust the values they
> read from the downstream DPRX, for instance left-shift/init the
> downstream DP_PHY_REPEATER_CNT value. Since the value returned by the
> monitor's DPRX is non-zero the adjusted values will be corrupt.
>
> Reading the LTTPR registers one-by-one instead of reading all of them
> with a single AUX transfer works around the issue.
>
> According to the DP standard's 0xF0000 register description:
> "LTTPR-related registers at DPCD Addresses F0000h through F02FFh are
> valid only for DPCD r1.4 (or higher)." While it's unclear if DPCD r1.4
> refers to the DPCD_REV or to the
> LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV register (tickets filed
> at the VESA site to clarify this haven't been addressed), one
> possibility is that it's a restriction due to non-compliant monitors
> described above. Disabling the non-transparent LTTPR mode for all such
> monitors is not a viable solution: the transparent LTTPR mode has its
> own issue causing link training failures and this would affect a lot of
> monitors in use with DPCD_REV < 1.4. Instead this patch works around
> the problem by reading the LTTPR common and PHY cap registers one-by-one
> for any monitor with a DPCD_REV < 1.4.
>
> The standard requires the DPCD capabilites to be read after the LTTPR
> common capabilities are read, so re-read the DPCD capabilities after
> the LTTPR common and PHY caps were read out.
>
> v2:
> - Use for instead of a while loop. (Ville)
> - Add to code comment the monitor model with the problem.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4531
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/dp/drm_dp.c | 57 ++++++++++++-------
> .../drm/i915/display/intel_dp_link_training.c | 30 +++++++---
> include/drm/dp/drm_dp_helper.h | 2 +
> 3 files changed, 58 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 703972ae14c64..58744f83931af 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -2390,9 +2390,35 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
> + u8 *buf, int buf_size)
> +{
> + /*
> + * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
> + * corrupted values when reading from the 0xF0000- range with a block
> + * size bigger than 1.
> + */
> + int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
> + int offset;
> + int ret;
> +
> + for (offset = 0; offset < buf_size; offset += block_size) {
> + ret = drm_dp_dpcd_read(aux,
> + address + offset,
> + &buf[offset], block_size);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != block_size);
> + }
> +
> + return 0;
> +}
> +
> /**
> * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> * @aux: DisplayPort AUX channel
> + * @dpcd: DisplayPort configuration data
> * @caps: buffer to return the capability info in
> *
> * Read capabilities common to all LTTPRs.
> @@ -2400,25 +2426,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> * Returns 0 on success or a negative error code on failure.
> */
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> {
> - int ret;
> -
> - ret = drm_dp_dpcd_read(aux,
> - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> - caps, DP_LTTPR_COMMON_CAP_SIZE);
> - if (ret < 0)
> - return ret;
> -
> - WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
> -
> - return 0;
> + return drm_dp_read_lttpr_regs(aux, dpcd,
> + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> + caps, DP_LTTPR_COMMON_CAP_SIZE);
> }
> EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
>
> /**
> * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
> * @aux: DisplayPort AUX channel
> + * @dpcd: DisplayPort configuration data
> * @dp_phy: LTTPR PHY to read the capabilities for
> * @caps: buffer to return the capability info in
> *
> @@ -2427,20 +2447,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
> * Returns 0 on success or a negative error code on failure.
> */
> int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy,
> u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> {
> - int ret;
> -
> - ret = drm_dp_dpcd_read(aux,
> - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> - caps, DP_LTTPR_PHY_CAP_SIZE);
> - if (ret < 0)
> - return ret;
> -
> - WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
> -
> - return 0;
> + return drm_dp_read_lttpr_regs(aux, dpcd,
> + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> + caps, DP_LTTPR_PHY_CAP_SIZE);
> }
> EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 5d98773efd1b3..fbee20a76cf44 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -55,6 +55,7 @@ static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
> }
>
> static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> @@ -63,7 +64,7 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
>
> intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
>
> - if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
> + if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> "[ENCODER:%d:%s][%s] failed to read the PHY caps\n",
> encoder->base.base.id, encoder->base.name, phy_name);
> @@ -77,10 +78,11 @@ static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
> phy_caps);
> }
>
> -static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> +static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + int ret;
>
> if (intel_dp_is_edp(intel_dp))
> return false;
> @@ -92,8 +94,9 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
> return false;
>
> - if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
> - intel_dp->lttpr_common_caps) < 0)
> + ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
> + intel_dp->lttpr_common_caps);
> + if (ret < 0)
> goto reset_caps;
>
> drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> @@ -122,14 +125,14 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
> return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
> }
>
> -static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> +static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> int lttpr_count;
> int i;
>
> - if (!intel_dp_read_lttpr_common_caps(intel_dp))
> + if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
> return 0;
>
> lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> @@ -168,7 +171,7 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> }
>
> for (i = 0; i < lttpr_count; i++)
> - intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
> + intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
>
> return lttpr_count;
> }
> @@ -193,9 +196,18 @@ static int intel_dp_init_lttpr(struct intel_dp *intel_dp)
> */
> int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
> {
> - int lttpr_count = intel_dp_init_lttpr(intel_dp);
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> + int lttpr_count;
>
> - /* The DPTX shall read the DPRX caps after LTTPR detection. */
> + if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
> + return -EIO;
> +
> + lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
> +
> + /*
> + * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
> + * it here.
> + */
> if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
> intel_dp_reset_lttpr_common_caps(intel_dp);
> return -EIO;
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index 51e02cf75277e..1eccd97419436 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -2148,8 +2148,10 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>
> int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> enum drm_dp_phy dp_phy,
> u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
> --
> 2.30.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
` (7 preceding siblings ...)
(?)
@ 2022-03-22 21:50 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-03-22 21:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30294 bytes --]
== Series Details ==
Series: drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2)
URL : https://patchwork.freedesktop.org/series/100851/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11396_full -> Patchwork_22643_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22643_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_softpin@overlap:
- {shard-rkl}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@gem_softpin@overlap.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-5/igt@gem_softpin@overlap.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-random:
- {shard-rkl}: [SKIP][3] ([fdo#112022] / [i915#4070]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-128x42-random.html
Known issues
------------
Here are the changes found in Patchwork_22643_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-1us:
- shard-iclb: [PASS][5] -> [TIMEOUT][6] ([i915#3070])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb2/igt@gem_eio@in-flight-contexts-1us.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb4/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl8/igt@gem_eio@in-flight-contexts-immediate.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl5/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-kbl: NOTRUN -> [DMESG-FAIL][11] ([i915#5076])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][12] ([i915#4547])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl1/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-apl: [PASS][18] -> [INCOMPLETE][19] ([i915#5268])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-apl4/igt@gem_exec_whisper@basic-fds-priority-all.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl2/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271]) +61 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3323])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271]) +215 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#118])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-glk3/igt@kms_big_fb@linear-32bpp-rotate-0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3777]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][28] ([i915#3743]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3763])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +6 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +4 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +18 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl1/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +9 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +5 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][38] ([i915#1319])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl2/igt@kms_content_protection@lic.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#533]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl10/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk1/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: NOTRUN -> [FAIL][41] ([i915#79]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][42] -> [DMESG-WARN][43] ([i915#180]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][44] ([i915#3701])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
- shard-iclb: [PASS][45] -> [SKIP][46] ([i915#3701])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271]) +111 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a:
- shard-skl: NOTRUN -> [FAIL][48] ([i915#1188])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][49] -> [DMESG-WARN][50] ([i915#180]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-apl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][57] -> [SKIP][58] ([i915#5235]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#658])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][61] -> [SKIP][62] ([fdo#109642] / [fdo#111068] / [i915#658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][64] -> [SKIP][65] ([fdo#109441]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][66] ([IGT#2])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl10/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][69] -> [FAIL][70] ([i915#1542])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl7/igt@perf@polling-parameterized.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl1/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle-many:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2994])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl10/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2994]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl2/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2994]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@sysfs_clients@sema-50.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-apl: [PASS][74] -> [FAIL][75] ([i915#1755])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-apl3/igt@sysfs_timeslice_duration@timeout@vecs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl6/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Possible fixes ####
* igt@fbdev@eof:
- {shard-rkl}: [SKIP][76] ([i915#2582]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@fbdev@eof.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@fbdev@eof.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][78] ([i915#2410]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@gem_ctx_persistence@many-contexts.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [INCOMPLETE][80] ([i915#4547]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl4/igt@gem_exec_capture@pi@bcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl1/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [FAIL][82] ([i915#2842]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][84] ([i915#2849]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_nop@basic-series:
- shard-glk: [DMESG-WARN][86] ([i915#118]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-glk1/igt@gem_exec_nop@basic-series.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk4/igt@gem_exec_nop@basic-series.html
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [DMESG-FAIL][88] -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-glk7/igt@gem_exec_whisper@basic-fds-forked-all.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk1/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][90] ([i915#454]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {shard-rkl}: [SKIP][92] ([fdo#109308]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@i915_pm_rpm@basic-pci-d3-state.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][94] ([i915#1397]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@kms_color@pipe-a-ctm-0-5:
- {shard-rkl}: [SKIP][96] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@kms_color@pipe-a-ctm-0-5.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color@pipe-b-gamma:
- {shard-rkl}: [SKIP][98] ([i915#1149] / [i915#1849] / [i915#4098]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@kms_color@pipe-b-gamma.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_color@pipe-b-gamma.html
* igt@kms_color@pipe-c-invalid-gamma-lut-sizes:
- {shard-rkl}: [SKIP][100] ([i915#4070]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-6/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-5/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][102] ([i915#180]) -> [PASS][103] +4 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- {shard-rkl}: [SKIP][104] ([fdo#112022]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-random:
- {shard-rkl}: [SKIP][106] ([fdo#112022] / [i915#4070]) -> [PASS][107] +8 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge:
- {shard-rkl}: [SKIP][110] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][111] +3 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
- {shard-rkl}: [SKIP][112] ([fdo#111825] / [i915#4070]) -> [PASS][113] +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][114] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][115] +5 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][116] ([i915#180] / [i915#636]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][118] ([i915#2122]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][120] ([i915#2122]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- {shard-rkl}: [SKIP][122] ([i915#1849]) -> [PASS][123] +24 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
- shard-skl: [FAIL][124] ([i915#1188]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-skl10/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-skl7/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
* igt@kms_invalid_mode@bad-vsync-end:
- {shard-rkl}: [SKIP][126] ([i915#4278]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@kms_invalid_mode@bad-vsync-end.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_invalid_mode@bad-vsync-end.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {shard-rkl}: [SKIP][128] ([i915#1849] / [i915#4098]) -> [PASS][129] +2 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right@pipe-b-planes:
- {shard-rkl}: [SKIP][130] ([i915#3558]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right@pipe-b-planes.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-b-planes.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- {shard-rkl}: [SKIP][132] ([i915#3558] / [i915#4070]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-b-tiling-y.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [SKIP][134] ([i915#5235]) -> [PASS][135] +2 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb3/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [SKIP][136] ([i915#5176]) -> [PASS][137] +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-iclb5/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][138] ([i915#1072]) -> [PASS][139] +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-rkl-5/igt@kms_psr@cursor_render.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][140] ([fdo#109441]) -> [PASS][141] +2 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11396/shard-iclb1/igt@kms_psr@psr
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22643/index.html
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^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-03-22 21:50 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-28 20:12 [PATCH] drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities Imre Deak
2022-02-28 20:12 ` [Intel-gfx] " Imre Deak
2022-03-01 0:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-03-01 1:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-01 14:14 ` [PATCH] " Ville Syrjälä
2022-03-01 14:14 ` [Intel-gfx] " Ville Syrjälä
2022-03-01 18:14 ` Imre Deak
2022-03-01 18:14 ` [Intel-gfx] " Imre Deak
2022-03-01 18:24 ` Ville Syrjälä
2022-03-01 18:24 ` [Intel-gfx] " Ville Syrjälä
2022-03-22 14:38 ` [PATCH v2] " Imre Deak
2022-03-22 14:38 ` [Intel-gfx] " Imre Deak
2022-03-22 17:31 ` Ville Syrjälä
2022-03-22 17:31 ` [Intel-gfx] " Ville Syrjälä
2022-03-22 14:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add a DP1.2 compatible way to read LTTPR capabilities (rev2) Patchwork
2022-03-22 14:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-22 15:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-22 21:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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